blob: f6e40def518688d4da8c4f00320ecc66041f3260 [file] [log] [blame]
Heiko Schocherca43ba12007-01-11 15:44:44 +01001/*
2 * (C) Copyright 2007
3 * Heiko Schocher, DENX Software Engineering, <hs@denx.de>.
4 *
5 * From:
6 * (C) Copyright 2003
7 * Juergen Beisert, EuroDesign embedded technologies, jbeisert@eurodsn.de
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31#undef USE_VGA_GRAPHICS
32
33/* Memory Map
Wolfgang Denk6d3e0102007-01-16 18:30:50 +010034 * 0x00000000 .... 0x03FFFFFF -> RAM (up to 128MiB)
35 * 0x74000000 .... 0x740FFFFF -> CS#6
36 * 0x74100000 .... 0x741FFFFF -> CS#7
37 * 0x74200000 .... 0x742FFFFF -> CS4# if no internal USB
38 * 0x74300000 .... 0x743FFFFF -> CS5# if no boosted IDE
39 * 0x77C00000 .... 0x77CFFFFF -> CS4# USB HC (1 MiB)
40 * 0x77D00000 .... 0x77DFFFFF -> CS1# NAND-Flash (1 MiB)
41 * 0x78000000 .... 0x78FFFFFF -> CS2# ISA-Bus Speicherzugriff (16 MiB)
42 * 0x79000000 .... 0x7900FFFF -> CS2# ISA-Bus IO-Zugriff (16 MiB, mapped: 64kiB)
43 * 0x79010000 .... 0x79FFFFFF -> CS2# ISA-Bus IO-Zugriff (mirrored)
44 * 0x7A000000 .... 0x7A0FFFFF -> CS5# IDE emulation (1MiB)
45 *
46 * 0x80000000 .... 0x9FFFFFFF -> PCI-Bus Speicherzugriff (512MiB, mapped: 1:1)
47 * 0xA0000000 .... 0xBFFFFFFF -> PCI-Bus Speicherzugriff (512MiB, mapped: 0x00000000...0x1FFFFFFF)
48 * 0xE8000000 .... 0xE800FFFF -> PCI-Bus IO-Zugriff (64kiB, translated to PCI: 0x0000...0xFFFF)
49 * 0xE8800000 .... 0xEBFFFFFF -> PCI-Bus IO-Zugriff (56MiB, translated to PCI: 0x00800000...0x3FFFFFF)
50 * 0xEED00000 .... 0xEED00003 -> PCI-Bus
51 * 0xEF400000 .... 0xEF40003F -> PCI-Bus Local Configuration Registers
52 * 0xEF40003F .... 0xEF5FFFFF -> reserved
53 * 0xEF600000 .... 0xEFFFFFFF -> 405GP internal Devices (10 MiB)
54 * 0xF0000000 .... 0xF01FFFFF -> Flash-ROM (2 MiB)
55 * 0xF0200000 .... 0xF7FFFFFF -> free for flash devices
56 * 0xF8000000 .... 0xF8000FFF -> OnChipMemory (4kiB)
57 * 0xF8001000 .... 0xFFDFFFFF -> free for flash devices
58 * 0xFFE00000 .... 0xFFFFFFFF -> BOOT-ROM (2 MiB)
59 */
Heiko Schocherca43ba12007-01-11 15:44:44 +010060
Wolfgang Denk9045f332007-06-08 10:24:58 +020061#define CONFIG_SC3 1
Heiko Schocherca43ba12007-01-11 15:44:44 +010062#define CONFIG_4xx 1
63#define CONFIG_405GP 1
64
65#define CONFIG_BOARD_EARLY_INIT_F 1
66
67/*
Wolfgang Denk6d3e0102007-01-16 18:30:50 +010068 * Define IDE_USES_ISA_EMULATION for slower IDE access in the ISA-IO address range
69 * If undefined, IDE access uses a seperat emulation with higher access speed.
Heiko Schocherca43ba12007-01-11 15:44:44 +010070 * Consider to inform your Linux IDE driver about the different addresses!
Jon Loeliger639221c2007-07-09 17:15:49 -050071 * IDE_USES_ISA_EMULATION is only used if you define CONFIG_CMD_IDE!
Heiko Schocherca43ba12007-01-11 15:44:44 +010072 */
73#define IDE_USES_ISA_EMULATION
74
75/*-----------------------------------------------------------------------
76 * Serial Port
77 *----------------------------------------------------------------------*/
78#define CONFIG_SERIAL_MULTI
79#undef CONFIG_SERIAL_SOFTWARE_FIFO
80/*
81 * define CONFIG_POWER_DOWN if your cpu should power down while waiting for your input
82 * Works only, if you have enabled the CONFIG_SERIAL_SOFTWARE_FIFO feature
83 */
84#if CONFIG_SERIAL_SOFTWARE_FIFO
85 #define CONFIG_POWER_DOWN
86#endif
87
88/*
89 * define CONFIG_SYS_CLK_FREQ to your base crystal clock in Hz
90 */
91#define CONFIG_SYS_CLK_FREQ 33333333
92
93/*
94 * define CONFIG_BAUDRATE to the baudrate value you want to use as default
95 */
96#define CONFIG_BAUDRATE 115200
Wolfgang Denkf11033e2007-01-15 13:41:04 +010097#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
Heiko Schocherca43ba12007-01-11 15:44:44 +010098
Wolfgang Denk1bbbbdd2007-01-16 12:46:35 +010099#define CONFIG_PREBOOT "echo;" \
Wolfgang Denk32bf3d12008-03-03 12:16:44 +0100100 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
Wolfgang Denk1bbbbdd2007-01-16 12:46:35 +0100101 "echo"
102
103#undef CONFIG_BOOTARGS
104
105#define CONFIG_EXTRA_ENV_SETTINGS \
106 "netdev=eth0\0" \
107 "nfsargs=setenv bootargs root=/dev/nfs rw " \
108 "nfsroot=${serverip}:${rootpath}\0" \
109 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Heiko Schochercb482072007-01-18 11:28:51 +0100110 "nand_args=setenv bootargs root=/dev/mtdblock5 rw" \
111 "rootfstype=jffs2\0" \
Wolfgang Denk1bbbbdd2007-01-16 12:46:35 +0100112 "addip=setenv bootargs ${bootargs} " \
113 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
114 ":${hostname}:${netdev}:off panic=1\0" \
Wolfgang Denka7090b92007-03-13 16:05:55 +0100115 "addcons=setenv bootargs ${bootargs} " \
116 "console=ttyS0,${baudrate}\0" \
117 "flash_nfs=run nfsargs addip addcons;" \
Wolfgang Denk1bbbbdd2007-01-16 12:46:35 +0100118 "bootm ${kernel_addr}\0" \
Wolfgang Denka7090b92007-03-13 16:05:55 +0100119 "flash_nand=run nand_args addip addcons;bootm ${kernel_addr}\0" \
120 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addcons;" \
121 "bootm\0" \
Wolfgang Denk1bbbbdd2007-01-16 12:46:35 +0100122 "rootpath=/opt/eldk/ppc_4xx\0" \
123 "bootfile=/tftpboot/sc3/uImage\0" \
Heiko Schocherd0b6e142007-01-19 18:05:26 +0100124 "u-boot=/tftpboot/sc3/u-boot.bin\0" \
125 "setup=tftp 200000 /tftpboot/sc3/setup.img;autoscr 200000\0" \
Wolfgang Denk1bbbbdd2007-01-16 12:46:35 +0100126 "kernel_addr=FFE08000\0" \
127 ""
128#undef CONFIG_BOOTCOMMAND
129
Heiko Schocherca43ba12007-01-11 15:44:44 +0100130#define CONFIG_SILENT_CONSOLE 1 /* enable silent startup */
131#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */
132
133#if 1 /* feel free to disable for development */
134#define CONFIG_AUTOBOOT_KEYED /* Enable password protection */
Wolfgang Denk51056dd2007-04-11 17:22:55 +0200135#define CONFIG_AUTOBOOT_PROMPT "\nSC3 - booting... stop with ENTER\n"
Wolfgang Denk9045f332007-06-08 10:24:58 +0200136#define CONFIG_AUTOBOOT_DELAY_STR "\r" /* 1st "password" */
137#define CONFIG_AUTOBOOT_DELAY_STR2 "\n" /* 1st "password" */
Heiko Schocherca43ba12007-01-11 15:44:44 +0100138#endif
139
140/*
141 * define CONFIG_BOOTCOMMAND to the autoboot commands. They will running after
142 * the CONFIG_BOOTDELAY delay to boot your machine
143 */
144#define CONFIG_BOOTCOMMAND "bootp;dcache on;bootm"
145
146/*
147 * define CONFIG_BOOTARGS to the default kernel parameters. They will used if you don't
148 * set different values at the u-boot prompt
149 */
150#ifdef USE_VGA_GRAPHICS
151 #define CONFIG_BOOTARGS "root=/dev/nfs rw ip=bootp nfsroot=/tftpboot/solidcard3re"
152#else
153 #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/nfs rw ip=bootp"
154#endif
155/*
156 * Is the USB host controller assembled? If yes define CONFIG_ISP1161_PRESENT
157 * This reserves memory bank #4 for this purpose
158 */
159#undef CONFIG_ISP1161_PRESENT
160
161#undef CONFIG_LOADS_ECHO /* no echo on for serial download */
162#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
163
164#define CONFIG_NET_MULTI
165/* #define CONFIG_EEPRO100_SROM_WRITE */
166/* #define CONFIG_SHOW_MAC */
167#define CONFIG_EEPRO100
168#define CONFIG_MII 1 /* add 405GP MII PHY management */
169#define CONFIG_PHY_ADDR 1 /* the connected Phy defaults to address 1 */
170
Jon Loeliger46da1e92007-07-04 22:33:30 -0500171/*
Jon Loeliger079a1362007-07-10 10:12:10 -0500172 * BOOTP options
173 */
174#define CONFIG_BOOTP_BOOTFILESIZE
175#define CONFIG_BOOTP_BOOTPATH
176#define CONFIG_BOOTP_GATEWAY
177#define CONFIG_BOOTP_HOSTNAME
178
179
180/*
Jon Loeliger46da1e92007-07-04 22:33:30 -0500181 * Command line configuration.
182 */
183#include <config_cmd_default.h>
Heiko Schocherca43ba12007-01-11 15:44:44 +0100184
Jon Loeliger46da1e92007-07-04 22:33:30 -0500185
186#define CONFIG_CMD_AUTOSCRIPT
187#define CONFIG_CMD_PCI
188#define CONFIG_CMD_IRQ
189#define CONFIG_CMD_NET
190#define CONFIG_CMD_MII
191#define CONFIG_CMD_PING
192#define CONFIG_CMD_NAND
193#define CONFIG_CMD_JFFS2
194#define CONFIG_CMD_I2C
195#define CONFIG_CMD_IDE
196#define CONFIG_CMD_DATE
197#define CONFIG_CMD_DHCP
198#define CONFIG_CMD_CACHE
199#define CONFIG_CMD_ELF
200
Heiko Schocherca43ba12007-01-11 15:44:44 +0100201
202#undef CONFIG_WATCHDOG /* watchdog disabled */
203
204/*
205 * Miscellaneous configurable options
206 */
207#define CFG_LONGHELP 1 /* undef to save memory */
208#define CFG_PROMPT "SC3> " /* Monitor Command Prompt */
209#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
210
211#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
212
213#define CFG_MAXARGS 16 /* max number of command args */
214#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
215
216#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
217#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
218
219/*
220 * If CFG_EXT_SERIAL_CLOCK, then the UART divisor is 1.
221 * If CFG_405_UART_ERRATA_59, then UART divisor is 31.
222 * Otherwise, UART divisor is determined by CPU Clock and CFG_BASE_BAUD value.
223 * The Linux BASE_BAUD define should match this configuration.
224 * baseBaud = cpuClock/(uartDivisor*16)
225 * If CFG_405_UART_ERRATA_59 and 200MHz CPU clock,
226 * set Linux BASE_BAUD to 403200.
227 *
228 * Consider the OPB clock! If it get lower the BASE_BAUD must be lower to
229 * (see 405GP datasheet for descritpion)
230 */
Wolfgang Denkf11033e2007-01-15 13:41:04 +0100231#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
232#undef CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
Heiko Schocherca43ba12007-01-11 15:44:44 +0100233#define CFG_BASE_BAUD 921600 /* internal clock */
234
235/* The following table includes the supported baudrates */
236#define CFG_BAUDRATE_TABLE \
237 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400}
238
239#define CFG_LOAD_ADDR 0x1000000 /* default load address */
240#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
241
242#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
243
244/*-----------------------------------------------------------------------
245 * IIC stuff
246 *-----------------------------------------------------------------------
247 */
248#define CONFIG_HARD_I2C /* I2C with hardware support */
Wolfgang Denkf11033e2007-01-15 13:41:04 +0100249#undef CONFIG_SOFT_I2C /* I2C bit-banged */
Heiko Schocherca43ba12007-01-11 15:44:44 +0100250
251#define I2C_INIT
252#define I2C_ACTIVE 0
253#define I2C_TRISTATE 0
254
255#define CFG_I2C_SPEED 100000 /* use the standard 100kHz speed */
256#define CFG_I2C_SLAVE 0x7F /* mask valid bits */
257
258#define CONFIG_RTC_DS1337
259#define CFG_I2C_RTC_ADDR 0x68
260
261/*-----------------------------------------------------------------------
262 * PCI stuff
263 *-----------------------------------------------------------------------
264 */
Wolfgang Denkf11033e2007-01-15 13:41:04 +0100265#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
266#define PCI_HOST_FORCE 1 /* configure as pci host */
267#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
Heiko Schocherca43ba12007-01-11 15:44:44 +0100268
Wolfgang Denkf11033e2007-01-15 13:41:04 +0100269#define CONFIG_PCI /* include pci support */
270#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
271#define CONFIG_PCI_PNP /* do pci plug-and-play */
272 /* resource configuration */
Heiko Schocherca43ba12007-01-11 15:44:44 +0100273
274/* If you want to see, whats connected to your PCI bus */
275/* #define CONFIG_PCI_SCAN_SHOW */
276
Wolfgang Denkf11033e2007-01-15 13:41:04 +0100277#define CFG_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */
278#define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */
279#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
280#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
281#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
282#define CFG_PCI_PTM2LA 0x00000000 /* disabled */
283#define CFG_PCI_PTM2MS 0x00000000 /* disabled */
284#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
Heiko Schocherca43ba12007-01-11 15:44:44 +0100285
286/*-----------------------------------------------------------------------
287 * External peripheral base address
288 *-----------------------------------------------------------------------
289 */
Jon Loeliger46da1e92007-07-04 22:33:30 -0500290#if !defined(CONFIG_CMD_IDE)
Heiko Schocherca43ba12007-01-11 15:44:44 +0100291
Wolfgang Denkf11033e2007-01-15 13:41:04 +0100292#undef CONFIG_IDE_LED /* no led for ide supported */
293#undef CONFIG_IDE_RESET /* no reset for ide supported */
Heiko Schocherca43ba12007-01-11 15:44:44 +0100294
295/*-----------------------------------------------------------------------
296 * IDE/ATA stuff
297 *-----------------------------------------------------------------------
298 */
Jon Loeliger46da1e92007-07-04 22:33:30 -0500299#else
Heiko Schocherca43ba12007-01-11 15:44:44 +0100300#define CONFIG_START_IDE 1 /* check, if use IDE */
301
Wolfgang Denkf11033e2007-01-15 13:41:04 +0100302#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
303#undef CONFIG_IDE_LED /* no led for ide supported */
304#undef CONFIG_IDE_RESET /* no reset for ide supported */
Heiko Schocherca43ba12007-01-11 15:44:44 +0100305
306#define CONFIG_ATAPI
307#define CONFIG_DOS_PARTITION
308#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
309
310#ifndef IDE_USES_ISA_EMULATION
311
312/* New and faster access */
313#define CFG_ATA_BASE_ADDR 0x7A000000 /* start of ISA IO emulation */
314
315/* How many IDE busses are available */
316#define CFG_IDE_MAXBUS 1
317
318/* What IDE ports are available */
319#define CFG_ATA_IDE0_OFFSET 0x000 /* first is available */
320#undef CFG_ATA_IDE1_OFFSET /* second not available */
321
322/* access to the data port is calculated:
323 CFG_ATA_BASE_ADDR + CFG_ATA_IDE0_OFFSET + CFG_ATA_DATA_OFFSET + 0 */
324#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
325
326/* access to the registers is calculated:
327 CFG_ATA_BASE_ADDR + CFG_ATA_IDE0_OFFSET + CFG_ATA_REG_OFFSET + [1..7] */
328#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
329
330/* access to the alternate register is calculated:
331 CFG_ATA_BASE_ADDR + CFG_ATA_IDE0_OFFSET + CFG_ATA_ALT_OFFSET + 6 */
332#define CFG_ATA_ALT_OFFSET 0x008 /* Offset for alternate registers */
333
334#else /* IDE_USES_ISA_EMULATION */
335
336#define CFG_ATA_BASE_ADDR 0x79000000 /* start of ISA IO emulation */
337
338/* How many IDE busses are available */
339#define CFG_IDE_MAXBUS 1
340
341/* What IDE ports are available */
342#define CFG_ATA_IDE0_OFFSET 0x01F0 /* first is available */
343#undef CFG_ATA_IDE1_OFFSET /* second not available */
344
345/* access to the data port is calculated:
346 CFG_ATA_BASE_ADDR + CFG_ATA_IDE0_OFFSET + CFG_ATA_DATA_OFFSET + 0 */
347#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
348
349/* access to the registers is calculated:
350 CFG_ATA_BASE_ADDR + CFG_ATA_IDE0_OFFSET + CFG_ATA_REG_OFFSET + [1..7] */
351#define CFG_ATA_REG_OFFSET 0x0000 /* Offset for normal register accesses */
352
353/* access to the alternate register is calculated:
354 CFG_ATA_BASE_ADDR + CFG_ATA_IDE0_OFFSET + CFG_ATA_ALT_OFFSET + 6 */
355#define CFG_ATA_ALT_OFFSET 0x03F0 /* Offset for alternate registers */
356
357#endif /* IDE_USES_ISA_EMULATION */
358
Jon Loeliger46da1e92007-07-04 22:33:30 -0500359#endif
Heiko Schocherca43ba12007-01-11 15:44:44 +0100360
361/*
362#define CFG_KEY_REG_BASE_ADDR 0xF0100000
363#define CFG_IR_REG_BASE_ADDR 0xF0200000
364#define CFG_FPGA_REG_BASE_ADDR 0xF0300000
365*/
366
367/*-----------------------------------------------------------------------
368 * Start addresses for the final memory configuration
369 * (Set up by the startup code)
370 * Please note that CFG_SDRAM_BASE _must_ start at 0
371 *
372 * CFG_FLASH_BASE -> start address of internal flash
373 * CFG_MONITOR_BASE -> start of u-boot
374 */
375#ifndef __ASSEMBLER__
376extern unsigned long offsetOfBigFlash;
377extern unsigned long offsetOfEnvironment;
378#endif
379
380#define CFG_SDRAM_BASE 0x00000000
381#define CFG_FLASH_BASE 0xFFE00000
382#define CFG_MONITOR_BASE 0xFFFC0000 /* placed last 256k */
383#define CFG_MONITOR_LEN (224 * 1024) /* Reserve 224 KiB for Monitor */
384#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 KiB for malloc() */
385
386/*
387 * For booting Linux, the board info and command line data
388 * have to be in the first 8 MiB of memory, since this is
389 * the maximum mapped by the Linux kernel during initialization.
390 */
391#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
392/*-----------------------------------------------------------------------
Wolfgang Denkf11033e2007-01-15 13:41:04 +0100393 * FLASH organization ## FIXME: lookup in datasheet
Heiko Schocherca43ba12007-01-11 15:44:44 +0100394 */
395#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
396#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
397
398#define CFG_FLASH_CFI /* flash is CFI compat. */
399#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver*/
400#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector */
401#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash*/
402#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
403#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
Heiko Schocherd0b6e142007-01-19 18:05:26 +0100404#define CFG_WRITE_SWAPPED_DATA /* swap Databytes between reading/writing */
Heiko Schocherca43ba12007-01-11 15:44:44 +0100405
406#define CFG_ENV_IS_IN_FLASH 1
407#if CFG_ENV_IS_IN_FLASH
Wolfgang Denk6d3e0102007-01-16 18:30:50 +0100408#define CFG_ENV_OFFSET 0x00000000 /* Offset of Environment Sector in bottom type */
409#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
410#define CFG_ENV_SECT_SIZE 0x4000 /* see README - env sector total size */
411
412/* Address and size of Redundant Environment Sector */
413#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
414#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
415
Heiko Schocherca43ba12007-01-11 15:44:44 +0100416#endif
417/* let us changing anything in our environment */
418#define CONFIG_ENV_OVERWRITE
419
420/*
421 * NAND-FLASH stuff
422 */
423#define CFG_MAX_NAND_DEVICE 1
424#define NAND_MAX_CHIPS 1
425#define CFG_NAND_BASE 0x77D00000
426
Heiko Schochercb482072007-01-18 11:28:51 +0100427
428#define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */
429
Wolfgang Denk51056dd2007-04-11 17:22:55 +0200430/* No command line, one static partition */
Heiko Schochercb482072007-01-18 11:28:51 +0100431#undef CONFIG_JFFS2_CMDLINE
432#define CONFIG_JFFS2_DEV "nand0"
Wolfgang Denk51056dd2007-04-11 17:22:55 +0200433#define CONFIG_JFFS2_PART_SIZE 0x01000000
434#define CONFIG_JFFS2_PART_OFFSET 0x00000000
Heiko Schochercb482072007-01-18 11:28:51 +0100435
Heiko Schocherca43ba12007-01-11 15:44:44 +0100436/*
437 * Init Memory Controller:
438 *
439 */
440
441#define FLASH_BASE0_PRELIM CFG_FLASH_BASE
442#define FLASH_BASE1_PRELIM 0
443
444/*-----------------------------------------------------------------------
445 * Some informations about the internal SRAM (OCM=On Chip Memory)
446 *
447 * CFG_OCM_DATA_ADDR -> location
448 * CFG_OCM_DATA_SIZE -> size
449*/
450
451#define CFG_TEMP_STACK_OCM 1
452#define CFG_OCM_DATA_ADDR 0xF8000000
453#define CFG_OCM_DATA_SIZE 0x1000
454
455/*-----------------------------------------------------------------------
456 * Definitions for initial stack pointer and data area (in DPRAM):
457 * - we are using the internal 4k SRAM, so we don't need data cache mapping
458 * - internal SRAM (OCM=On Chip Memory) is placed to CFG_OCM_DATA_ADDR
459 * - Stackpointer will be located to
460 * (CFG_INIT_RAM_ADDR&0xFFFF0000) | (CFG_INIT_SP_OFFSET&0x0000FFFF)
461 * in cpu/ppc4xx/start.S
462 */
463
464#undef CFG_INIT_DCACHE_CS
465/* Where the internal SRAM starts */
Wolfgang Denkf11033e2007-01-15 13:41:04 +0100466#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR
Heiko Schocherca43ba12007-01-11 15:44:44 +0100467/* Where the internal SRAM ends (only offset) */
Wolfgang Denkf11033e2007-01-15 13:41:04 +0100468#define CFG_INIT_RAM_END 0x0F00
Heiko Schocherca43ba12007-01-11 15:44:44 +0100469
470/*
471
472 CFG_INIT_RAM_ADDR ------> ------------ lower address
Wolfgang Denkf11033e2007-01-15 13:41:04 +0100473 | |
474 | ^ |
475 | | |
476 | | Stack |
Heiko Schocherca43ba12007-01-11 15:44:44 +0100477 CFG_GBL_DATA_OFFSET ----> ------------
Wolfgang Denkf11033e2007-01-15 13:41:04 +0100478 | |
479 | 64 Bytes |
480 | |
Heiko Schocherca43ba12007-01-11 15:44:44 +0100481 CFG_INIT_RAM_END ------> ------------ higher address
482 (offset only)
483
484*/
485/* size in bytes reserved for initial data */
486#define CFG_GBL_DATA_SIZE 64
487#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
488/* Initial value of the stack pointern in internal SRAM */
489#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
490
491/*
492 * Internal Definitions
493 *
494 * Boot Flags
495 */
496#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
497#define BOOTFLAG_WARM 0x02 /* Software reboot */
498
499/* ################################################################################### */
500/* These defines will be used in cpu/ppc4xx/cpu_init.c to setup external chip selects */
501/* They are currently undefined cause they are initiaized in board/solidcard3/init.S */
502
503/* This chip select accesses the boot device */
504/* It depends on boot select switch if this device is 16 or 8 bit */
505
506#undef CFG_EBC_PB0AP
507#undef CFG_EBC_PB0CR
508
509#undef CFG_EBC_PB1AP
510#undef CFG_EBC_PB1CR
511
512#undef CFG_EBC_PB2AP
513#undef CFG_EBC_PB2CR
514
515#undef CFG_EBC_PB3AP
516#undef CFG_EBC_PB3CR
517
518#undef CFG_EBC_PB4AP
519#undef CFG_EBC_PB4CR
520
521#undef CFG_EBC_PB5AP
522#undef CFG_EBC_PB5CR
523
524#undef CFG_EBC_PB6AP
525#undef CFG_EBC_PB6CR
526
527#undef CFG_EBC_PB7AP
528#undef CFG_EBC_PB7CR
529
Heiko Schochercb482072007-01-18 11:28:51 +0100530#define CFG_EBC_CFG 0xb84ef000
531
Heiko Schocherca43ba12007-01-11 15:44:44 +0100532#define CONFIG_SDRAM_BANK0 /* use the standard SDRAM initialization */
533#undef CONFIG_SPD_EEPROM
534
535/*
536 * Define this to get more information about system configuration
537 */
538/* #define SC3_DEBUGOUT */
539#undef SC3_DEBUGOUT
540
541/***********************************************************************
542 * External peripheral base address
543 ***********************************************************************/
544
545#define CFG_ISA_MEM_BASE_ADDRESS 0x78000000
546/*
547 Die Grafik-Treiber greifen über die Adresse in diesem Macro auf den Chip zu.
548 Das funktioniert bei deren Karten, weil sie eine PCI-Bridge benutzen, die
549 das gleiche Mapping durchführen kann, wie der SC520 (also Aufteilen von IO-Zugriffen
550 auf ISA- und PCI-Zyklen)
551 */
552#define CFG_ISA_IO_BASE_ADDRESS 0xE8000000
553/*#define CFG_ISA_IO_BASE_ADDRESS 0x79000000 */
554
555/************************************************************
556 * Video support
557 ************************************************************/
558
559#ifdef USE_VGA_GRAPHICS
560#define CONFIG_VIDEO /* To enable video controller support */
561#define CONFIG_VIDEO_CT69000
562#define CONFIG_CFB_CONSOLE
563/* #define CONFIG_VIDEO_LOGO */
564#define CONFIG_VGA_AS_SINGLE_DEVICE
565#define CONFIG_VIDEO_SW_CURSOR
566/* #define CONFIG_VIDEO_HW_CURSOR */
567#define CONFIG_VIDEO_ONBOARD /* Video controller is on-board */
568
569#define VIDEO_HW_RECTFILL
570#define VIDEO_HW_BITBLT
571
572#endif
573
574/************************************************************
575 * Ident
576 ************************************************************/
577#define CONFIG_SC3_VERSION "r1.4"
578
579#define POST_OUT(x) (*((volatile unsigned char*)(0x79000080))=x)
580
581#endif /* __CONFIG_H */