blob: 4ed7313683d9e990b614053032bebd77274e25c4 [file] [log] [blame]
Jagan Tekie9dfa1e2017-02-24 15:32:54 +05301/*
2 * Copyright (C) 2016 Amarula Solutions B.V.
3 * Copyright (C) 2016 Engicam S.r.l.
4 *
5 * This file is dual-licensed: you can use it either under the terms
6 * of the GPL or the X11 license, at your option. Note that this dual
7 * licensing only applies to this file, and not this project as a
8 * whole.
9 *
10 * a) This file is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * version 2 as published by the Free Software Foundation.
13 *
14 * This file is distributed in the hope that it will be useful
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */
42
Jagan Tekie9dfa1e2017-02-24 15:32:54 +053043#include <dt-bindings/gpio/gpio.h>
44#include <dt-bindings/input/input.h>
Jagan Tekie9dfa1e2017-02-24 15:32:54 +053045
46/ {
47 memory {
48 reg = <0x80000000 0x20000000>;
49 };
50
51 chosen {
52 stdout-path = &uart1;
53 };
54};
55
Jagan Teki580a7d62017-02-24 15:32:57 +053056&fec1 {
57 pinctrl-names = "default";
58 pinctrl-0 = <&pinctrl_enet1>;
59 phy-mode = "rmii";
60 status = "okay";
61};
62
Jagan Teki08a480b2017-02-24 15:32:55 +053063&i2c1 {
64 clock-frequency = <100000>;
65 pinctrl-names = "default";
66 pinctrl-0 = <&pinctrl_i2c1>;
67 status = "okay";
68};
69
70&i2c2 {
71 clock_frequency = <100000>;
72 pinctrl-names = "default";
73 pinctrl-0 = <&pinctrl_i2c2>;
74 status = "okay";
75};
76
Jagan Tekie9dfa1e2017-02-24 15:32:54 +053077&uart1 {
78 pinctrl-names = "default";
79 pinctrl-0 = <&pinctrl_uart1>;
80 status = "okay";
81};
82
83&usdhc1 {
84 pinctrl-names = "default";
85 pinctrl-0 = <&pinctrl_usdhc1>;
86 cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
87 bus-width = <4>;
88 no-1-8-v;
89 status = "okay";
90};
91
Jagan Teki067a9da2018-04-11 18:02:21 +053092&usdhc2 {
93 pinctrl-names = "default";
94 pinctrl-0 = <&pinctrl_usdhc2>;
95 cd-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>;
96 bus-width = <8>;
97 no-1-8-v;
98 status = "disabled";
99};
100
Jagan Tekie9dfa1e2017-02-24 15:32:54 +0530101&iomuxc {
Jagan Teki580a7d62017-02-24 15:32:57 +0530102 pinctrl_enet1: enet1grp {
103 fsl,pins = <
104 MX6UL_PAD_ENET2_RX_DATA0__ENET1_MDIO 0x1b0b0
105 MX6UL_PAD_ENET2_RX_DATA1__ENET1_MDC 0x1b0b0
106 MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0
107 MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0
108 MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0
109 MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0
110 MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0
111 MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0
112 MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031
113 MX6UL_PAD_ENET2_RX_EN__GPIO2_IO10 0x1b0b0
114 >;
115 };
116
Jagan Teki08a480b2017-02-24 15:32:55 +0530117 pinctrl_i2c1: i2c1grp {
118 fsl,pins = <
119 MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0
120 MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0
121 >;
122 };
123
124 pinctrl_i2c2: i2c2grp {
125 fsl,pins = <
126 MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0
127 MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0
128 >;
129 };
130
Jagan Tekie9dfa1e2017-02-24 15:32:54 +0530131 pinctrl_uart1: uart1grp {
132 fsl,pins = <
133 MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1
134 MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1
135 >;
136 };
137
138 pinctrl_usdhc1: usdhc1grp {
Jagan Tekie9dfa1e2017-02-24 15:32:54 +0530139 fsl,pins = <
140 MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059
141 MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059
142 MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059
143 MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059
144 MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059
145 MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059
146 >;
147 };
Jagan Teki067a9da2018-04-11 18:02:21 +0530148
149 pinctrl_usdhc2: usdhc2grp {
150 u-boot,dm-spl;
151 fsl,pins = <
152 MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17070
153 MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x10070
154 MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17070
155 MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17070
156 MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17070
157 MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17070
158 MX6UL_PAD_NAND_DATA04__USDHC2_DATA4 0x17070
159 MX6UL_PAD_NAND_DATA05__USDHC2_DATA5 0x17070
160 MX6UL_PAD_NAND_DATA06__USDHC2_DATA6 0x17070
161 MX6UL_PAD_NAND_DATA07__USDHC2_DATA7 0x17070
162 MX6UL_PAD_NAND_ALE__USDHC2_RESET_B 0x17070
163 >;
164 };
Jagan Tekie9dfa1e2017-02-24 15:32:54 +0530165};