blob: 318c4c5d51cf65ff6c5ca8ed88d37c400aa35106 [file] [log] [blame]
Ron Madrid5bb907a2009-01-22 15:05:24 -08001/*
2 * Copyright (C) Sheldon Instruments, Inc. 2008
3 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22/*
23 * simpc8313 board configuration file
24 */
25
26#ifndef __CONFIG_H
27#define __CONFIG_H
28
29/*
30 * High Level Configuration Options
31 */
32#define CONFIG_NAND_U_BOOT
33
34#define CONFIG_E300 1
Peter Tyser0f898602009-05-22 17:23:24 -050035#define CONFIG_MPC83xx 1
Peter Tyser2c7920a2009-05-22 17:23:25 -050036#define CONFIG_MPC831x 1
Ron Madrid5bb907a2009-01-22 15:05:24 -080037#define CONFIG_MPC8313 1
38
Scott Woodf1c574d2010-11-24 13:28:40 +000039#define CONFIG_SYS_NAND_U_BOOT_SIZE (512 << 10)
40#define CONFIG_SYS_NAND_U_BOOT_DST 0x00100000
41#define CONFIG_SYS_NAND_U_BOOT_START 0x00100100
42#define CONFIG_SYS_NAND_U_BOOT_RELOC 0x00010000
43#define CONFIG_SYS_NAND_U_BOOT_RELOC_SP (CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000)
44
45#define CONFIG_SYS_TEXT_BASE 0x00100000 /* CONFIG_SYS_NAND_U_BOOT_DST */
46#define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000
47
48#ifdef CONFIG_NAND_SPL
49#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */
50#else
51#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Wolfgang Denk2ae18242010-10-06 09:05:45 +020052#endif
53
Ron Madrid5bb907a2009-01-22 15:05:24 -080054#define CONFIG_PCI
Gabor Juhos842033e2013-05-30 07:06:12 +000055#define CONFIG_PCI_INDIRECT_BRIDGE
Becky Bruce0914f482010-06-17 11:37:18 -050056#define CONFIG_FSL_ELBC 1
Ron Madrid5bb907a2009-01-22 15:05:24 -080057
58#define CONFIG_MISC_INIT_R
59
60/*
61 * On-board devices
62 *
63 * TSEC1 is Marvell PHY 88E1118
64 */
65
66#define CONFIG_SYS_33MHZ
67
68#define CONFIG_83XX_CLKIN 33333333 /* in Hz */
69
70#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
71
72#define CONFIG_SYS_IMMR 0xE0000000
73
74#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
75#define CONFIG_DEFAULT_IMMR CONFIG_SYS_IMMR
76#endif
77
78#define CONFIG_SYS_MEMTEST_START 0x00001000
79#define CONFIG_SYS_MEMTEST_END 0x07f00000
80
Joe Hershbergerbb0f5bc2011-10-11 23:57:21 -050081#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
82#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
Ron Madrid5bb907a2009-01-22 15:05:24 -080083
84/*
85 * Device configurations
86 */
87#define CONFIG_TSEC1
88
89/*
90 * DDR Setup
91 */
Joe Hershbergerbb0f5bc2011-10-11 23:57:21 -050092 /* DDR is system memory*/
93#define CONFIG_SYS_DDR_BASE 0x00000000
Ron Madrid5bb907a2009-01-22 15:05:24 -080094#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
95#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
96
97#define CONFIG_VERY_BIG_RAM
98#define CONFIG_MAX_MEM_MAPPED (512 << 20)
99
Joe Hershbergerbb0f5bc2011-10-11 23:57:21 -0500100#define CONFIG_SYS_DDRCDR (DDRCDR_EN \
Ron Madrid5bb907a2009-01-22 15:05:24 -0800101 | DDRCDR_PZ_NOMZ \
102 | DDRCDR_NZ_NOMZ \
Joe Hershbergerbb0f5bc2011-10-11 23:57:21 -0500103 | DDRCDR_M_ODR)
Ron Madrid5bb907a2009-01-22 15:05:24 -0800104 /* 0x73000002 TODO ODR & DRN ? */
105
106/*
107 * FLASH on the Local Bus
108 */
109#define CONFIG_SYS_NO_FLASH
110
Ron Madrid5bb907a2009-01-22 15:05:24 -0800111#if !defined(CONFIG_NAND_SPL)
112#define CONFIG_SYS_RAMBOOT
113#endif
114
115#define CONFIG_SYS_INIT_RAM_LOCK 1
Joe Hershbergerbb0f5bc2011-10-11 23:57:21 -0500116#define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */
117#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/
Ron Madrid5bb907a2009-01-22 15:05:24 -0800118
Joe Hershbergerbb0f5bc2011-10-11 23:57:21 -0500119#define CONFIG_SYS_GBL_DATA_OFFSET \
120 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Ron Madrid5bb907a2009-01-22 15:05:24 -0800121#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
122
123/* CONFIG_SYS_MONITOR_LEN must be a multiple of CONFIG_ENV_SECT_SIZE */
Joe Hershbergerbb0f5bc2011-10-11 23:57:21 -0500124#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
125#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
Ron Madrid5bb907a2009-01-22 15:05:24 -0800126
127/*
128 * Local Bus LCRR and LBCR regs
129 */
Kim Phillipsc7190f02009-09-25 18:19:44 -0500130#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
131#define CONFIG_SYS_LCRR_EADC LCRR_EADC_1
132#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2
Ron Madrid5bb907a2009-01-22 15:05:24 -0800133#define CONFIG_SYS_LBC_LBCR (0x00040000 /* TODO */ \
134 | (0xFF << LBCR_BMT_SHIFT) \
Joe Hershbergerbb0f5bc2011-10-11 23:57:21 -0500135 | 0xF) /* 0x0004ff0f */
Ron Madrid5bb907a2009-01-22 15:05:24 -0800136
Joe Hershbergerbb0f5bc2011-10-11 23:57:21 -0500137 /* LB refresh timer prescal, 266MHz/32 */
138#define CONFIG_SYS_LBC_MRTPR 0x20000000
Ron Madrid5bb907a2009-01-22 15:05:24 -0800139
140/* drivers/mtd/nand/nand.c */
141#ifdef CONFIG_NAND_SPL
142#define CONFIG_SYS_NAND_BASE 0xFFF00000
143#else
144#define CONFIG_SYS_NAND_BASE 0xE2800000
145#endif
Ron Madrid3b439792010-04-28 16:04:43 -0700146#define CONFIG_SYS_FPGA_BASE 0xFF000000
Ron Madrid5bb907a2009-01-22 15:05:24 -0800147
Vladimir Zapolskiy6bbb3e92011-11-20 16:10:16 +0200148#define CONFIG_CMD_NAND
Ron Madrid5bb907a2009-01-22 15:05:24 -0800149#define CONFIG_SYS_MAX_NAND_DEVICE 1
Ron Madrid5bb907a2009-01-22 15:05:24 -0800150#define CONFIG_MTD_NAND_VERIFY_WRITE
Ron Madrid5bb907a2009-01-22 15:05:24 -0800151#define CONFIG_NAND_FSL_ELBC 1
152
Joe Hershbergerbb0f5bc2011-10-11 23:57:21 -0500153#define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE \
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500154 | BR_DECC_CHK_GEN /* Use HW ECC */ \
Joe Hershbergerbb0f5bc2011-10-11 23:57:21 -0500155 | BR_PS_8 /* 8 bit Port */ \
156 | BR_MS_FCM /* MSEL = FCM */ \
157 | BR_V) /* valid */
Ron Madrid5bb907a2009-01-22 15:05:24 -0800158
159#ifdef CONFIG_NAND_SP
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500160#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \
Ron Madrid5bb907a2009-01-22 15:05:24 -0800161 | OR_FCM_CSCT \
162 | OR_FCM_CST \
163 | OR_FCM_CHT \
164 | OR_FCM_SCY_1 \
165 | OR_FCM_TRLX \
Joe Hershbergerbb0f5bc2011-10-11 23:57:21 -0500166 | OR_FCM_EHTR)
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500167#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32KB)
168#define CONFIG_SYS_NAND_PAGE_SIZE 512 /* NAND chip page size */
Joe Hershbergerbb0f5bc2011-10-11 23:57:21 -0500169 /* NAND chip block size */
170#define CONFIG_SYS_NAND_BLOCK_SIZE (16 << 10)
Ron Madrid5bb907a2009-01-22 15:05:24 -0800171#define NAND_CACHE_PAGES 32
172#elif defined(CONFIG_NAND_LP)
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500173#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_256KB \
Ron Madrid5bb907a2009-01-22 15:05:24 -0800174 | OR_FCM_PGS \
175 | OR_FCM_CSCT \
176 | OR_FCM_CST \
177 | OR_FCM_CHT \
178 | OR_FCM_SCY_1 \
179 | OR_FCM_TRLX \
Joe Hershbergerbb0f5bc2011-10-11 23:57:21 -0500180 | OR_FCM_EHTR)
Joe Hershberger7d6a0982011-10-11 23:57:30 -0500181#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_256KB)
182#define CONFIG_SYS_NAND_PAGE_SIZE 2048 /* NAND chip page size */
Joe Hershbergerbb0f5bc2011-10-11 23:57:21 -0500183 /* NAND chip block size */
184#define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10)
Ron Madrid5bb907a2009-01-22 15:05:24 -0800185#define NAND_CACHE_PAGES 64
186#else
187#error Page size of NAND not defined.
188#endif /* CONFIG_NAND_SP */
189
190#define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SYS_NAND_BLOCK_SIZE
191
192#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM
193#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM
194
195#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_NAND_BASE
196
197#define CONFIG_SYS_NAND_LBLAWBAR_PRELIM CONFIG_SYS_LBLAWBAR0_PRELIM
198#define CONFIG_SYS_NAND_LBLAWAR_PRELIM CONFIG_SYS_LBLAWAR0_PRELIM
199
Joe Hershbergerbb0f5bc2011-10-11 23:57:21 -0500200#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FPGA_BASE \
Ron Madrid3b439792010-04-28 16:04:43 -0700201 | BR_PS_16 \
202 | BR_MS_UPMA \
Joe Hershbergerbb0f5bc2011-10-11 23:57:21 -0500203 | BR_V)
204#define CONFIG_SYS_OR1_PRELIM (OR_AM_2MB \
Ron Madrid3b439792010-04-28 16:04:43 -0700205 | OR_UPM_BCTLD)
206
207#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_FPGA_BASE
208#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_2MB)
209
Ron Madrid5bb907a2009-01-22 15:05:24 -0800210/*
211 * JFFS2 configuration
212 */
213#define CONFIG_JFFS2_NAND
214#define CONFIG_JFFS2_DEV "nand0"
215
216/* mtdparts command line support */
Stefan Roese68d7d652009-03-19 13:30:36 +0100217#define CONFIG_CMD_MTDPARTS
Joe Hershbergerbb0f5bc2011-10-11 23:57:21 -0500218#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
Ron Madrid5bb907a2009-01-22 15:05:24 -0800219#define MTDIDS_DEFAULT "nand0=nand0"
220#define MTDPARTS_DEFAULT "mtdparts=nand0:2M(u-boot),6M(kernel),-(jffs2)"
221
222/* pass open firmware flat tree */
223#define CONFIG_OF_LIBFDT 1
224#define CONFIG_OF_BOARD_SETUP 1
225#define CONFIG_OF_STDOUT_VIA_ALIAS 1
226
227/*
228 * Serial Port
229 */
230#define CONFIG_CONS_INDEX 1
231#define CONFIG_SYS_NS16550
232#define CONFIG_SYS_NS16550_SERIAL
233#define CONFIG_SYS_NS16550_REG_SIZE 1
Ron Madridf5675aa2009-02-18 14:30:44 -0800234#ifdef CONFIG_NAND_SPL
235#define CONFIG_NS16550_MIN_FUNCTIONS
236#endif
Ron Madrid5bb907a2009-01-22 15:05:24 -0800237
238#define CONFIG_SYS_BAUDRATE_TABLE \
Joe Hershbergerbb0f5bc2011-10-11 23:57:21 -0500239 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
Ron Madrid5bb907a2009-01-22 15:05:24 -0800240
241#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
242#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
243
244/* Use the HUSH parser */
245#define CONFIG_SYS_HUSH_PARSER
Ron Madrid5bb907a2009-01-22 15:05:24 -0800246
247/* I2C */
Joe Hershbergerbb0f5bc2011-10-11 23:57:21 -0500248#define CONFIG_HARD_I2C /* I2C with hardware support*/
Ron Madrid5bb907a2009-01-22 15:05:24 -0800249#define CONFIG_FSL_I2C
250#define CONFIG_I2C_MULTI_BUS
Joe Hershbergerbb0f5bc2011-10-11 23:57:21 -0500251#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
252#define CONFIG_SYS_I2C_SLAVE 0x7F
253#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } /* Don't probe these addrs */
254#define CONFIG_SYS_I2C_OFFSET 0x3000
255#define CONFIG_SYS_I2C2_OFFSET 0x3100
Ron Madrid5bb907a2009-01-22 15:05:24 -0800256
257/*
258 * General PCI
259 * Addresses are mapped 1-1.
260 */
261#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
262#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
263#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000 /* 256M */
264#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
265#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
266#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000 /* 256M */
267#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
268#define CONFIG_SYS_PCI1_IO_PHYS 0xE2000000
269#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
270
271#define CONFIG_PCI_PNP /* do pci plug-and-play */
272#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
273
274/*
275 * TSEC
276 */
277#define CONFIG_TSEC_ENET /* TSEC ethernet support */
278
Ron Madrid5bb907a2009-01-22 15:05:24 -0800279#define CONFIG_GMII /* MII PHY management */
280
281#ifdef CONFIG_TSEC1
282#define CONFIG_HAS_ETH0
283#define CONFIG_TSEC1_NAME "TSEC0"
284#define CONFIG_SYS_TSEC1_OFFSET 0x24000
285#define TSEC1_PHY_ADDR 0x0
286#define TSEC1_FLAGS TSEC_GIGABIT
287#define TSEC1_PHYIDX 0
288#endif
289
290#ifdef CONFIG_TSEC2
291#define CONFIG_HAS_ETH1
292#define CONFIG_TSEC2_NAME "TSEC1"
293#define CONFIG_SYS_TSEC2_OFFSET 0x25000
294#define TSEC2_PHY_ADDR 4
295#define TSEC2_FLAGS TSEC_GIGABIT
296#define TSEC2_PHYIDX 0
297#endif
298
299
300/* Options are: TSEC[0-1] */
301#define CONFIG_ETHPRIME "TSEC1"
302
303/*
304 * Configure on-board RTC
305 */
306#define CONFIG_RTC_DS1337
307#define CONFIG_SYS_I2C_RTC_ADDR 0x68
308
309/*
310 * Environment
311 */
312#if defined(CONFIG_NAND_U_BOOT)
Joe Hershbergerbb0f5bc2011-10-11 23:57:21 -0500313 #define CONFIG_ENV_IS_IN_NAND 1
314 #define CONFIG_ENV_OFFSET (768 * 1024)
315 #define CONFIG_ENV_SECT_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
316 #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE
317 #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
318 #define CONFIG_ENV_RANGE (CONFIG_ENV_SECT_SIZE * 4)
319 #define CONFIG_ENV_OFFSET_REDUND \
320 (CONFIG_ENV_OFFSET + CONFIG_ENV_RANGE)
Ron Madrid5bb907a2009-01-22 15:05:24 -0800321#elif !defined(CONFIG_SYS_RAMBOOT)
Joe Hershbergerbb0f5bc2011-10-11 23:57:21 -0500322 #define CONFIG_ENV_IS_IN_FLASH 1
323 #define CONFIG_ENV_ADDR \
324 (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
325 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */
326 #define CONFIG_ENV_SIZE 0x2000
Ron Madrid5bb907a2009-01-22 15:05:24 -0800327
328/* Address and size of Redundant Environment Sector */
329#else
Joe Hershbergerbb0f5bc2011-10-11 23:57:21 -0500330 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
331 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
332 #define CONFIG_ENV_SIZE 0x2000
Ron Madrid5bb907a2009-01-22 15:05:24 -0800333#endif
334
Joe Hershbergerbb0f5bc2011-10-11 23:57:21 -0500335#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
336#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Ron Madrid5bb907a2009-01-22 15:05:24 -0800337
338/*
339 * BOOTP options
340 */
341#define CONFIG_BOOTP_BOOTFILESIZE
342#define CONFIG_BOOTP_BOOTPATH
343#define CONFIG_BOOTP_GATEWAY
344#define CONFIG_BOOTP_HOSTNAME
345
346
347/*
348 * Command line configuration.
349 */
350#include <config_cmd_default.h>
351#undef CONFIG_CMD_IMLS
352#undef CONFIG_CMD_FLASH
353
354#define CONFIG_CMD_PING
355#define CONFIG_CMD_DHCP
356#define CONFIG_CMD_I2C
357#define CONFIG_CMD_MII
358#define CONFIG_CMD_DATE
359#define CONFIG_CMD_PCI
360#define CONFIG_CMD_JFFS2
361
362#if defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_NAND_U_BOOT)
Mike Frysingerbdab39d2009-01-28 19:08:14 -0500363 #undef CONFIG_CMD_SAVEENV
Ron Madrid5bb907a2009-01-22 15:05:24 -0800364 #undef CONFIG_CMD_LOADS
365#endif
366
Joe Hershbergerbb0f5bc2011-10-11 23:57:21 -0500367#define CONFIG_CMDLINE_EDITING 1
368#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Ron Madrid5bb907a2009-01-22 15:05:24 -0800369
370/*
371 * Miscellaneous configurable options
372 */
Joe Hershbergerbb0f5bc2011-10-11 23:57:21 -0500373#define CONFIG_SYS_LONGHELP /* undef to save memory */
374#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
375#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
376#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Ron Madrid5bb907a2009-01-22 15:05:24 -0800377
Joe Hershbergerbb0f5bc2011-10-11 23:57:21 -0500378#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
379 + sizeof(CONFIG_SYS_PROMPT) \
380 + 16) /* Print Buffer Size */
381#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
382 /* Boot Argument Buffer Size */
383#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
384#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
Ron Madrid5bb907a2009-01-22 15:05:24 -0800385
386/*
387 * For booting Linux, the board info and command line data
Ira W. Snyder9f530d52010-09-10 15:42:32 -0700388 * have to be in the first 256 MB of memory, since this is
Ron Madrid5bb907a2009-01-22 15:05:24 -0800389 * the maximum mapped by the Linux kernel during initialization.
390 */
Joe Hershbergerbb0f5bc2011-10-11 23:57:21 -0500391 /* Initial Memory map for Linux*/
392#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
Ron Madrid5bb907a2009-01-22 15:05:24 -0800393
Joe Hershbergerbb0f5bc2011-10-11 23:57:21 -0500394#define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */
Ron Madrid5bb907a2009-01-22 15:05:24 -0800395
Joe Hershbergerbb0f5bc2011-10-11 23:57:21 -0500396#define CONFIG_SYS_HRCW_LOW (HRCWL_LCL_BUS_TO_SCB_CLK_1X1 \
397 | 0x20000000 /* reserved */ \
398 | HRCWL_DDR_TO_SCB_CLK_2X1 \
399 | HRCWL_CSB_TO_CLKIN_4X1 \
400 | HRCWL_CORE_TO_CSB_2_5X1)
Ron Madrid5bb907a2009-01-22 15:05:24 -0800401
Joe Hershbergerbb0f5bc2011-10-11 23:57:21 -0500402#define CONFIG_SYS_NS16550_CLK (CONFIG_83XX_CLKIN * 4)
Ron Madrid5bb907a2009-01-22 15:05:24 -0800403
Joe Hershbergerbb0f5bc2011-10-11 23:57:21 -0500404#define CONFIG_SYS_HRCW_HIGH_BASE (HRCWH_PCI_HOST \
405 | HRCWH_PCI1_ARBITER_ENABLE \
406 | HRCWH_CORE_ENABLE \
407 | HRCWH_BOOTSEQ_DISABLE \
408 | HRCWH_SW_WATCHDOG_DISABLE \
409 | HRCWH_TSEC1M_IN_RGMII \
410 | HRCWH_TSEC2M_IN_RGMII \
411 | HRCWH_BIG_ENDIAN \
412 | HRCWH_LALE_NORMAL)
Ron Madrid5bb907a2009-01-22 15:05:24 -0800413
414#ifdef CONFIG_NAND_LP
Joe Hershbergerbb0f5bc2011-10-11 23:57:21 -0500415#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE \
416 | HRCWH_FROM_0XFFF00100 \
417 | HRCWH_ROM_LOC_NAND_LP_8BIT \
Ron Madrid5bb907a2009-01-22 15:05:24 -0800418 | HRCWH_RL_EXT_NAND)
419#else
Joe Hershbergerbb0f5bc2011-10-11 23:57:21 -0500420#define CONFIG_SYS_HRCW_HIGH (CONFIG_SYS_HRCW_HIGH_BASE \
421 | HRCWH_FROM_0XFFF00100 \
422 | HRCWH_ROM_LOC_NAND_SP_8BIT \
423 | HRCWH_RL_EXT_NAND)
Ron Madrid5bb907a2009-01-22 15:05:24 -0800424#endif
425
426/* System IO Config */
Joe Hershbergerbb0f5bc2011-10-11 23:57:21 -0500427#define CONFIG_SYS_SICRH (SICRH_ETSEC2_B \
Ron Madrid5bb907a2009-01-22 15:05:24 -0800428 | SICRH_ETSEC2_C \
429 | SICRH_ETSEC2_D \
430 | SICRH_ETSEC2_E \
431 | SICRH_ETSEC2_F \
432 | SICRH_ETSEC2_G \
433 | SICRH_TSOBI1 \
Joe Hershbergerbb0f5bc2011-10-11 23:57:21 -0500434 | SICRH_TSOBI2)
435#define CONFIG_SYS_SICRL (SICRL_LBC \
Ron Madridf9863252010-06-01 17:00:49 -0700436 | SICRL_USBDR_10 \
Joe Hershbergerbb0f5bc2011-10-11 23:57:21 -0500437 | SICRL_ETSEC2_A)
Ron Madrid5bb907a2009-01-22 15:05:24 -0800438
439#define CONFIG_SYS_HID0_INIT 0x000000000
Joe Hershbergerbb0f5bc2011-10-11 23:57:21 -0500440#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \
441 | HID0_ENABLE_INSTRUCTION_CACHE \
442 | HID0_ENABLE_DYNAMIC_POWER_MANAGMENT)
Ron Madrid5bb907a2009-01-22 15:05:24 -0800443
444#define CONFIG_SYS_HID2 HID2_HBE
445
446#define CONFIG_HIGH_BATS 1 /* High BATs supported */
447
448/* DDR @ 0x00000000 */
Joe Hershberger72cd4082011-10-11 23:57:28 -0500449#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW)
Joe Hershbergerbb0f5bc2011-10-11 23:57:21 -0500450#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
451 | BATU_BL_256M \
452 | BATU_VS \
453 | BATU_VP)
454#define CONFIG_SYS_IBAT1L ((CONFIG_SYS_SDRAM_BASE + 0x10000000) \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500455 | BATL_PP_RW)
Joe Hershbergerbb0f5bc2011-10-11 23:57:21 -0500456#define CONFIG_SYS_IBAT1U ((CONFIG_SYS_SDRAM_BASE + 0x10000000) \
457 | BATU_BL_256M \
458 | BATU_VS \
459 | BATU_VP)
Ron Madrid5bb907a2009-01-22 15:05:24 -0800460
461/* PCI @ 0x80000000 */
Joe Hershberger72cd4082011-10-11 23:57:28 -0500462#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_MEM_BASE | BATL_PP_RW)
Joe Hershbergerbb0f5bc2011-10-11 23:57:21 -0500463#define CONFIG_SYS_IBAT2U (CONFIG_SYS_PCI1_MEM_BASE \
464 | BATU_BL_256M \
465 | BATU_VS \
466 | BATU_VP)
467#define CONFIG_SYS_IBAT3L (CONFIG_SYS_PCI1_MMIO_BASE \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500468 | BATL_PP_RW \
Joe Hershbergerbb0f5bc2011-10-11 23:57:21 -0500469 | BATL_CACHEINHIBIT \
470 | BATL_GUARDEDSTORAGE)
471#define CONFIG_SYS_IBAT3U (CONFIG_SYS_PCI1_MMIO_BASE \
472 | BATU_BL_256M \
473 | BATU_VS \
474 | BATU_VP)
Ron Madrid5bb907a2009-01-22 15:05:24 -0800475
476/* PCI2 not supported on 8313 */
477#define CONFIG_SYS_IBAT4L (0)
478#define CONFIG_SYS_IBAT4U (0)
479
480/* IMMRBAR @ 0xE0000000, PCI IO @ 0xE2000000 */
Joe Hershbergerbb0f5bc2011-10-11 23:57:21 -0500481#define CONFIG_SYS_IBAT5L (CONFIG_SYS_IMMR \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500482 | BATL_PP_RW \
Joe Hershbergerbb0f5bc2011-10-11 23:57:21 -0500483 | BATL_CACHEINHIBIT \
484 | BATL_GUARDEDSTORAGE)
485#define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR \
486 | BATU_BL_256M \
487 | BATU_VS \
488 | BATU_VP)
Ron Madrid5bb907a2009-01-22 15:05:24 -0800489
490/* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */
Joe Hershbergerbb0f5bc2011-10-11 23:57:21 -0500491#define CONFIG_SYS_IBAT6L (0xF0000000 \
Joe Hershberger72cd4082011-10-11 23:57:28 -0500492 | BATL_PP_RW \
Joe Hershbergerbb0f5bc2011-10-11 23:57:21 -0500493 | BATL_GUARDEDSTORAGE)
494#define CONFIG_SYS_IBAT6U (0xF0000000 \
495 | BATU_BL_256M \
496 | BATU_VS \
497 | BATU_VP)
Ron Madrid5bb907a2009-01-22 15:05:24 -0800498
499#define CONFIG_SYS_IBAT7L (0)
500#define CONFIG_SYS_IBAT7U (0)
501
502#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
503#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
504#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
505#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
506#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
507#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
508#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
509#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
510#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
511#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
512#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
513#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
514#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
515#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
516#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
517#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
518
519/*
Ron Madrid5bb907a2009-01-22 15:05:24 -0800520 * Environment Configuration
521 */
522#define CONFIG_ENV_OVERWRITE
523
Joe Hershbergerbb0f5bc2011-10-11 23:57:21 -0500524#define CONFIG_NETDEV "eth1"
Ron Madrid5bb907a2009-01-22 15:05:24 -0800525
526#define CONFIG_HOSTNAME simpc8313
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000527#define CONFIG_ROOTPATH "/tftpboot/"
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000528#define CONFIG_BOOTFILE "/tftpboot/uImage"
Joe Hershbergerbb0f5bc2011-10-11 23:57:21 -0500529 /* U-Boot image on TFTP server */
530#define CONFIG_UBOOTPATH "u-boot-nand.bin"
531#define CONFIG_FDTFILE "simpc8313.dtb"
Ron Madrid5bb907a2009-01-22 15:05:24 -0800532
Joe Hershbergerbb0f5bc2011-10-11 23:57:21 -0500533 /* default location for tftp and bootm */
534#define CONFIG_LOADADDR 500000
Ron Madrid5bb907a2009-01-22 15:05:24 -0800535#define CONFIG_BOOTDELAY 5 /* 5 second delay */
536#define CONFIG_BAUDRATE 115200
537
Joe Hershbergerbb0f5bc2011-10-11 23:57:21 -0500538#define CONFIG_BOOTCOMMAND "nand read $loadaddr kernel 600000;" \
539 "bootm $loadaddr - $fdtaddr"
Ron Madrid5bb907a2009-01-22 15:05:24 -0800540
Ron Madrid5bb907a2009-01-22 15:05:24 -0800541#define CONFIG_EXTRA_ENV_SETTINGS \
Joe Hershbergerbb0f5bc2011-10-11 23:57:21 -0500542 "netdev=" CONFIG_NETDEV "\0" \
Ron Madrid5bb907a2009-01-22 15:05:24 -0800543 "ethprime=TSEC1\0" \
Joe Hershbergerbb0f5bc2011-10-11 23:57:21 -0500544 "uboot=" CONFIG_UBOOTPATH "\0" \
Ron Madrid5bb907a2009-01-22 15:05:24 -0800545 "tftpflash=tftpboot $loadaddr $uboot; " \
Marek Vasut5368c552012-09-23 17:41:24 +0200546 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
547 " +$filesize; " \
548 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
549 " +$filesize; " \
550 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
551 " $filesize; " \
552 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
553 " +$filesize; " \
554 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
555 " $filesize\0" \
Ron Madrid5bb907a2009-01-22 15:05:24 -0800556 "fdtaddr=ae0000\0" \
Joe Hershbergerbb0f5bc2011-10-11 23:57:21 -0500557 "fdtfile=" CONFIG_FDTFILE "\0" \
Ron Madrid5bb907a2009-01-22 15:05:24 -0800558 "console=ttyS0\0" \
559 "setbootargs=setenv bootargs " \
560 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
Joe Hershbergerbb0f5bc2011-10-11 23:57:21 -0500561 "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
562 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:" \
563 "$netdev:off " \
564 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
Ron Madrid5bb907a2009-01-22 15:05:24 -0800565 "load_uboot=tftp 100000 u-boot-nand.bin\0" \
566 "burn_uboot=nand erase u-boot 80000; " \
567 "nand write 100000 u-boot $filesize\0" \
568 "update_uboot=run load_uboot;run burn_uboot\0" \
569 "mtdids=nand0=nand0\0" \
570 "mtdparts=mtdparts=nand0:2M(u-boot),6M(kernel),-(jffs2)\0" \
571 "nfsargs=setenv bootargs root=/dev/nfs rw " \
572 "nfsroot=${serverip}:${rootpath}\0" \
573 "ramargs=setenv bootargs root=/dev/ram rw\0" \
574 "addip=setenv bootargs ${bootargs} " \
575 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
576 ":${hostname}:${netdev}:off panic=1\0" \
Joe Hershbergerbb0f5bc2011-10-11 23:57:21 -0500577 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \
Ron Madrid5bb907a2009-01-22 15:05:24 -0800578 "bootargs=root=/dev/mtdblock2 rootfstype=jffs2 rw " \
579 "console=ttyS0,115200\0" \
580 ""
581
582#define CONFIG_NFSBOOTCOMMAND \
583 "setenv rootdev /dev/nfs;" \
584 "run setbootargs;" \
585 "run setipargs;" \
586 "tftp $loadaddr $bootfile;" \
587 "tftp $fdtaddr $fdtfile;" \
588 "bootm $loadaddr - $fdtaddr"
589
590#define CONFIG_RAMBOOTCOMMAND \
591 "setenv rootdev /dev/ram;" \
592 "run setbootargs;" \
593 "tftp $ramdiskaddr $ramdiskfile;" \
594 "tftp $loadaddr $bootfile;" \
595 "tftp $fdtaddr $fdtfile;" \
596 "bootm $loadaddr $ramdiskaddr $fdtaddr"
597
Ron Madrid5bb907a2009-01-22 15:05:24 -0800598#endif /* __CONFIG_H */