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wdenke2211742002-11-02 23:30:20 +00001/*
2 * (C) Copyright 2001
3 * Frank Gottschling, ELTEC Elektronik AG, fgottschling@eltec.de
4 *
5 * (C) Copyright 2001
6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 *
8 * Configuation settings for the miniHiPerCam.
9 *
10 * -----------------------------------------------------------------
Wolfgang Denk3765b3e2013-10-07 13:07:26 +020011 * SPDX-License-Identifier: GPL-2.0+
wdenke2211742002-11-02 23:30:20 +000012 */
13
14/*
15 * board/config.h - configuration options, board specific
16 */
17
18#ifndef __CONFIG_H
19#define __CONFIG_H
20
21/*
22 * High Level Configuration Options
23 * (easy to change)
24 */
25#define CONFIG_MPC823 1 /* This is a MPC823 CPU */
wdenkc837dcb2004-01-20 23:12:12 +000026#define CONFIG_MHPC 1 /* on a miniHiPerCam */
27#define CONFIG_BOARD_EARLY_INIT_F 1 /* do special hardware init. */
28#define CONFIG_MISC_INIT_R 1
wdenke2211742002-11-02 23:30:20 +000029
Wolfgang Denk2ae18242010-10-06 09:05:45 +020030#define CONFIG_SYS_TEXT_BASE 0xfe000000
31
wdenke2211742002-11-02 23:30:20 +000032#define CONFIG_8xx_GCLK_FREQ MPC8XX_SPEED
33#undef CONFIG_8xx_CONS_SMC1
wdenkc837dcb2004-01-20 23:12:12 +000034#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */
wdenke2211742002-11-02 23:30:20 +000035#undef CONFIG_8xx_CONS_NONE
36#define CONFIG_BAUDRATE 9600
37#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
38
wdenkc837dcb2004-01-20 23:12:12 +000039#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
wdenke2211742002-11-02 23:30:20 +000040
wdenkc837dcb2004-01-20 23:12:12 +000041#define CONFIG_ENV_OVERWRITE 1
42#define CONFIG_ETHADDR 00:00:5b:ee:de:ad
wdenke2211742002-11-02 23:30:20 +000043
wdenkc837dcb2004-01-20 23:12:12 +000044#undef CONFIG_BOOTARGS
wdenke2211742002-11-02 23:30:20 +000045#define CONFIG_BOOTCOMMAND \
46 "bootp;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010047 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
48 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
wdenke2211742002-11-02 23:30:20 +000049 "bootm"
50
51#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020052#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
wdenke2211742002-11-02 23:30:20 +000053
54#undef CONFIG_WATCHDOG /* watchdog disabled */
wdenkc837dcb2004-01-20 23:12:12 +000055#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
wdenke2211742002-11-02 23:30:20 +000056
wdenkc837dcb2004-01-20 23:12:12 +000057#undef CONFIG_UCODE_PATCH
wdenke2211742002-11-02 23:30:20 +000058
59/* enable I2C and select the hardware/software driver */
Heiko Schocherea818db2013-01-29 08:53:15 +010060#define CONFIG_SYS_I2C
61#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
62#define CONFIG_SYS_I2C_SOFT_SPEED 50000
63#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
wdenke2211742002-11-02 23:30:20 +000064/*
65 * Software (bit-bang) I2C driver configuration
66 */
67#define PB_SCL 0x00000020 /* PB 26 */
68#define PB_SDA 0x00000010 /* PB 27 */
69
70#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
71#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
72#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
73#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
74#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
wdenkc837dcb2004-01-20 23:12:12 +000075 else immr->im_cpm.cp_pbdat &= ~PB_SDA
wdenke2211742002-11-02 23:30:20 +000076#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
wdenkc837dcb2004-01-20 23:12:12 +000077 else immr->im_cpm.cp_pbdat &= ~PB_SCL
wdenke2211742002-11-02 23:30:20 +000078#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
79
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020080#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM X24C04 */
81#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* bytes of address */
wdenkc837dcb2004-01-20 23:12:12 +000082/* mask of address bits that overflow into the "EEPROM chip address" */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020083#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
84#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
85#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
wdenke2211742002-11-02 23:30:20 +000086
wdenkc837dcb2004-01-20 23:12:12 +000087#define LCD_VIDEO_ADDR (SDRAM_MAX_SIZE-SDRAM_RES_SIZE)
88#define LCD_VIDEO_SIZE SDRAM_RES_SIZE /* 2MB */
89#define LCD_VIDEO_COLS 640
90#define LCD_VIDEO_ROWS 480
91#define LCD_VIDEO_FG 255
92#define LCD_VIDEO_BG 0
wdenke2211742002-11-02 23:30:20 +000093
wdenkc837dcb2004-01-20 23:12:12 +000094#undef CONFIG_VIDEO /* test only ! s.a devices.c and 8xx */
95#define CONFIG_CFB_CONSOLE /* framebuffer console with std input */
wdenke2211742002-11-02 23:30:20 +000096#define CONFIG_VIDEO_LOGO
97
wdenkc837dcb2004-01-20 23:12:12 +000098#define VIDEO_KBD_INIT_FCT 0 /* no KBD dev on MHPC - use serial */
99#define VIDEO_TSTC_FCT serial_tstc
100#define VIDEO_GETC_FCT serial_getc
wdenke2211742002-11-02 23:30:20 +0000101
wdenkc837dcb2004-01-20 23:12:12 +0000102#define CONFIG_BR0_WORKAROUND 1
wdenke2211742002-11-02 23:30:20 +0000103
Jon Loeliger8353e132007-07-08 14:14:17 -0500104
105/*
106 * Command line configuration.
107 */
108#include <config_cmd_default.h>
109
110#define CONFIG_CMD_DATE
111#define CONFIG_CMD_EEPROM
112#define CONFIG_CMD_ELF
113#define CONFIG_CMD_I2C
114#define CONFIG_CMD_JFFS2
115#define CONFIG_CMD_REGINFO
116
wdenke2211742002-11-02 23:30:20 +0000117
Jon Loeliger7be044e2007-07-09 21:24:19 -0500118/*
119 * BOOTP options
120 */
121#define CONFIG_BOOTP_SUBNETMASK
122#define CONFIG_BOOTP_GATEWAY
123#define CONFIG_BOOTP_HOSTNAME
124#define CONFIG_BOOTP_BOOTPATH
125#define CONFIG_BOOTP_BOOTFILESIZE
126
wdenke2211742002-11-02 23:30:20 +0000127
wdenke2211742002-11-02 23:30:20 +0000128/*
129 * Miscellaneous configurable options
130 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200131#define CONFIG_SYS_LONGHELP /* undef to save memory */
Jon Loeliger8353e132007-07-08 14:14:17 -0500132#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200133#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenke2211742002-11-02 23:30:20 +0000134#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200135#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenke2211742002-11-02 23:30:20 +0000136#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200137#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
138#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
139#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenke2211742002-11-02 23:30:20 +0000140
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200141#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
142#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
wdenke2211742002-11-02 23:30:20 +0000143
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144#define CONFIG_SYS_LOAD_ADDR 0x300000 /* default load address */
wdenke2211742002-11-02 23:30:20 +0000145
wdenke2211742002-11-02 23:30:20 +0000146/*
147 * Low Level Configuration Settings
148 * (address mappings, register initial values, etc.)
149 * You should know what you are doing if you make changes here.
150 */
151
152/*-----------------------------------------------------------------------
153 * Physical memory map
154 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200155#define CONFIG_SYS_IMMR 0xFFF00000 /* Internal Memory Mapped Register*/
wdenke2211742002-11-02 23:30:20 +0000156
157/*-----------------------------------------------------------------------
158 * Definitions for initial stack pointer and data area (in DPRAM)
159 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200160#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk553f0982010-10-26 13:32:32 +0200161#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200162#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200163#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenke2211742002-11-02 23:30:20 +0000164
165/*-----------------------------------------------------------------------
166 * Start addresses for the final memory configuration
167 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200168 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenke2211742002-11-02 23:30:20 +0000169 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200170#define CONFIG_SYS_SDRAM_BASE 0x00000000
171#define CONFIG_SYS_FLASH_BASE 0xfe000000
wdenke2211742002-11-02 23:30:20 +0000172
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173#define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256 kB for Monitor */
174#undef CONFIG_SYS_MONITOR_BASE /* to run U-Boot from RAM */
175#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
176#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenke2211742002-11-02 23:30:20 +0000177
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200178/*
179 * JFFS2 partitions
180 *
181 */
182/* No command line, one static partition, whole device */
Stefan Roese68d7d652009-03-19 13:30:36 +0100183#undef CONFIG_CMD_MTDPARTS
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200184#define CONFIG_JFFS2_DEV "nor0"
185#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
186#define CONFIG_JFFS2_PART_OFFSET 0x00000000
187
188/* mtdparts command line support */
189/* Note: fake mtd_id used, no linux mtd map file */
190/*
Stefan Roese68d7d652009-03-19 13:30:36 +0100191#define CONFIG_CMD_MTDPARTS
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200192#define MTDIDS_DEFAULT "nor0=mhpc-0"
193#define MTDPARTS_DEFAULT "mtdparts=mhpc-0:-(jffs2)"
194*/
wdenke2211742002-11-02 23:30:20 +0000195
196/*
197 * For booting Linux, the board info and command line data
198 * have to be in the first 8 MB of memory, since this is
199 * the maximum mapped by the Linux kernel during initialization.
200 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200201#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map- for Linux */
wdenke2211742002-11-02 23:30:20 +0000202
203/*-----------------------------------------------------------------------
204 * FLASH organization
205 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200206#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
207#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max number of sectors on one chip */
wdenke2211742002-11-02 23:30:20 +0000208
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200209#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
210#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200211#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200212#define CONFIG_ENV_OFFSET CONFIG_SYS_MONITOR_LEN /* Offset of Environment */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200213#define CONFIG_ENV_SIZE 0x20000 /* Total Size of Environment */
wdenke2211742002-11-02 23:30:20 +0000214
215/*-----------------------------------------------------------------------
216 * Cache Configuration
217 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200218#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeliger8353e132007-07-08 14:14:17 -0500219#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200220#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
wdenke2211742002-11-02 23:30:20 +0000221#endif
222
223/*-----------------------------------------------------------------------
224 * SYPCR - System Protection Control 11-9
225 * SYPCR can only be written once after reset!
226 *-----------------------------------------------------------------------
227 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
228 */
229#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200230#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
wdenke2211742002-11-02 23:30:20 +0000231 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
232#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200233#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
wdenk8bde7f72003-06-27 21:31:46 +0000234 SYPCR_SWP)
wdenke2211742002-11-02 23:30:20 +0000235#endif
236
237/*-----------------------------------------------------------------------
238 * SIUMCR - SIU Module Configuration 11-6
239 *-----------------------------------------------------------------------
240 * PCMCIA config., multi-function pin tri-state
241 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200242#define CONFIG_SYS_SIUMCR (SIUMCR_SEME)
wdenke2211742002-11-02 23:30:20 +0000243
244/*-----------------------------------------------------------------------
245 * TBSCR - Time Base Status and Control 11-26
246 *-----------------------------------------------------------------------
247 * Clear Reference Interrupt Status, Timebase freezing enabled
248 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200249#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
wdenke2211742002-11-02 23:30:20 +0000250
251/*-----------------------------------------------------------------------
252 * PISCR - Periodic Interrupt Status and Control 11-31
253 *-----------------------------------------------------------------------
254 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
255 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200256#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF | PISCR_PTE)
wdenke2211742002-11-02 23:30:20 +0000257
258/*-----------------------------------------------------------------------
259 * RTCSC - Real-Time Clock Status and Control Register 12-18
260 *-----------------------------------------------------------------------
261 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200262#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
wdenke2211742002-11-02 23:30:20 +0000263
264/*-----------------------------------------------------------------------
265 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
266 *-----------------------------------------------------------------------
267 * Reset PLL lock status sticky bit, timer expired status bit and timer
268 * interrupt status bit - leave PLL multiplication factor unchanged !
269 */
270#define MPC8XX_SPEED 50000000L
wdenkc837dcb2004-01-20 23:12:12 +0000271#define MPC8XX_XIN 5000000L /* ref clk */
wdenke2211742002-11-02 23:30:20 +0000272#define MPC8XX_FACT (MPC8XX_SPEED/MPC8XX_XIN)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200273#define CONFIG_SYS_PLPRCR (((MPC8XX_FACT-1) << PLPRCR_MF_SHIFT) | \
wdenk8bde7f72003-06-27 21:31:46 +0000274 PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
wdenke2211742002-11-02 23:30:20 +0000275
276/*-----------------------------------------------------------------------
277 * SCCR - System Clock and reset Control Register 15-27
278 *-----------------------------------------------------------------------
279 * Set clock output, timebase and RTC source and divider,
280 * power management and some other internal clocks
281 */
282
283#define SCCR_MASK (SCCR_RTDIV | SCCR_RTSEL) /* SCCR_EBDF11 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200284#define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_DFLCD001)
wdenke2211742002-11-02 23:30:20 +0000285
286
287/*-----------------------------------------------------------------------
288 * MAMR settings for SDRAM - 16-14
289 * => 0xC080200F
290 *-----------------------------------------------------------------------
291 * periodic timer for refresh
292 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200293#define CONFIG_SYS_MAMR_PTA 0xC0
294#define CONFIG_SYS_MAMR ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | MAMR_G0CLA_A11 | MAMR_TLFA_MSK)
wdenke2211742002-11-02 23:30:20 +0000295
296/*
297 * BR0 and OR0 (FLASH) used to re-map FLASH
298 */
299
300/* allow for max 8 MB of Flash */
301#define FLASH_BASE 0xFE000000 /* FLASH bank #0*/
302#define FLASH_BASE0_PRELIM 0xFE000000 /* FLASH bank #0*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200303#define CONFIG_SYS_REMAP_OR_AM 0xFF800000 /* OR addr mask */
304#define CONFIG_SYS_PRELIM_OR_AM 0xFF800000 /* OR addr mask */
wdenke2211742002-11-02 23:30:20 +0000305
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200306#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | OR_SCY_8_CLK) /* (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | OR_SCY_6_CLK)*/
wdenke2211742002-11-02 23:30:20 +0000307
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200308#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
309#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
310#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_GPCM | BR_V )
wdenke2211742002-11-02 23:30:20 +0000311
312/*
313 * BR1 and OR1 (SDRAM)
314 */
315#define SDRAM_BASE1_PRELIM 0x00000000 /* SDRAM bank #0 */
wdenkc837dcb2004-01-20 23:12:12 +0000316#define SDRAM_MAX_SIZE 0x01000000 /* max 16 MB */
317#define SDRAM_RES_SIZE 0x00200000 /* 2 MB for framebuffer */
wdenke2211742002-11-02 23:30:20 +0000318
319/* SDRAM timing: drive GPL5 high on first cycle */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200320#define CONFIG_SYS_OR_TIMING_SDRAM (OR_G5LS)
wdenke2211742002-11-02 23:30:20 +0000321
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200322#define CONFIG_SYS_OR1_PRELIM ((~(SDRAM_MAX_SIZE)+1)| CONFIG_SYS_OR_TIMING_SDRAM )
323#define CONFIG_SYS_BR1_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
wdenke2211742002-11-02 23:30:20 +0000324
325/*
326 * BR2/OR2 - DIMM
327 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200328#define CONFIG_SYS_OR2 (OR_ACS_DIV4)
329#define CONFIG_SYS_BR2 (BR_MS_UPMA)
wdenke2211742002-11-02 23:30:20 +0000330
331/*
332 * BR3/OR3 - DIMM
333 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200334#define CONFIG_SYS_OR3 (OR_ACS_DIV4)
335#define CONFIG_SYS_BR3 (BR_MS_UPMA)
wdenke2211742002-11-02 23:30:20 +0000336
337/*
338 * BR4/OR4
339 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200340#define CONFIG_SYS_OR4 0
341#define CONFIG_SYS_BR4 0
wdenke2211742002-11-02 23:30:20 +0000342
343/*
344 * BR5/OR5
345 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200346#define CONFIG_SYS_OR5 0
347#define CONFIG_SYS_BR5 0
wdenke2211742002-11-02 23:30:20 +0000348
349/*
350 * BR6/OR6
351 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200352#define CONFIG_SYS_OR6 0
353#define CONFIG_SYS_BR6 0
wdenke2211742002-11-02 23:30:20 +0000354
355/*
356 * BR7/OR7
357 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200358#define CONFIG_SYS_OR7 0
359#define CONFIG_SYS_BR7 0
wdenke2211742002-11-02 23:30:20 +0000360
361
362/*-----------------------------------------------------------------------
363 * Debug Entry Mode
364 *-----------------------------------------------------------------------
365 *
366 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200367#define CONFIG_SYS_DER 0
wdenke2211742002-11-02 23:30:20 +0000368
wdenke2211742002-11-02 23:30:20 +0000369#endif /* __CONFIG_H */