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Macpaul Lin6cb144b2010-10-19 17:05:51 +08001/*
2 * Copyright (C) 2011 Andes Technology Corporation
3 * Shawn Lin, Andes Technology Corporation <nobuhiro@andestech.com>
4 * Macpaul Lin, Andes Technology Corporation <macpaul@andestech.com>
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Macpaul Lin6cb144b2010-10-19 17:05:51 +08007 */
8
9#ifndef __CONFIG_H
10#define __CONFIG_H
11
12#include <asm/arch/ag101.h>
13
14/*
15 * CPU and Board Configuration Options
16 */
17#define CONFIG_ADP_AG101P
18
19#define CONFIG_USE_INTERRUPT
20
21#define CONFIG_SKIP_LOWLEVEL_INIT
22
ken kuoe3c58b02013-06-08 11:14:12 +080023/*
24 * Definitions related to passing arguments to kernel.
25 */
26#define CONFIG_CMDLINE_TAG /* send commandline to Kernel */
27#define CONFIG_SETUP_MEMORY_TAGS /* send memory definition to kernel */
28#define CONFIG_INITRD_TAG /* send initrd params */
29
Macpaul Lin6cb144b2010-10-19 17:05:51 +080030#ifndef CONFIG_SKIP_LOWLEVEL_INIT
31#define CONFIG_MEM_REMAP
32#endif
33
34#ifdef CONFIG_SKIP_LOWLEVEL_INIT
35#define CONFIG_SYS_TEXT_BASE 0x03200000
36#else
37#define CONFIG_SYS_TEXT_BASE 0x00000000
38#endif
39
40/*
41 * Timer
42 */
Macpaul Lin6cb144b2010-10-19 17:05:51 +080043#define CONFIG_SYS_CLK_FREQ 39062500
44#define VERSION_CLOCK CONFIG_SYS_CLK_FREQ
45
46/*
47 * Use Externel CLOCK or PCLK
48 */
49#undef CONFIG_FTRTC010_EXTCLK
50
51#ifndef CONFIG_FTRTC010_EXTCLK
52#define CONFIG_FTRTC010_PCLK
53#endif
54
55#ifdef CONFIG_FTRTC010_EXTCLK
56#define TIMER_CLOCK 32768 /* CONFIG_FTRTC010_EXTCLK */
57#else
58#define TIMER_CLOCK CONFIG_SYS_HZ /* CONFIG_FTRTC010_PCLK */
59#endif
60
61#define TIMER_LOAD_VAL 0xffffffff
62
63/*
64 * Real Time Clock
65 */
66#define CONFIG_RTC_FTRTC010
67
68/*
69 * Real Time Clock Divider
70 * RTC_DIV_COUNT (OSC_CLK/OSC_5MHZ)
71 */
72#define OSC_5MHZ (5*1000000)
73#define OSC_CLK (4*OSC_5MHZ)
74#define RTC_DIV_COUNT (0.5) /* Why?? */
75
76/*
77 * Serial console configuration
78 */
79
80/* FTUART is a high speed NS 16C550A compatible UART, addr: 0x99600000 */
81#define CONFIG_BAUDRATE 38400
82#define CONFIG_CONS_INDEX 1
83#define CONFIG_SYS_NS16550
84#define CONFIG_SYS_NS16550_SERIAL
85#define CONFIG_SYS_NS16550_COM1 CONFIG_FTUART010_02_BASE
86#define CONFIG_SYS_NS16550_REG_SIZE -4
87#define CONFIG_SYS_NS16550_CLK ((18432000 * 20) / 25) /* AG101P */
88
Macpaul Lin6cb144b2010-10-19 17:05:51 +080089/*
90 * Ethernet
91 */
92#define CONFIG_FTMAC100
93
94#define CONFIG_BOOTDELAY 3
95
96/*
97 * SD (MMC) controller
98 */
99#define CONFIG_MMC
100#define CONFIG_CMD_MMC
101#define CONFIG_GENERIC_MMC
102#define CONFIG_DOS_PARTITION
103#define CONFIG_FTSDC010
104#define CONFIG_FTSDC010_NUMBER 1
ken kuo61ccf082013-06-08 11:14:11 +0800105#define CONFIG_FTSDC010_SDIO
Macpaul Lin6cb144b2010-10-19 17:05:51 +0800106#define CONFIG_CMD_FAT
ken kuo61ccf082013-06-08 11:14:11 +0800107#define CONFIG_CMD_EXT2
Macpaul Lin6cb144b2010-10-19 17:05:51 +0800108
109/*
110 * Command line configuration.
111 */
112#include <config_cmd_default.h>
113
114#define CONFIG_CMD_CACHE
115#define CONFIG_CMD_DATE
116#define CONFIG_CMD_PING
117
118/*
119 * Miscellaneous configurable options
120 */
121#define CONFIG_SYS_LONGHELP /* undef to save memory */
122#define CONFIG_SYS_PROMPT "NDS32 # " /* Monitor Command Prompt */
123#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
124
125/* Print Buffer Size */
126#define CONFIG_SYS_PBSIZE \
127 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
128
129/* max number of command args */
130#define CONFIG_SYS_MAXARGS 16
131
132/* Boot Argument Buffer Size */
133#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
134
135/*
Macpaul Lin6cb144b2010-10-19 17:05:51 +0800136 * Size of malloc() pool
137 */
138/* 512kB is suggested, (CONFIG_ENV_SIZE + 128 * 1024) was not enough */
139#define CONFIG_SYS_MALLOC_LEN (512 << 10)
140
141/*
142 * size in bytes reserved for initial data
143 */
144#define CONFIG_SYS_GBL_DATA_SIZE 128
145
146/*
147 * AHB Controller configuration
148 */
149#define CONFIG_FTAHBC020S
150
151#ifdef CONFIG_FTAHBC020S
152#include <faraday/ftahbc020s.h>
153
154/* Address of PHYS_SDRAM_0 before memory remap is at 0x(100)00000 */
155#define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE 0x100
156
157/*
158 * CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6: this define is used in lowlevel_init.S,
159 * hence we cannot use FTAHBC020S_BSR_SIZE(2048) since it will use ffs() wrote
160 * in C language.
161 */
162#define CONFIG_SYS_FTAHBC020S_SLAVE_BSR_6 \
163 (FTAHBC020S_SLAVE_BSR_BASE(CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE) | \
164 FTAHBC020S_SLAVE_BSR_SIZE(0xb))
165#endif
166
167/*
168 * Watchdog
169 */
170#define CONFIG_FTWDT010_WATCHDOG
171
172/*
173 * PMU Power controller configuration
174 */
175#define CONFIG_PMU
176#define CONFIG_FTPMU010_POWER
177
178#ifdef CONFIG_FTPMU010_POWER
179#include <faraday/ftpmu010.h>
180#define CONFIG_SYS_FTPMU010_PDLLCR0_HCLKOUTDIS 0x0E
181#define CONFIG_SYS_FTPMU010_SDRAMHTC (FTPMU010_SDRAMHTC_EBICTRL_DCSR | \
182 FTPMU010_SDRAMHTC_EBIDATA_DCSR | \
183 FTPMU010_SDRAMHTC_SDRAMCS_DCSR | \
184 FTPMU010_SDRAMHTC_SDRAMCTL_DCSR | \
185 FTPMU010_SDRAMHTC_CKE_DCSR | \
186 FTPMU010_SDRAMHTC_DQM_DCSR | \
187 FTPMU010_SDRAMHTC_SDCLK_DCSR)
188#endif
189
190/*
191 * SDRAM controller configuration
192 */
193#define CONFIG_FTSDMC021
194
195#ifdef CONFIG_FTSDMC021
196#include <faraday/ftsdmc021.h>
197
198#define CONFIG_SYS_FTSDMC021_TP1 (FTSDMC021_TP1_TRAS(2) | \
199 FTSDMC021_TP1_TRP(1) | \
200 FTSDMC021_TP1_TRCD(1) | \
201 FTSDMC021_TP1_TRF(3) | \
202 FTSDMC021_TP1_TWR(1) | \
203 FTSDMC021_TP1_TCL(2))
204
205#define CONFIG_SYS_FTSDMC021_TP2 (FTSDMC021_TP2_INI_PREC(4) | \
206 FTSDMC021_TP2_INI_REFT(8) | \
207 FTSDMC021_TP2_REF_INTV(0x180))
208
209/*
210 * CONFIG_SYS_FTSDMC021_CR1: this define is used in lowlevel_init.S,
211 * hence we cannot use FTSDMC021_BANK_SIZE(64) since it will use ffs() wrote in
212 * C language.
213 */
214#define CONFIG_SYS_FTSDMC021_CR1 (FTSDMC021_CR1_DDW(2) | \
215 FTSDMC021_CR1_DSZ(3) | \
216 FTSDMC021_CR1_MBW(2) | \
217 FTSDMC021_CR1_BNKSIZE(6))
218
219#define CONFIG_SYS_FTSDMC021_CR2 (FTSDMC021_CR2_IPREC | \
220 FTSDMC021_CR2_IREF | \
221 FTSDMC021_CR2_ISMR)
222
223#define CONFIG_SYS_FTSDMC021_BANK0_BASE CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE
224#define CONFIG_SYS_FTSDMC021_BANK0_BSR (FTSDMC021_BANK_ENABLE | \
225 CONFIG_SYS_FTSDMC021_BANK0_BASE)
226
ken kuo3c016702013-06-08 11:14:09 +0800227#define CONFIG_SYS_FTSDMC021_BANK1_BASE \
228 (CONFIG_SYS_FTAHBC020S_SLAVE_BSR_BASE + (PHYS_SDRAM_0_SIZE >> 20))
229#define CONFIG_SYS_FTSDMC021_BANK1_BSR (FTSDMC021_BANK_ENABLE | \
230 CONFIG_SYS_FTSDMC021_BANK1_BASE)
Macpaul Lin6cb144b2010-10-19 17:05:51 +0800231#endif
232
233/*
234 * Physical Memory Map
235 */
236#if defined(CONFIG_MEM_REMAP) || defined(CONFIG_SKIP_LOWLEVEL_INIT)
237#define PHYS_SDRAM_0 0x00000000 /* SDRAM Bank #1 */
238#if defined(CONFIG_MEM_REMAP)
239#define PHYS_SDRAM_0_AT_INIT 0x10000000 /* SDRAM Bank #1 before remap*/
240#endif
241#else /* !CONFIG_SKIP_LOWLEVEL_INIT && !CONFIG_MEM_REMAP */
242#define PHYS_SDRAM_0 0x10000000 /* SDRAM Bank #1 */
243#endif
ken kuo3c016702013-06-08 11:14:09 +0800244#define PHYS_SDRAM_1 \
245 (PHYS_SDRAM_0 + PHYS_SDRAM_0_SIZE) /* SDRAM Bank #2 */
Macpaul Lin6cb144b2010-10-19 17:05:51 +0800246
ken kuo3c016702013-06-08 11:14:09 +0800247#define CONFIG_NR_DRAM_BANKS 2 /* we have 2 bank of DRAM */
Macpaul Lin6cb144b2010-10-19 17:05:51 +0800248#define PHYS_SDRAM_0_SIZE 0x04000000 /* 64 MB */
ken kuo3c016702013-06-08 11:14:09 +0800249#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
Macpaul Lin6cb144b2010-10-19 17:05:51 +0800250
251#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_0
252
253#ifdef CONFIG_MEM_REMAP
254#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0xA0000 - \
255 GENERATED_GBL_DATA_SIZE)
256#else
257#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \
258 GENERATED_GBL_DATA_SIZE)
259#endif /* CONFIG_MEM_REMAP */
260
261/*
262 * Load address and memory test area should agree with
263 * arch/nds32/config.mk. Be careful not to overwrite U-boot itself.
264 */
265#define CONFIG_SYS_LOAD_ADDR 0x300000
266
267/* memtest works on 63 MB in DRAM */
268#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_0
269#define CONFIG_SYS_MEMTEST_END (PHYS_SDRAM_0 + 0x03F00000)
270
271/*
272 * Static memory controller configuration
273 */
274#define CONFIG_FTSMC020
275
276#ifdef CONFIG_FTSMC020
277#include <faraday/ftsmc020.h>
278
279#define CONFIG_SYS_FTSMC020_CONFIGS { \
280 { FTSMC020_BANK0_CONFIG, FTSMC020_BANK0_TIMING, }, \
281 { FTSMC020_BANK1_CONFIG, FTSMC020_BANK1_TIMING, }, \
282}
283
284#ifndef CONFIG_SKIP_LOWLEVEL_INIT /* FLASH is on BANK 0 */
285#define FTSMC020_BANK0_LOWLV_CONFIG (FTSMC020_BANK_ENABLE | \
286 FTSMC020_BANK_SIZE_32M | \
287 FTSMC020_BANK_MBW_32)
288
289#define FTSMC020_BANK0_LOWLV_TIMING (FTSMC020_TPR_RBE | \
290 FTSMC020_TPR_AST(1) | \
291 FTSMC020_TPR_CTW(1) | \
292 FTSMC020_TPR_ATI(1) | \
293 FTSMC020_TPR_AT2(1) | \
294 FTSMC020_TPR_WTC(1) | \
295 FTSMC020_TPR_AHT(1) | \
296 FTSMC020_TPR_TRNA(1))
297#endif
298
299/*
300 * FLASH on ADP_AG101P is connected to BANK0
301 * Just disalbe the other BANK to avoid detection error.
302 */
303#define FTSMC020_BANK0_CONFIG (FTSMC020_BANK_ENABLE | \
304 FTSMC020_BANK_BASE(PHYS_FLASH_1) | \
305 FTSMC020_BANK_SIZE_32M | \
306 FTSMC020_BANK_MBW_32)
307
308#define FTSMC020_BANK0_TIMING (FTSMC020_TPR_AST(3) | \
309 FTSMC020_TPR_CTW(3) | \
310 FTSMC020_TPR_ATI(0xf) | \
311 FTSMC020_TPR_AT2(3) | \
312 FTSMC020_TPR_WTC(3) | \
313 FTSMC020_TPR_AHT(3) | \
314 FTSMC020_TPR_TRNA(0xf))
315
316#define FTSMC020_BANK1_CONFIG (0x00)
317#define FTSMC020_BANK1_TIMING (0x00)
318#endif /* CONFIG_FTSMC020 */
319
320/*
321 * FLASH and environment organization
322 */
323/* use CFI framework */
324#define CONFIG_SYS_FLASH_CFI
325#define CONFIG_FLASH_CFI_DRIVER
326
327#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
328#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
329
330/* support JEDEC */
331
332/* Do not use CONFIG_FLASH_CFI_LEGACY to detect on board flash */
333#ifdef CONFIG_SKIP_LOWLEVEL_INIT
334#define PHYS_FLASH_1 0x80400000 /* BANK 1 */
335#else /* !CONFIG_SKIP_LOWLEVEL_INIT */
336#ifdef CONFIG_MEM_REMAP
337#define PHYS_FLASH_1 0x80000000 /* BANK 0 */
338#else
339#define PHYS_FLASH_1 0x00000000 /* BANK 0 */
340#endif /* CONFIG_MEM_REMAP */
341#endif /* CONFIG_SKIP_LOWLEVEL_INIT */
342
343#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
344#define CONFIG_SYS_FLASH_BANKS_LIST { PHYS_FLASH_1, }
345#define CONFIG_SYS_MONITOR_BASE PHYS_FLASH_1
346
347#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* TO for Flash Erase (ms) */
348#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* TO for Flash Write (ms) */
349
350/* max number of memory banks */
351/*
352 * There are 4 banks supported for this Controller,
353 * but we have only 1 bank connected to flash on board
354 */
355#define CONFIG_SYS_MAX_FLASH_BANKS 1
356
357/* max number of sectors on one chip */
358#define CONFIG_FLASH_SECTOR_SIZE (0x10000*2*2)
359#define CONFIG_ENV_SECT_SIZE CONFIG_FLASH_SECTOR_SIZE
360#define CONFIG_SYS_MAX_FLASH_SECT 128
361
362/* environments */
363#define CONFIG_ENV_IS_IN_FLASH
364#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x140000)
365#define CONFIG_ENV_SIZE 8192
366#define CONFIG_ENV_OVERWRITE
367
368#endif /* __CONFIG_H */