blob: 7927ea9a50289e16486071a73333f45bbb1f2395 [file] [log] [blame]
wdenk16f21702002-08-26 21:58:50 +00001/*
2 * (C) Copyright 2000, 2001
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 * Ulrich Lutz, Speech Design GmbH, ulutz@datalab.de.
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24
25#include <common.h>
26#include <mpc8xx.h>
27#include <commproc.h>
28
29#ifdef CONFIG_STATUS_LED
30# include <status_led.h>
31#endif
32
33/* ------------------------------------------------------------------------- */
34
35static long int dram_size (long int, long int *, long int);
36
37/* ------------------------------------------------------------------------- */
38
39#define _NOT_USED_ 0xFFFFFFFF
40
41/*
42 * 50 MHz SHARC access using UPM A
43 */
wdenkc83bf6a2004-01-06 22:38:14 +000044const uint sharc_table[] = {
wdenk16f21702002-08-26 21:58:50 +000045 /*
46 * Single Read. (Offset 0 in UPM RAM)
47 */
48 0x0FF3FC04, 0x0FF3EC00, 0x7FFFEC04, 0xFFFFEC04,
wdenkc83bf6a2004-01-06 22:38:14 +000049 0xFFFFEC05, /* last */
50 _NOT_USED_, _NOT_USED_, _NOT_USED_,
wdenk16f21702002-08-26 21:58:50 +000051 /*
52 * Burst Read. (Offset 8 in UPM RAM)
53 */
54 /* last */
55 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
56 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
57 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
58 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
59 /*
60 * Single Write. (Offset 18 in UPM RAM)
61 */
62 0x0FAFFC04, 0x0FAFEC00, 0x7FFFEC04, 0xFFFFEC04,
wdenkc83bf6a2004-01-06 22:38:14 +000063 0xFFFFEC05, /* last */
64 _NOT_USED_, _NOT_USED_, _NOT_USED_,
wdenk16f21702002-08-26 21:58:50 +000065 /*
66 * Burst Write. (Offset 20 in UPM RAM)
67 */
68 /* last */
69 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
70 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
71 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
72 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
73 /*
74 * Refresh (Offset 30 in UPM RAM)
75 */
76 /* last */
77 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
78 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
79 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
80 /*
81 * Exception. (Offset 3c in UPM RAM)
82 */
wdenkc83bf6a2004-01-06 22:38:14 +000083 0x7FFFFC07, /* last */
84 _NOT_USED_, _NOT_USED_, _NOT_USED_,
wdenk16f21702002-08-26 21:58:50 +000085};
86
87
88/*
89 * 50 MHz SDRAM access using UPM B
90 */
wdenkc83bf6a2004-01-06 22:38:14 +000091const uint sdram_table[] = {
wdenk16f21702002-08-26 21:58:50 +000092 /*
93 * Single Read. (Offset 0 in UPM RAM)
94 */
95 0x0E26FC04, 0x11ADFC04, 0xEFBBBC00, 0x1FF77C45, /* last */
96 _NOT_USED_,
97 /*
98 * SDRAM Initialization (offset 5 in UPM RAM)
99 *
wdenk8bde7f72003-06-27 21:31:46 +0000100 * This is no UPM entry point. The following definition uses
101 * the remaining space to establish an initialization
102 * sequence, which is executed by a RUN command.
wdenk16f21702002-08-26 21:58:50 +0000103 *
104 */
wdenkc83bf6a2004-01-06 22:38:14 +0000105 0x1FF77C35, 0xEFEABC34, 0x1FB57C35, /* last */
wdenk16f21702002-08-26 21:58:50 +0000106 /*
107 * Burst Read. (Offset 8 in UPM RAM)
108 */
109 0x0E26FC04, 0x10ADFC04, 0xF0AFFC00, 0xF0AFFC00,
wdenkc83bf6a2004-01-06 22:38:14 +0000110 0xF1AFFC00, 0xEFBBBC00, 0x1FF77C45, /* last */
111 _NOT_USED_,
wdenk16f21702002-08-26 21:58:50 +0000112 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
113 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
114 /*
115 * Single Write. (Offset 18 in UPM RAM)
116 */
wdenkc83bf6a2004-01-06 22:38:14 +0000117 0x1F27FC04, 0xEEAEBC04, 0x01B93C00, 0x1FF77C45, /* last */
wdenk16f21702002-08-26 21:58:50 +0000118 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
119 /*
120 * Burst Write. (Offset 20 in UPM RAM)
121 */
122 0x0E26BC00, 0x10AD7C00, 0xF0AFFC00, 0xF0AFFC00,
wdenkc83bf6a2004-01-06 22:38:14 +0000123 0xE1BBBC04, 0x1FF77C45, /* last */
124 _NOT_USED_, _NOT_USED_,
wdenk16f21702002-08-26 21:58:50 +0000125 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
126 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
127 /*
128 * Refresh (Offset 30 in UPM RAM)
129 */
130 0x1FF5FC84, 0xFFFFFC04, 0xFFFFFC04, 0xFFFFFC84,
wdenkc83bf6a2004-01-06 22:38:14 +0000131 0xFFFFFC05, /* last */
132 _NOT_USED_, _NOT_USED_, _NOT_USED_,
wdenk16f21702002-08-26 21:58:50 +0000133 _NOT_USED_, _NOT_USED_, _NOT_USED_, _NOT_USED_,
134 /*
135 * Exception. (Offset 3c in UPM RAM)
136 */
wdenkc83bf6a2004-01-06 22:38:14 +0000137 0x7FFFFC07, /* last */
138 _NOT_USED_, _NOT_USED_, _NOT_USED_,
wdenk16f21702002-08-26 21:58:50 +0000139};
140
141/* ------------------------------------------------------------------------- */
142
143
144/*
145 * Check Board Identity:
146 *
147 */
148
149int checkboard (void)
150{
151#ifdef CONFIG_IVMS8
152 puts ("Board: IVMS8\n");
153#endif
154#ifdef CONFIG_IVML24
155 puts ("Board: IVM-L8/24\n");
156#endif
157 return (0);
158}
159
160/* ------------------------------------------------------------------------- */
161
wdenkc83bf6a2004-01-06 22:38:14 +0000162long int initdram (int board_type)
wdenk16f21702002-08-26 21:58:50 +0000163{
wdenkc83bf6a2004-01-06 22:38:14 +0000164 volatile immap_t *immr = (immap_t *) CFG_IMMR;
165 volatile memctl8xx_t *memctl = &immr->im_memctl;
166 long int size_b0;
wdenk16f21702002-08-26 21:58:50 +0000167
wdenkc83bf6a2004-01-06 22:38:14 +0000168 /* enable SDRAM clock ("switch on" SDRAM) */
169 immr->im_cpm.cp_pbpar &= ~(CFG_PB_SDRAM_CLKE); /* GPIO */
170 immr->im_cpm.cp_pbodr &= ~(CFG_PB_SDRAM_CLKE); /* active output */
171 immr->im_cpm.cp_pbdir |= CFG_PB_SDRAM_CLKE; /* output */
172 immr->im_cpm.cp_pbdat |= CFG_PB_SDRAM_CLKE; /* assert SDRAM CLKE */
173 udelay (1);
wdenk16f21702002-08-26 21:58:50 +0000174
wdenkc83bf6a2004-01-06 22:38:14 +0000175 /*
176 * Map controller bank 1 for ELIC SACCO
177 */
178 memctl->memc_or1 = CFG_OR1;
179 memctl->memc_br1 = CFG_BR1;
wdenk16f21702002-08-26 21:58:50 +0000180
wdenkc83bf6a2004-01-06 22:38:14 +0000181 /*
182 * Map controller bank 2 for ELIC EPIC
183 */
184 memctl->memc_or2 = CFG_OR2;
185 memctl->memc_br2 = CFG_BR2;
wdenk16f21702002-08-26 21:58:50 +0000186
wdenkc83bf6a2004-01-06 22:38:14 +0000187 /*
188 * Configure UPMA for SHARC
189 */
190 upmconfig (UPMA, (uint *) sharc_table,
191 sizeof (sharc_table) / sizeof (uint));
wdenk16f21702002-08-26 21:58:50 +0000192
193#if defined(CONFIG_IVML24)
wdenkc83bf6a2004-01-06 22:38:14 +0000194 /*
195 * Map controller bank 4 for HDLC Address space
196 */
197 memctl->memc_or4 = CFG_OR4;
198 memctl->memc_br4 = CFG_BR4;
wdenk16f21702002-08-26 21:58:50 +0000199#endif
200
wdenkc83bf6a2004-01-06 22:38:14 +0000201 /*
202 * Map controller bank 5 for SHARC
203 */
204 memctl->memc_or5 = CFG_OR5;
205 memctl->memc_br5 = CFG_BR5;
wdenk16f21702002-08-26 21:58:50 +0000206
wdenkc83bf6a2004-01-06 22:38:14 +0000207 memctl->memc_mamr = 0x00001000;
wdenk16f21702002-08-26 21:58:50 +0000208
wdenkc83bf6a2004-01-06 22:38:14 +0000209 /*
210 * Configure UPMB for SDRAM
211 */
212 upmconfig (UPMB, (uint *) sdram_table,
213 sizeof (sdram_table) / sizeof (uint));
wdenk16f21702002-08-26 21:58:50 +0000214
wdenkc83bf6a2004-01-06 22:38:14 +0000215 memctl->memc_mptpr = CFG_MPTPR_1BK_8K;
wdenk16f21702002-08-26 21:58:50 +0000216
wdenkc83bf6a2004-01-06 22:38:14 +0000217 memctl->memc_mar = 0x00000088;
wdenk16f21702002-08-26 21:58:50 +0000218
wdenkc83bf6a2004-01-06 22:38:14 +0000219 /*
220 * Map controller bank 3 to the SDRAM bank at preliminary address.
221 */
222 memctl->memc_or3 = CFG_OR3_PRELIM;
223 memctl->memc_br3 = CFG_BR3_PRELIM;
wdenk16f21702002-08-26 21:58:50 +0000224
wdenkc83bf6a2004-01-06 22:38:14 +0000225 memctl->memc_mbmr = CFG_MBMR_8COL; /* refresh not enabled yet */
wdenk16f21702002-08-26 21:58:50 +0000226
wdenkc83bf6a2004-01-06 22:38:14 +0000227 udelay (200);
228 memctl->memc_mcr = 0x80806105; /* precharge */
229 udelay (1);
230 memctl->memc_mcr = 0x80806106; /* load mode register */
231 udelay (1);
232 memctl->memc_mcr = 0x80806130; /* autorefresh */
233 udelay (1);
234 memctl->memc_mcr = 0x80806130; /* autorefresh */
235 udelay (1);
236 memctl->memc_mcr = 0x80806130; /* autorefresh */
237 udelay (1);
238 memctl->memc_mcr = 0x80806130; /* autorefresh */
239 udelay (1);
240 memctl->memc_mcr = 0x80806130; /* autorefresh */
241 udelay (1);
242 memctl->memc_mcr = 0x80806130; /* autorefresh */
243 udelay (1);
244 memctl->memc_mcr = 0x80806130; /* autorefresh */
245 udelay (1);
246 memctl->memc_mcr = 0x80806130; /* autorefresh */
wdenk16f21702002-08-26 21:58:50 +0000247
wdenkc83bf6a2004-01-06 22:38:14 +0000248 memctl->memc_mbmr |= MBMR_PTBE; /* refresh enabled */
wdenk16f21702002-08-26 21:58:50 +0000249
wdenkc83bf6a2004-01-06 22:38:14 +0000250 /*
251 * Check Bank 0 Memory Size for re-configuration
252 */
253 size_b0 =
Wolfgang Denk77ddac92005-10-13 16:45:02 +0200254 dram_size (CFG_MBMR_8COL, (long *) SDRAM_BASE3_PRELIM,
wdenkc83bf6a2004-01-06 22:38:14 +0000255 SDRAM_MAX_SIZE);
wdenk16f21702002-08-26 21:58:50 +0000256
wdenkc83bf6a2004-01-06 22:38:14 +0000257 memctl->memc_mbmr = CFG_MBMR_8COL | MBMR_PTBE;
wdenk16f21702002-08-26 21:58:50 +0000258
wdenkc83bf6a2004-01-06 22:38:14 +0000259 return (size_b0);
wdenk16f21702002-08-26 21:58:50 +0000260}
261
262/* ------------------------------------------------------------------------- */
263
264/*
265 * Check memory range for valid RAM. A simple memory test determines
266 * the actually available RAM size between addresses `base' and
267 * `base + maxsize'. Some (not all) hardware errors are detected:
268 * - short between address lines
269 * - short between data lines
270 */
271
wdenkc83bf6a2004-01-06 22:38:14 +0000272static long int dram_size (long int mamr_value, long int *base,
273 long int maxsize)
wdenk16f21702002-08-26 21:58:50 +0000274{
wdenkc83bf6a2004-01-06 22:38:14 +0000275 volatile immap_t *immr = (immap_t *) CFG_IMMR;
276 volatile memctl8xx_t *memctl = &immr->im_memctl;
wdenk16f21702002-08-26 21:58:50 +0000277
wdenkc83bf6a2004-01-06 22:38:14 +0000278 memctl->memc_mbmr = mamr_value;
wdenk16f21702002-08-26 21:58:50 +0000279
wdenkc83bf6a2004-01-06 22:38:14 +0000280 return (get_ram_size (base, maxsize));
wdenk16f21702002-08-26 21:58:50 +0000281}
282
283/* ------------------------------------------------------------------------- */
284
wdenkc83bf6a2004-01-06 22:38:14 +0000285void reset_phy (void)
wdenk16f21702002-08-26 21:58:50 +0000286{
wdenkc83bf6a2004-01-06 22:38:14 +0000287 immap_t *immr = (immap_t *) CFG_IMMR;
wdenk16f21702002-08-26 21:58:50 +0000288
289 /* De-assert Ethernet Powerdown */
wdenkc83bf6a2004-01-06 22:38:14 +0000290 immr->im_cpm.cp_pbpar &= ~(CFG_PB_ETH_POWERDOWN); /* GPIO */
291 immr->im_cpm.cp_pbodr &= ~(CFG_PB_ETH_POWERDOWN); /* active output */
292 immr->im_cpm.cp_pbdir |= CFG_PB_ETH_POWERDOWN; /* output */
293 immr->im_cpm.cp_pbdat &= ~(CFG_PB_ETH_POWERDOWN); /* Enable PHY power */
294 udelay (1000);
wdenk16f21702002-08-26 21:58:50 +0000295
296 /*
wdenk8bde7f72003-06-27 21:31:46 +0000297 * RESET is implemented by a positive pulse of at least 1 us
298 * at the reset pin.
wdenk16f21702002-08-26 21:58:50 +0000299 *
300 * Configure RESET pins for NS DP83843 PHY, and RESET chip.
301 *
302 * Note: The RESET pin is high active, but there is an
wdenkc83bf6a2004-01-06 22:38:14 +0000303 * inverter on the SPD823TS board...
wdenk16f21702002-08-26 21:58:50 +0000304 */
305 immr->im_ioport.iop_pcpar &= ~(CFG_PC_ETH_RESET);
wdenkc83bf6a2004-01-06 22:38:14 +0000306 immr->im_ioport.iop_pcdir |= CFG_PC_ETH_RESET;
wdenk16f21702002-08-26 21:58:50 +0000307 /* assert RESET signal of PHY */
308 immr->im_ioport.iop_pcdat &= ~(CFG_PC_ETH_RESET);
309 udelay (10);
310 /* de-assert RESET signal of PHY */
wdenkc83bf6a2004-01-06 22:38:14 +0000311 immr->im_ioport.iop_pcdat |= CFG_PC_ETH_RESET;
wdenk16f21702002-08-26 21:58:50 +0000312 udelay (10);
313}
314
315/* ------------------------------------------------------------------------- */
316
317void show_boot_progress (int status)
318{
319#if defined(CONFIG_STATUS_LED)
320# if defined(STATUS_LED_YELLOW)
321 status_led_set (STATUS_LED_YELLOW,
322 (status < 0) ? STATUS_LED_ON : STATUS_LED_OFF);
wdenkc83bf6a2004-01-06 22:38:14 +0000323# endif /* STATUS_LED_YELLOW */
wdenk16f21702002-08-26 21:58:50 +0000324# if defined(STATUS_LED_BOOT)
325 if (status == 6)
wdenkc83bf6a2004-01-06 22:38:14 +0000326 status_led_set (STATUS_LED_BOOT, STATUS_LED_OFF);
327# endif /* STATUS_LED_BOOT */
wdenk16f21702002-08-26 21:58:50 +0000328#endif /* CONFIG_STATUS_LED */
329}
330
331/* ------------------------------------------------------------------------- */
332
wdenkc83bf6a2004-01-06 22:38:14 +0000333void ide_set_reset (int on)
wdenk16f21702002-08-26 21:58:50 +0000334{
wdenkc83bf6a2004-01-06 22:38:14 +0000335 volatile immap_t *immr = (immap_t *) CFG_IMMR;
wdenk16f21702002-08-26 21:58:50 +0000336
337 /*
338 * Configure PC for IDE Reset Pin
339 */
340 if (on) { /* assert RESET */
341 immr->im_ioport.iop_pcdat &= ~(CFG_PC_IDE_RESET);
342 } else { /* release RESET */
wdenkc83bf6a2004-01-06 22:38:14 +0000343 immr->im_ioport.iop_pcdat |= CFG_PC_IDE_RESET;
wdenk16f21702002-08-26 21:58:50 +0000344 }
345
346 /* program port pin as GPIO output */
347 immr->im_ioport.iop_pcpar &= ~(CFG_PC_IDE_RESET);
wdenkc83bf6a2004-01-06 22:38:14 +0000348 immr->im_ioport.iop_pcso &= ~(CFG_PC_IDE_RESET);
349 immr->im_ioport.iop_pcdir |= CFG_PC_IDE_RESET;
wdenk16f21702002-08-26 21:58:50 +0000350}
351
352/* ------------------------------------------------------------------------- */