blob: 9b3117341e9ead6cf3275c7d585ab33d930c7393 [file] [log] [blame]
Shengzhou Liuf6050792014-11-24 17:11:54 +08001/* Copyright 2014 Freescale Semiconductor, Inc.
2 *
3 * Shengzhou Liu <Shengzhou.Liu@freescale.com>
4 *
5 * SPDX-License-Identifier: GPL-2.0+
6 */
7
8#include <common.h>
9#include <phy.h>
10#include <fm_eth.h>
11#include <asm/immap_85xx.h>
12#include <asm/fsl_serdes.h>
13
14u32 port_to_devdisr[] = {
15 [FM1_DTSEC1] = FSL_CORENET_DEVDISR2_DTSEC1_1,
16 [FM1_DTSEC2] = FSL_CORENET_DEVDISR2_DTSEC1_2,
17 [FM1_DTSEC3] = FSL_CORENET_DEVDISR2_DTSEC1_3,
18 [FM1_DTSEC4] = FSL_CORENET_DEVDISR2_DTSEC1_4,
19 [FM1_10GEC1] = FSL_CORENET_DEVDISR2_10GEC1_1, /* MAC1 */
20};
21
22static int is_device_disabled(enum fm_port port)
23{
24 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
25 u32 devdisr2 = in_be32(&gur->devdisr2);
26
27 return port_to_devdisr[port] & devdisr2;
28}
29
30void fman_disable_port(enum fm_port port)
31{
32 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
33
34 setbits_be32(&gur->devdisr2, port_to_devdisr[port]);
35}
36
37phy_interface_t fman_port_enet_if(enum fm_port port)
38{
39 ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
40 u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
41
42 if (is_device_disabled(port))
43 return PHY_INTERFACE_MODE_NONE;
44
45 if ((port == FM1_10GEC1) && (is_serdes_configured(XFI_FM1_MAC1)))
46 return PHY_INTERFACE_MODE_XGMII;
47
48 if ((port == FM1_DTSEC3) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) ==
49 FSL_CORENET_RCWSR13_EC2_RGMII) &&
50 (!is_serdes_configured(QSGMII_FM1_A)))
51 return PHY_INTERFACE_MODE_RGMII;
52
53 if ((port == FM1_DTSEC4) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) ==
54 FSL_CORENET_RCWSR13_EC1_RGMII) &&
55 (!is_serdes_configured(QSGMII_FM1_A)))
56 return PHY_INTERFACE_MODE_RGMII;
57
58 /* handle SGMII */
59 switch (port) {
60 case FM1_DTSEC1:
61 case FM1_DTSEC2:
62 case FM1_DTSEC3:
63 if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1))
64 return PHY_INTERFACE_MODE_SGMII;
65 else if (is_serdes_configured(SGMII_2500_FM1_DTSEC1
66 + port - FM1_DTSEC1))
67 return PHY_INTERFACE_MODE_SGMII_2500;
68 break;
69 default:
70 break;
71 }
72
73 /* handle QSGMII */
74 switch (port) {
75 case FM1_DTSEC1:
76 case FM1_DTSEC2:
77 case FM1_DTSEC3:
78 case FM1_DTSEC4:
79 /* check lane A on SerDes1 */
80 if (is_serdes_configured(QSGMII_FM1_A))
81 return PHY_INTERFACE_MODE_QSGMII;
82 break;
83 default:
84 break;
85 }
86
87 return PHY_INTERFACE_MODE_NONE;
88}