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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Gururaja Hebbar K R535cfa42008-08-25 11:30:29 +02002/*
3 * (C) Copyright 2008
4 * Gururaja Hebbar gururajakr@sanyo.co.in
5 *
6 * reference linux-2.6.20.6/drivers/rtc/rtc-pl031.c
Gururaja Hebbar K R535cfa42008-08-25 11:30:29 +02007 */
8
9#include <common.h>
10#include <command.h>
AKASHI Takahiroa370e422018-09-14 17:06:53 +090011#include <dm.h>
12#include <errno.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -060013#include <log.h>
Gururaja Hebbar K R535cfa42008-08-25 11:30:29 +020014#include <rtc.h>
AKASHI Takahiroa370e422018-09-14 17:06:53 +090015#include <asm/io.h>
16#include <asm/types.h>
Gururaja Hebbar K R535cfa42008-08-25 11:30:29 +020017
18/*
19 * Register definitions
20 */
21#define RTC_DR 0x00 /* Data read register */
22#define RTC_MR 0x04 /* Match register */
23#define RTC_LR 0x08 /* Data load register */
24#define RTC_CR 0x0c /* Control register */
25#define RTC_IMSC 0x10 /* Interrupt mask and set register */
26#define RTC_RIS 0x14 /* Raw interrupt status register */
27#define RTC_MIS 0x18 /* Masked interrupt status register */
28#define RTC_ICR 0x1c /* Interrupt clear register */
29
30#define RTC_CR_START (1 << 0)
31
Simon Glass8a8d24b2020-12-03 16:55:23 -070032struct pl031_plat {
AKASHI Takahiroa370e422018-09-14 17:06:53 +090033 phys_addr_t base;
34};
Gururaja Hebbar K R535cfa42008-08-25 11:30:29 +020035
AKASHI Takahiroa370e422018-09-14 17:06:53 +090036static inline u32 pl031_read_reg(struct udevice *dev, int reg)
Gururaja Hebbar K R535cfa42008-08-25 11:30:29 +020037{
Simon Glass8a8d24b2020-12-03 16:55:23 -070038 struct pl031_plat *pdata = dev_get_plat(dev);
Gururaja Hebbar K R535cfa42008-08-25 11:30:29 +020039
AKASHI Takahiroa370e422018-09-14 17:06:53 +090040 return readl(pdata->base + reg);
41}
42
43static inline u32 pl031_write_reg(struct udevice *dev, int reg, u32 value)
44{
Simon Glass8a8d24b2020-12-03 16:55:23 -070045 struct pl031_plat *pdata = dev_get_plat(dev);
AKASHI Takahiroa370e422018-09-14 17:06:53 +090046
47 return writel(value, pdata->base + reg);
Gururaja Hebbar K R535cfa42008-08-25 11:30:29 +020048}
49
50/*
AKASHI Takahiroa370e422018-09-14 17:06:53 +090051 * Probe RTC device
Gururaja Hebbar K R535cfa42008-08-25 11:30:29 +020052 */
AKASHI Takahiroa370e422018-09-14 17:06:53 +090053static int pl031_probe(struct udevice *dev)
Gururaja Hebbar K R535cfa42008-08-25 11:30:29 +020054{
AKASHI Takahiroa370e422018-09-14 17:06:53 +090055 /* Enable RTC Start in Control register*/
56 pl031_write_reg(dev, RTC_CR, RTC_CR_START);
Gururaja Hebbar K R535cfa42008-08-25 11:30:29 +020057
AKASHI Takahiroa370e422018-09-14 17:06:53 +090058 return 0;
Gururaja Hebbar K R535cfa42008-08-25 11:30:29 +020059}
60
61/*
62 * Get the current time from the RTC
63 */
AKASHI Takahiroa370e422018-09-14 17:06:53 +090064static int pl031_get(struct udevice *dev, struct rtc_time *tm)
Gururaja Hebbar K R535cfa42008-08-25 11:30:29 +020065{
AKASHI Takahiroa370e422018-09-14 17:06:53 +090066 unsigned long tim;
Gururaja Hebbar K R535cfa42008-08-25 11:30:29 +020067
AKASHI Takahiroa370e422018-09-14 17:06:53 +090068 if (!tm)
69 return -EINVAL;
Gururaja Hebbar K R535cfa42008-08-25 11:30:29 +020070
AKASHI Takahiroa370e422018-09-14 17:06:53 +090071 tim = pl031_read_reg(dev, RTC_DR);
Gururaja Hebbar K R535cfa42008-08-25 11:30:29 +020072
AKASHI Takahiroa370e422018-09-14 17:06:53 +090073 rtc_to_tm(tim, tm);
Gururaja Hebbar K R535cfa42008-08-25 11:30:29 +020074
AKASHI Takahiroa370e422018-09-14 17:06:53 +090075 debug("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
76 tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday,
77 tm->tm_hour, tm->tm_min, tm->tm_sec);
Gururaja Hebbar K R535cfa42008-08-25 11:30:29 +020078
79 return 0;
80}
81
AKASHI Takahiroa370e422018-09-14 17:06:53 +090082/*
83 * Set the RTC
84 */
85static int pl031_set(struct udevice *dev, const struct rtc_time *tm)
86{
87 unsigned long tim;
88
89 if (!tm)
90 return -EINVAL;
91
92 debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n",
93 tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_wday,
94 tm->tm_hour, tm->tm_min, tm->tm_sec);
95
96 /* Calculate number of seconds this incoming time represents */
97 tim = rtc_mktime(tm);
98
99 pl031_write_reg(dev, RTC_LR, tim);
100
101 return 0;
102}
103
104/*
105 * Reset the RTC. We set the date back to 1970-01-01.
106 */
107static int pl031_reset(struct udevice *dev)
108{
109 pl031_write_reg(dev, RTC_LR, 0);
110
111 return 0;
112}
113
114static const struct rtc_ops pl031_ops = {
115 .get = pl031_get,
116 .set = pl031_set,
117 .reset = pl031_reset,
118};
119
120static const struct udevice_id pl031_ids[] = {
121 { .compatible = "arm,pl031" },
122 { }
123};
124
Simon Glassd1998a92020-12-03 16:55:21 -0700125static int pl031_of_to_plat(struct udevice *dev)
AKASHI Takahiroa370e422018-09-14 17:06:53 +0900126{
Simon Glass8a8d24b2020-12-03 16:55:23 -0700127 struct pl031_plat *pdata = dev_get_plat(dev);
AKASHI Takahiroa370e422018-09-14 17:06:53 +0900128
129 pdata->base = dev_read_addr(dev);
130
131 return 0;
132}
133
134U_BOOT_DRIVER(rtc_pl031) = {
135 .name = "rtc-pl031",
136 .id = UCLASS_RTC,
137 .of_match = pl031_ids,
138 .probe = pl031_probe,
Simon Glassd1998a92020-12-03 16:55:21 -0700139 .of_to_plat = pl031_of_to_plat,
Simon Glass8a8d24b2020-12-03 16:55:23 -0700140 .plat_auto = sizeof(struct pl031_plat),
AKASHI Takahiroa370e422018-09-14 17:06:53 +0900141 .ops = &pl031_ops,
142};