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Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Jagan Teki46d0a992015-08-17 18:38:06 +05302/*
3 * (C) Copyright 2013 Xilinx, Inc.
4 * (C) Copyright 2015 Jagan Teki <jteki@openedev.com>
5 *
6 * Xilinx Zynq Quad-SPI(QSPI) controller driver (master mode only)
Jagan Teki46d0a992015-08-17 18:38:06 +05307 */
8
T Karthik Reddyea836be2020-02-04 05:47:45 -07009#include <clk.h>
Jagan Teki46d0a992015-08-17 18:38:06 +053010#include <common.h>
11#include <dm.h>
T Karthik Reddyea836be2020-02-04 05:47:45 -070012#include <dm/device_compat.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -060013#include <log.h>
Jagan Teki46d0a992015-08-17 18:38:06 +053014#include <malloc.h>
15#include <spi.h>
Simon Glass401d1c42020-10-30 21:38:53 -060016#include <asm/global_data.h>
Jagan Teki46d0a992015-08-17 18:38:06 +053017#include <asm/io.h>
Simon Glasscd93d622020-05-10 11:40:13 -060018#include <linux/bitops.h>
T Karthik Reddybab0c022022-01-30 22:22:40 -070019#include <spi-mem.h>
Jagan Teki46d0a992015-08-17 18:38:06 +053020
21DECLARE_GLOBAL_DATA_PTR;
22
23/* zynq qspi register bit masks ZYNQ_QSPI_<REG>_<BIT>_MASK */
Jagan Teki736b4df2015-10-22 20:40:16 +053024#define ZYNQ_QSPI_CR_IFMODE_MASK BIT(31) /* Flash intrface mode*/
25#define ZYNQ_QSPI_CR_MSA_MASK BIT(15) /* Manual start enb */
26#define ZYNQ_QSPI_CR_MCS_MASK BIT(14) /* Manual chip select */
27#define ZYNQ_QSPI_CR_PCS_MASK BIT(10) /* Peri chip select */
Jagan Teki9cf2ffb2015-10-22 21:06:37 +053028#define ZYNQ_QSPI_CR_FW_MASK GENMASK(7, 6) /* FIFO width */
29#define ZYNQ_QSPI_CR_SS_MASK GENMASK(13, 10) /* Slave Select */
30#define ZYNQ_QSPI_CR_BAUD_MASK GENMASK(5, 3) /* Baud rate div */
Jagan Teki736b4df2015-10-22 20:40:16 +053031#define ZYNQ_QSPI_CR_CPHA_MASK BIT(2) /* Clock phase */
32#define ZYNQ_QSPI_CR_CPOL_MASK BIT(1) /* Clock polarity */
33#define ZYNQ_QSPI_CR_MSTREN_MASK BIT(0) /* Mode select */
34#define ZYNQ_QSPI_IXR_RXNEMPTY_MASK BIT(4) /* RX_FIFO_not_empty */
35#define ZYNQ_QSPI_IXR_TXOW_MASK BIT(2) /* TX_FIFO_not_full */
Jagan Teki9cf2ffb2015-10-22 21:06:37 +053036#define ZYNQ_QSPI_IXR_ALL_MASK GENMASK(6, 0) /* All IXR bits */
Jagan Teki736b4df2015-10-22 20:40:16 +053037#define ZYNQ_QSPI_ENR_SPI_EN_MASK BIT(0) /* SPI Enable */
Nathan Rossi04a44d32015-12-09 00:44:40 +100038#define ZYNQ_QSPI_LQSPICFG_LQMODE_MASK BIT(31) /* Linear QSPI Mode */
Jagan Teki46d0a992015-08-17 18:38:06 +053039
40/* zynq qspi Transmit Data Register */
41#define ZYNQ_QSPI_TXD_00_00_OFFSET 0x1C /* Transmit 4-byte inst */
42#define ZYNQ_QSPI_TXD_00_01_OFFSET 0x80 /* Transmit 1-byte inst */
43#define ZYNQ_QSPI_TXD_00_10_OFFSET 0x84 /* Transmit 2-byte inst */
44#define ZYNQ_QSPI_TXD_00_11_OFFSET 0x88 /* Transmit 3-byte inst */
45
46#define ZYNQ_QSPI_TXFIFO_THRESHOLD 1 /* Tx FIFO threshold level*/
47#define ZYNQ_QSPI_RXFIFO_THRESHOLD 32 /* Rx FIFO threshold level */
48
49#define ZYNQ_QSPI_CR_BAUD_MAX 8 /* Baud rate divisor max val */
50#define ZYNQ_QSPI_CR_BAUD_SHIFT 3 /* Baud rate divisor shift */
51#define ZYNQ_QSPI_CR_SS_SHIFT 10 /* Slave select shift */
52
Siva Durga Prasad Paladugu30671862022-01-30 22:22:39 -070053#define ZYNQ_QSPI_MAX_BAUD_RATE 0x7
54#define ZYNQ_QSPI_DEFAULT_BAUD_RATE 0x2
55
Jagan Teki46d0a992015-08-17 18:38:06 +053056#define ZYNQ_QSPI_FIFO_DEPTH 63
Ashok Reddy Somaf44bd3b2020-05-18 01:11:00 -060057#define ZYNQ_QSPI_WAIT (CONFIG_SYS_HZ / 100) /* 10 ms */
Jagan Teki46d0a992015-08-17 18:38:06 +053058
59/* zynq qspi register set */
60struct zynq_qspi_regs {
61 u32 cr; /* 0x00 */
62 u32 isr; /* 0x04 */
63 u32 ier; /* 0x08 */
64 u32 idr; /* 0x0C */
65 u32 imr; /* 0x10 */
66 u32 enr; /* 0x14 */
67 u32 dr; /* 0x18 */
68 u32 txd0r; /* 0x1C */
69 u32 drxr; /* 0x20 */
70 u32 sicr; /* 0x24 */
71 u32 txftr; /* 0x28 */
72 u32 rxftr; /* 0x2C */
73 u32 gpior; /* 0x30 */
74 u32 reserved0[19];
75 u32 txd1r; /* 0x80 */
76 u32 txd2r; /* 0x84 */
77 u32 txd3r; /* 0x88 */
Nathan Rossi04a44d32015-12-09 00:44:40 +100078 u32 reserved1[5];
79 u32 lqspicfg; /* 0xA0 */
80 u32 lqspists; /* 0xA4 */
Jagan Teki46d0a992015-08-17 18:38:06 +053081};
82
83/* zynq qspi platform data */
Simon Glass8a8d24b2020-12-03 16:55:23 -070084struct zynq_qspi_plat {
Jagan Teki46d0a992015-08-17 18:38:06 +053085 struct zynq_qspi_regs *regs;
86 u32 frequency; /* input frequency */
87 u32 speed_hz;
88};
89
90/* zynq qspi priv */
91struct zynq_qspi_priv {
92 struct zynq_qspi_regs *regs;
93 u8 cs;
94 u8 mode;
95 u8 fifo_depth;
96 u32 freq; /* required frequency */
Siva Durga Prasad Paladugu1acb7032022-07-15 19:31:16 +053097 u32 max_hz;
Jagan Teki46d0a992015-08-17 18:38:06 +053098 const void *tx_buf;
99 void *rx_buf;
100 unsigned len;
101 int bytes_to_transfer;
102 int bytes_to_receive;
103 unsigned int is_inst;
104 unsigned cs_change:1;
105};
106
Simon Glassd1998a92020-12-03 16:55:21 -0700107static int zynq_qspi_of_to_plat(struct udevice *bus)
Jagan Teki46d0a992015-08-17 18:38:06 +0530108{
Simon Glass0fd3d912020-12-22 19:30:28 -0700109 struct zynq_qspi_plat *plat = dev_get_plat(bus);
Jagan Teki46d0a992015-08-17 18:38:06 +0530110 const void *blob = gd->fdt_blob;
Simon Glasse160f7d2017-01-17 16:52:55 -0700111 int node = dev_of_offset(bus);
Jagan Teki46d0a992015-08-17 18:38:06 +0530112
113 plat->regs = (struct zynq_qspi_regs *)fdtdec_get_addr(blob,
114 node, "reg");
115
Jagan Teki46d0a992015-08-17 18:38:06 +0530116 return 0;
117}
118
Ashok Reddy Soma17fbb592020-01-28 07:39:04 -0700119/**
120 * zynq_qspi_init_hw - Initialize the hardware
121 * @priv: Pointer to the zynq_qspi_priv structure
122 *
123 * The default settings of the QSPI controller's configurable parameters on
124 * reset are
125 * - Master mode
126 * - Baud rate divisor is set to 2
127 * - Threshold value for TX FIFO not full interrupt is set to 1
128 * - Flash memory interface mode enabled
129 * - Size of the word to be transferred as 8 bit
130 * This function performs the following actions
131 * - Disable and clear all the interrupts
132 * - Enable manual slave select
133 * - Enable auto start
134 * - Deselect all the chip select lines
135 * - Set the size of the word to be transferred as 32 bit
136 * - Set the little endian mode of TX FIFO and
137 * - Enable the QSPI controller
138 */
Jagan Teki46d0a992015-08-17 18:38:06 +0530139static void zynq_qspi_init_hw(struct zynq_qspi_priv *priv)
140{
141 struct zynq_qspi_regs *regs = priv->regs;
142 u32 confr;
143
144 /* Disable QSPI */
145 writel(~ZYNQ_QSPI_ENR_SPI_EN_MASK, &regs->enr);
146
147 /* Disable Interrupts */
148 writel(ZYNQ_QSPI_IXR_ALL_MASK, &regs->idr);
149
150 /* Clear the TX and RX threshold reg */
151 writel(ZYNQ_QSPI_TXFIFO_THRESHOLD, &regs->txftr);
152 writel(ZYNQ_QSPI_RXFIFO_THRESHOLD, &regs->rxftr);
153
154 /* Clear the RX FIFO */
155 while (readl(&regs->isr) & ZYNQ_QSPI_IXR_RXNEMPTY_MASK)
156 readl(&regs->drxr);
157
158 /* Clear Interrupts */
159 writel(ZYNQ_QSPI_IXR_ALL_MASK, &regs->isr);
160
161 /* Manual slave select and Auto start */
162 confr = readl(&regs->cr);
163 confr &= ~ZYNQ_QSPI_CR_MSA_MASK;
164 confr |= ZYNQ_QSPI_CR_IFMODE_MASK | ZYNQ_QSPI_CR_MCS_MASK |
165 ZYNQ_QSPI_CR_PCS_MASK | ZYNQ_QSPI_CR_FW_MASK |
166 ZYNQ_QSPI_CR_MSTREN_MASK;
167 writel(confr, &regs->cr);
168
Nathan Rossi04a44d32015-12-09 00:44:40 +1000169 /* Disable the LQSPI feature */
170 confr = readl(&regs->lqspicfg);
171 confr &= ~ZYNQ_QSPI_LQSPICFG_LQMODE_MASK;
172 writel(confr, &regs->lqspicfg);
173
Jagan Teki46d0a992015-08-17 18:38:06 +0530174 /* Enable SPI */
175 writel(ZYNQ_QSPI_ENR_SPI_EN_MASK, &regs->enr);
176}
177
Siva Durga Prasad Paladugu1acb7032022-07-15 19:31:16 +0530178static int zynq_qspi_child_pre_probe(struct udevice *bus)
179{
180 struct spi_slave *slave = dev_get_parent_priv(bus);
181 struct zynq_qspi_priv *priv = dev_get_priv(bus->parent);
182
183 priv->max_hz = slave->max_hz;
184
185 return 0;
186}
187
Jagan Teki46d0a992015-08-17 18:38:06 +0530188static int zynq_qspi_probe(struct udevice *bus)
189{
Simon Glass8a8d24b2020-12-03 16:55:23 -0700190 struct zynq_qspi_plat *plat = dev_get_plat(bus);
Jagan Teki46d0a992015-08-17 18:38:06 +0530191 struct zynq_qspi_priv *priv = dev_get_priv(bus);
T Karthik Reddyea836be2020-02-04 05:47:45 -0700192 struct clk clk;
193 unsigned long clock;
194 int ret;
Jagan Teki46d0a992015-08-17 18:38:06 +0530195
196 priv->regs = plat->regs;
197 priv->fifo_depth = ZYNQ_QSPI_FIFO_DEPTH;
198
T Karthik Reddyea836be2020-02-04 05:47:45 -0700199 ret = clk_get_by_name(bus, "ref_clk", &clk);
200 if (ret < 0) {
201 dev_err(bus, "failed to get clock\n");
202 return ret;
203 }
204
205 clock = clk_get_rate(&clk);
206 if (IS_ERR_VALUE(clock)) {
207 dev_err(bus, "failed to get rate\n");
208 return clock;
209 }
210
211 ret = clk_enable(&clk);
Michal Simek9b7aac72021-02-09 15:28:15 +0100212 if (ret) {
T Karthik Reddyea836be2020-02-04 05:47:45 -0700213 dev_err(bus, "failed to enable clock\n");
214 return ret;
215 }
216
Jagan Teki46d0a992015-08-17 18:38:06 +0530217 /* init the zynq spi hw */
218 zynq_qspi_init_hw(priv);
219
T Karthik Reddyea836be2020-02-04 05:47:45 -0700220 plat->frequency = clock;
221 plat->speed_hz = plat->frequency / 2;
222
223 debug("%s: max-frequency=%d\n", __func__, plat->speed_hz);
224
Jagan Teki46d0a992015-08-17 18:38:06 +0530225 return 0;
226}
227
Ashok Reddy Soma17fbb592020-01-28 07:39:04 -0700228/**
Jagan Teki46d0a992015-08-17 18:38:06 +0530229 * zynq_qspi_read_data - Copy data to RX buffer
Ashok Reddy Soma17fbb592020-01-28 07:39:04 -0700230 * @priv: Pointer to the zynq_qspi_priv structure
Jagan Teki46d0a992015-08-17 18:38:06 +0530231 * @data: The 32 bit variable where data is stored
232 * @size: Number of bytes to be copied from data to RX buffer
233 */
234static void zynq_qspi_read_data(struct zynq_qspi_priv *priv, u32 data, u8 size)
235{
236 u8 byte3;
237
238 debug("%s: data 0x%04x rx_buf addr: 0x%08x size %d\n", __func__ ,
239 data, (unsigned)(priv->rx_buf), size);
240
241 if (priv->rx_buf) {
242 switch (size) {
243 case 1:
244 *((u8 *)priv->rx_buf) = data;
245 priv->rx_buf += 1;
246 break;
247 case 2:
Siva Durga Prasad Paladugu255537b2022-01-30 22:22:37 -0700248 *((u8 *)priv->rx_buf) = data;
249 priv->rx_buf += 1;
250 *((u8 *)priv->rx_buf) = (u8)(data >> 8);
251 priv->rx_buf += 1;
Jagan Teki46d0a992015-08-17 18:38:06 +0530252 break;
253 case 3:
Siva Durga Prasad Paladugu255537b2022-01-30 22:22:37 -0700254 *((u8 *)priv->rx_buf) = data;
255 priv->rx_buf += 1;
256 *((u8 *)priv->rx_buf) = (u8)(data >> 8);
257 priv->rx_buf += 1;
Jagan Teki46d0a992015-08-17 18:38:06 +0530258 byte3 = (u8)(data >> 16);
259 *((u8 *)priv->rx_buf) = byte3;
260 priv->rx_buf += 1;
261 break;
262 case 4:
263 /* Can not assume word aligned buffer */
264 memcpy(priv->rx_buf, &data, size);
265 priv->rx_buf += 4;
266 break;
267 default:
268 /* This will never execute */
269 break;
270 }
271 }
272 priv->bytes_to_receive -= size;
273 if (priv->bytes_to_receive < 0)
274 priv->bytes_to_receive = 0;
275}
276
Ashok Reddy Soma17fbb592020-01-28 07:39:04 -0700277/**
Jagan Teki46d0a992015-08-17 18:38:06 +0530278 * zynq_qspi_write_data - Copy data from TX buffer
Ashok Reddy Soma17fbb592020-01-28 07:39:04 -0700279 * @priv: Pointer to the zynq_qspi_priv structure
Jagan Teki46d0a992015-08-17 18:38:06 +0530280 * @data: Pointer to the 32 bit variable where data is to be copied
281 * @size: Number of bytes to be copied from TX buffer to data
282 */
283static void zynq_qspi_write_data(struct zynq_qspi_priv *priv,
284 u32 *data, u8 size)
285{
286 if (priv->tx_buf) {
287 switch (size) {
288 case 1:
289 *data = *((u8 *)priv->tx_buf);
290 priv->tx_buf += 1;
291 *data |= 0xFFFFFF00;
292 break;
293 case 2:
Siva Durga Prasad Paladugua5a387a2022-01-30 22:22:38 -0700294 *data = *((u8 *)priv->tx_buf);
295 priv->tx_buf += 1;
296 *data |= (*((u8 *)priv->tx_buf) << 8);
297 priv->tx_buf += 1;
Jagan Teki46d0a992015-08-17 18:38:06 +0530298 *data |= 0xFFFF0000;
299 break;
300 case 3:
Siva Durga Prasad Paladugua5a387a2022-01-30 22:22:38 -0700301 *data = *((u8 *)priv->tx_buf);
302 priv->tx_buf += 1;
303 *data |= (*((u8 *)priv->tx_buf) << 8);
304 priv->tx_buf += 1;
Jagan Teki46d0a992015-08-17 18:38:06 +0530305 *data |= (*((u8 *)priv->tx_buf) << 16);
306 priv->tx_buf += 1;
307 *data |= 0xFF000000;
308 break;
309 case 4:
310 /* Can not assume word aligned buffer */
311 memcpy(data, priv->tx_buf, size);
312 priv->tx_buf += 4;
313 break;
314 default:
315 /* This will never execute */
316 break;
317 }
318 } else {
319 *data = 0;
320 }
321
322 debug("%s: data 0x%08x tx_buf addr: 0x%08x size %d\n", __func__,
323 *data, (u32)priv->tx_buf, size);
324
325 priv->bytes_to_transfer -= size;
326 if (priv->bytes_to_transfer < 0)
327 priv->bytes_to_transfer = 0;
328}
329
Ashok Reddy Soma17fbb592020-01-28 07:39:04 -0700330/**
331 * zynq_qspi_chipselect - Select or deselect the chip select line
332 * @priv: Pointer to the zynq_qspi_priv structure
333 * @is_on: Select(1) or deselect (0) the chip select line
334 */
Jagan Teki46d0a992015-08-17 18:38:06 +0530335static void zynq_qspi_chipselect(struct zynq_qspi_priv *priv, int is_on)
336{
337 u32 confr;
338 struct zynq_qspi_regs *regs = priv->regs;
339
340 confr = readl(&regs->cr);
341
342 if (is_on) {
343 /* Select the slave */
344 confr &= ~ZYNQ_QSPI_CR_SS_MASK;
345 confr |= (~(1 << priv->cs) << ZYNQ_QSPI_CR_SS_SHIFT) &
346 ZYNQ_QSPI_CR_SS_MASK;
347 } else
348 /* Deselect the slave */
349 confr |= ZYNQ_QSPI_CR_SS_MASK;
350
351 writel(confr, &regs->cr);
352}
353
Ashok Reddy Soma17fbb592020-01-28 07:39:04 -0700354/**
Jagan Teki46d0a992015-08-17 18:38:06 +0530355 * zynq_qspi_fill_tx_fifo - Fills the TX FIFO with as many bytes as possible
Ashok Reddy Soma17fbb592020-01-28 07:39:04 -0700356 * @priv: Pointer to the zynq_qspi_priv structure
357 * @size: Number of bytes to be copied to fifo
Jagan Teki46d0a992015-08-17 18:38:06 +0530358 */
359static void zynq_qspi_fill_tx_fifo(struct zynq_qspi_priv *priv, u32 size)
360{
361 u32 data = 0;
362 u32 fifocount = 0;
363 unsigned len, offset;
364 struct zynq_qspi_regs *regs = priv->regs;
365 static const unsigned offsets[4] = {
366 ZYNQ_QSPI_TXD_00_00_OFFSET, ZYNQ_QSPI_TXD_00_01_OFFSET,
367 ZYNQ_QSPI_TXD_00_10_OFFSET, ZYNQ_QSPI_TXD_00_11_OFFSET };
368
369 while ((fifocount < size) &&
370 (priv->bytes_to_transfer > 0)) {
371 if (priv->bytes_to_transfer >= 4) {
372 if (priv->tx_buf) {
373 memcpy(&data, priv->tx_buf, 4);
374 priv->tx_buf += 4;
375 } else {
376 data = 0;
377 }
378 writel(data, &regs->txd0r);
379 priv->bytes_to_transfer -= 4;
380 fifocount++;
381 } else {
382 /* Write TXD1, TXD2, TXD3 only if TxFIFO is empty. */
383 if (!(readl(&regs->isr)
384 & ZYNQ_QSPI_IXR_TXOW_MASK) &&
385 !priv->rx_buf)
386 return;
387 len = priv->bytes_to_transfer;
388 zynq_qspi_write_data(priv, &data, len);
389 offset = (priv->rx_buf) ? offsets[0] : offsets[len];
390 writel(data, &regs->cr + (offset / 4));
391 }
392 }
393}
394
Ashok Reddy Soma17fbb592020-01-28 07:39:04 -0700395/**
Jagan Teki46d0a992015-08-17 18:38:06 +0530396 * zynq_qspi_irq_poll - Interrupt service routine of the QSPI controller
Ashok Reddy Soma17fbb592020-01-28 07:39:04 -0700397 * @priv: Pointer to the zynq_qspi structure
Jagan Teki46d0a992015-08-17 18:38:06 +0530398 *
399 * This function handles TX empty and Mode Fault interrupts only.
400 * On TX empty interrupt this function reads the received data from RX FIFO and
401 * fills the TX FIFO if there is any data remaining to be transferred.
402 * On Mode Fault interrupt this function indicates that transfer is completed,
403 * the SPI subsystem will identify the error as the remaining bytes to be
404 * transferred is non-zero.
405 *
406 * returns: 0 for poll timeout
407 * 1 transfer operation complete
408 */
409static int zynq_qspi_irq_poll(struct zynq_qspi_priv *priv)
410{
411 struct zynq_qspi_regs *regs = priv->regs;
412 u32 rxindex = 0;
413 u32 rxcount;
414 u32 status, timeout;
415
416 /* Poll until any of the interrupt status bits are set */
417 timeout = get_timer(0);
418 do {
419 status = readl(&regs->isr);
420 } while ((status == 0) &&
Ashok Reddy Somaf44bd3b2020-05-18 01:11:00 -0600421 (get_timer(timeout) < ZYNQ_QSPI_WAIT));
Jagan Teki46d0a992015-08-17 18:38:06 +0530422
423 if (status == 0) {
424 printf("zynq_qspi_irq_poll: Timeout!\n");
425 return -ETIMEDOUT;
426 }
427
428 writel(status, &regs->isr);
429
430 /* Disable all interrupts */
431 writel(ZYNQ_QSPI_IXR_ALL_MASK, &regs->idr);
432 if ((status & ZYNQ_QSPI_IXR_TXOW_MASK) ||
433 (status & ZYNQ_QSPI_IXR_RXNEMPTY_MASK)) {
434 /*
435 * This bit is set when Tx FIFO has < THRESHOLD entries. We have
436 * the THRESHOLD value set to 1, so this bit indicates Tx FIFO
437 * is empty
438 */
439 rxcount = priv->bytes_to_receive - priv->bytes_to_transfer;
440 rxcount = (rxcount % 4) ? ((rxcount/4)+1) : (rxcount/4);
441 while ((rxindex < rxcount) &&
442 (rxindex < ZYNQ_QSPI_RXFIFO_THRESHOLD)) {
443 /* Read out the data from the RX FIFO */
444 u32 data;
445 data = readl(&regs->drxr);
446
447 if (priv->bytes_to_receive >= 4) {
448 if (priv->rx_buf) {
449 memcpy(priv->rx_buf, &data, 4);
450 priv->rx_buf += 4;
451 }
452 priv->bytes_to_receive -= 4;
453 } else {
454 zynq_qspi_read_data(priv, data,
455 priv->bytes_to_receive);
456 }
457 rxindex++;
458 }
459
460 if (priv->bytes_to_transfer) {
461 /* There is more data to send */
462 zynq_qspi_fill_tx_fifo(priv,
463 ZYNQ_QSPI_RXFIFO_THRESHOLD);
464
465 writel(ZYNQ_QSPI_IXR_ALL_MASK, &regs->ier);
466 } else {
467 /*
468 * If transfer and receive is completed then only send
469 * complete signal
470 */
471 if (!priv->bytes_to_receive) {
472 /* return operation complete */
473 writel(ZYNQ_QSPI_IXR_ALL_MASK,
474 &regs->idr);
475 return 1;
476 }
477 }
478 }
479
480 return 0;
481}
482
Ashok Reddy Soma17fbb592020-01-28 07:39:04 -0700483/**
Jagan Teki46d0a992015-08-17 18:38:06 +0530484 * zynq_qspi_start_transfer - Initiates the QSPI transfer
Ashok Reddy Soma17fbb592020-01-28 07:39:04 -0700485 * @priv: Pointer to the zynq_qspi_priv structure
Jagan Teki46d0a992015-08-17 18:38:06 +0530486 *
487 * This function fills the TX FIFO, starts the QSPI transfer, and waits for the
488 * transfer to be completed.
489 *
490 * returns: Number of bytes transferred in the last transfer
491 */
492static int zynq_qspi_start_transfer(struct zynq_qspi_priv *priv)
493{
494 u32 data = 0;
495 struct zynq_qspi_regs *regs = priv->regs;
496
497 debug("%s: qspi: 0x%08x transfer: 0x%08x len: %d\n", __func__,
498 (u32)priv, (u32)priv, priv->len);
499
500 priv->bytes_to_transfer = priv->len;
501 priv->bytes_to_receive = priv->len;
502
503 if (priv->len < 4)
504 zynq_qspi_fill_tx_fifo(priv, priv->len);
505 else
506 zynq_qspi_fill_tx_fifo(priv, priv->fifo_depth);
507
508 writel(ZYNQ_QSPI_IXR_ALL_MASK, &regs->ier);
Jagan Teki46d0a992015-08-17 18:38:06 +0530509
510 /* wait for completion */
511 do {
512 data = zynq_qspi_irq_poll(priv);
513 } while (data == 0);
514
515 return (priv->len) - (priv->bytes_to_transfer);
516}
517
518static int zynq_qspi_transfer(struct zynq_qspi_priv *priv)
519{
520 unsigned cs_change = 1;
521 int status = 0;
522
523 while (1) {
524 /* Select the chip if required */
525 if (cs_change)
526 zynq_qspi_chipselect(priv, 1);
527
528 cs_change = priv->cs_change;
529
530 if (!priv->tx_buf && !priv->rx_buf && priv->len) {
531 status = -1;
532 break;
533 }
534
535 /* Request the transfer */
536 if (priv->len) {
537 status = zynq_qspi_start_transfer(priv);
538 priv->is_inst = 0;
539 }
540
541 if (status != priv->len) {
542 if (status > 0)
543 status = -EMSGSIZE;
544 debug("zynq_qspi_transfer:%d len:%d\n",
545 status, priv->len);
546 break;
547 }
548 status = 0;
549
550 if (cs_change)
551 /* Deselect the chip */
552 zynq_qspi_chipselect(priv, 0);
553
554 break;
555 }
556
Vipul Kumar240cd752018-06-25 14:13:57 +0530557 return status;
Jagan Teki46d0a992015-08-17 18:38:06 +0530558}
559
560static int zynq_qspi_claim_bus(struct udevice *dev)
561{
562 struct udevice *bus = dev->parent;
563 struct zynq_qspi_priv *priv = dev_get_priv(bus);
564 struct zynq_qspi_regs *regs = priv->regs;
565
566 writel(ZYNQ_QSPI_ENR_SPI_EN_MASK, &regs->enr);
567
568 return 0;
569}
570
571static int zynq_qspi_release_bus(struct udevice *dev)
572{
573 struct udevice *bus = dev->parent;
574 struct zynq_qspi_priv *priv = dev_get_priv(bus);
575 struct zynq_qspi_regs *regs = priv->regs;
576
577 writel(~ZYNQ_QSPI_ENR_SPI_EN_MASK, &regs->enr);
578
579 return 0;
580}
581
582static int zynq_qspi_xfer(struct udevice *dev, unsigned int bitlen,
583 const void *dout, void *din, unsigned long flags)
584{
585 struct udevice *bus = dev->parent;
586 struct zynq_qspi_priv *priv = dev_get_priv(bus);
Simon Glass8a8d24b2020-12-03 16:55:23 -0700587 struct dm_spi_slave_plat *slave_plat = dev_get_parent_plat(dev);
Jagan Teki46d0a992015-08-17 18:38:06 +0530588
589 priv->cs = slave_plat->cs;
590 priv->tx_buf = dout;
591 priv->rx_buf = din;
592 priv->len = bitlen / 8;
593
Jagan Tekie5e0d682015-10-25 09:31:54 +0530594 debug("zynq_qspi_xfer: bus:%i cs:%i bitlen:%i len:%i flags:%lx\n",
Simon Glass8b85dfc2020-12-16 21:20:07 -0700595 dev_seq(bus), slave_plat->cs, bitlen, priv->len, flags);
Jagan Teki46d0a992015-08-17 18:38:06 +0530596
597 /*
598 * Festering sore.
599 * Assume that the beginning of a transfer with bits to
600 * transmit must contain a device command.
601 */
602 if (dout && flags & SPI_XFER_BEGIN)
603 priv->is_inst = 1;
604 else
605 priv->is_inst = 0;
606
607 if (flags & SPI_XFER_END)
608 priv->cs_change = 1;
609 else
610 priv->cs_change = 0;
611
612 zynq_qspi_transfer(priv);
613
614 return 0;
615}
616
617static int zynq_qspi_set_speed(struct udevice *bus, uint speed)
618{
Simon Glass0fd3d912020-12-22 19:30:28 -0700619 struct zynq_qspi_plat *plat = dev_get_plat(bus);
Jagan Teki46d0a992015-08-17 18:38:06 +0530620 struct zynq_qspi_priv *priv = dev_get_priv(bus);
621 struct zynq_qspi_regs *regs = priv->regs;
622 uint32_t confr;
623 u8 baud_rate_val = 0;
624
Ashok Reddy Soma2a75bc12022-07-15 19:31:19 +0530625 if (!speed || speed > priv->max_hz)
626 speed = priv->max_hz;
Jagan Teki46d0a992015-08-17 18:38:06 +0530627
628 /* Set the clock frequency */
629 confr = readl(&regs->cr);
Ashok Reddy Soma2a75bc12022-07-15 19:31:19 +0530630 if (plat->speed_hz != speed) {
Jagan Teki46d0a992015-08-17 18:38:06 +0530631 while ((baud_rate_val < ZYNQ_QSPI_CR_BAUD_MAX) &&
632 ((plat->frequency /
633 (2 << baud_rate_val)) > speed))
634 baud_rate_val++;
635
Siva Durga Prasad Paladugu30671862022-01-30 22:22:39 -0700636 if (baud_rate_val > ZYNQ_QSPI_MAX_BAUD_RATE)
637 baud_rate_val = ZYNQ_QSPI_DEFAULT_BAUD_RATE;
638
Jagan Teki46d0a992015-08-17 18:38:06 +0530639 plat->speed_hz = speed / (2 << baud_rate_val);
640 }
641 confr &= ~ZYNQ_QSPI_CR_BAUD_MASK;
642 confr |= (baud_rate_val << ZYNQ_QSPI_CR_BAUD_SHIFT);
643
644 writel(confr, &regs->cr);
645 priv->freq = speed;
646
Jagan Tekie5e0d682015-10-25 09:31:54 +0530647 debug("%s: regs=%p, speed=%d\n", __func__, priv->regs, priv->freq);
Jagan Teki46d0a992015-08-17 18:38:06 +0530648
649 return 0;
650}
651
652static int zynq_qspi_set_mode(struct udevice *bus, uint mode)
653{
654 struct zynq_qspi_priv *priv = dev_get_priv(bus);
655 struct zynq_qspi_regs *regs = priv->regs;
656 uint32_t confr;
657
658 /* Set the SPI Clock phase and polarities */
659 confr = readl(&regs->cr);
660 confr &= ~(ZYNQ_QSPI_CR_CPHA_MASK | ZYNQ_QSPI_CR_CPOL_MASK);
661
Jagan Teki2775e912015-09-08 01:39:44 +0530662 if (mode & SPI_CPHA)
Jagan Teki46d0a992015-08-17 18:38:06 +0530663 confr |= ZYNQ_QSPI_CR_CPHA_MASK;
Jagan Teki2775e912015-09-08 01:39:44 +0530664 if (mode & SPI_CPOL)
Jagan Teki46d0a992015-08-17 18:38:06 +0530665 confr |= ZYNQ_QSPI_CR_CPOL_MASK;
666
667 writel(confr, &regs->cr);
668 priv->mode = mode;
669
Jagan Tekie5e0d682015-10-25 09:31:54 +0530670 debug("%s: regs=%p, mode=%d\n", __func__, priv->regs, priv->mode);
Jagan Teki46d0a992015-08-17 18:38:06 +0530671
672 return 0;
673}
674
T Karthik Reddybab0c022022-01-30 22:22:40 -0700675static int zynq_qspi_exec_op(struct spi_slave *slave,
676 const struct spi_mem_op *op)
677{
678 int op_len, pos = 0, ret, i;
679 unsigned int flag = 0;
680 const u8 *tx_buf = NULL;
681 u8 *rx_buf = NULL;
682
683 if (op->data.nbytes) {
684 if (op->data.dir == SPI_MEM_DATA_IN)
685 rx_buf = op->data.buf.in;
686 else
687 tx_buf = op->data.buf.out;
688 }
689
690 op_len = op->cmd.nbytes + op->addr.nbytes + op->dummy.nbytes;
691
692 u8 op_buf[op_len];
693
694 op_buf[pos++] = op->cmd.opcode;
695
696 if (op->addr.nbytes) {
697 for (i = 0; i < op->addr.nbytes; i++)
698 op_buf[pos + i] = op->addr.val >>
699 (8 * (op->addr.nbytes - i - 1));
700
701 pos += op->addr.nbytes;
702 }
703
Stefan Herbrechtsmeier99c1aba2023-04-27 08:53:54 +0200704 if (op->dummy.nbytes)
705 memset(op_buf + pos, 0xff, op->dummy.nbytes);
T Karthik Reddybab0c022022-01-30 22:22:40 -0700706
707 /* 1st transfer: opcode + address + dummy cycles */
708 /* Make sure to set END bit if no tx or rx data messages follow */
709 if (!tx_buf && !rx_buf)
710 flag |= SPI_XFER_END;
711
712 ret = zynq_qspi_xfer(slave->dev, op_len * 8, op_buf, NULL,
713 flag | SPI_XFER_BEGIN);
714 if (ret)
715 return ret;
716
717 /* 2nd transfer: rx or tx data path */
718 if (tx_buf || rx_buf) {
719 ret = zynq_qspi_xfer(slave->dev, op->data.nbytes * 8, tx_buf,
720 rx_buf, flag | SPI_XFER_END);
721 if (ret)
722 return ret;
723 }
724
725 spi_release_bus(slave);
726
727 return 0;
728}
729
Ashok Reddy Somabc479582022-07-15 19:31:18 +0530730static int zynq_qspi_check_buswidth(struct spi_slave *slave, u8 width)
731{
732 u32 mode = slave->mode;
733
734 switch (width) {
735 case 1:
736 return 0;
737 case 2:
738 if (mode & SPI_RX_DUAL)
739 return 0;
740 break;
741 case 4:
742 if (mode & SPI_RX_QUAD)
743 return 0;
744 break;
745 }
746
747 return -EOPNOTSUPP;
748}
749
Algapally Santosh Sagar0ebb68f2023-06-14 03:03:56 -0600750static bool zynq_qspi_mem_exec_op(struct spi_slave *slave,
751 const struct spi_mem_op *op)
Ashok Reddy Somabc479582022-07-15 19:31:18 +0530752{
753 if (zynq_qspi_check_buswidth(slave, op->cmd.buswidth))
754 return false;
755
756 if (op->addr.nbytes &&
757 zynq_qspi_check_buswidth(slave, op->addr.buswidth))
758 return false;
759
760 if (op->dummy.nbytes &&
761 zynq_qspi_check_buswidth(slave, op->dummy.buswidth))
762 return false;
763
764 if (op->data.dir != SPI_MEM_NO_DATA &&
765 zynq_qspi_check_buswidth(slave, op->data.buswidth))
766 return false;
767
768 return true;
769}
770
T Karthik Reddybab0c022022-01-30 22:22:40 -0700771static const struct spi_controller_mem_ops zynq_qspi_mem_ops = {
772 .exec_op = zynq_qspi_exec_op,
Ashok Reddy Somabc479582022-07-15 19:31:18 +0530773 .supports_op = zynq_qspi_mem_exec_op,
T Karthik Reddybab0c022022-01-30 22:22:40 -0700774};
775
Jagan Teki46d0a992015-08-17 18:38:06 +0530776static const struct dm_spi_ops zynq_qspi_ops = {
777 .claim_bus = zynq_qspi_claim_bus,
778 .release_bus = zynq_qspi_release_bus,
779 .xfer = zynq_qspi_xfer,
780 .set_speed = zynq_qspi_set_speed,
781 .set_mode = zynq_qspi_set_mode,
T Karthik Reddybab0c022022-01-30 22:22:40 -0700782 .mem_ops = &zynq_qspi_mem_ops,
Jagan Teki46d0a992015-08-17 18:38:06 +0530783};
784
785static const struct udevice_id zynq_qspi_ids[] = {
786 { .compatible = "xlnx,zynq-qspi-1.0" },
787 { }
788};
789
790U_BOOT_DRIVER(zynq_qspi) = {
791 .name = "zynq_qspi",
792 .id = UCLASS_SPI,
793 .of_match = zynq_qspi_ids,
794 .ops = &zynq_qspi_ops,
Simon Glassd1998a92020-12-03 16:55:21 -0700795 .of_to_plat = zynq_qspi_of_to_plat,
Simon Glass8a8d24b2020-12-03 16:55:23 -0700796 .plat_auto = sizeof(struct zynq_qspi_plat),
Simon Glass41575d82020-12-03 16:55:17 -0700797 .priv_auto = sizeof(struct zynq_qspi_priv),
Jagan Teki46d0a992015-08-17 18:38:06 +0530798 .probe = zynq_qspi_probe,
Siva Durga Prasad Paladugu1acb7032022-07-15 19:31:16 +0530799 .child_pre_probe = zynq_qspi_child_pre_probe,
Jagan Teki46d0a992015-08-17 18:38:06 +0530800};