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wdenk4a9cbbe2002-08-27 09:48:53 +00001/*
wdenk4532cb62003-04-27 22:52:51 +00002 * (C) Copyright 2000-2003
wdenk4a9cbbe2002-08-27 09:48:53 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
wdenk8564acf2003-07-14 22:13:32 +000025 * CPU specific code for the MPC825x / MPC826x / MPC827x / MPC828x
wdenk4a9cbbe2002-08-27 09:48:53 +000026 *
27 * written or collected and sometimes rewritten by
28 * Magnus Damm <damm@bitsmart.com>
29 *
wdenk4532cb62003-04-27 22:52:51 +000030 * modified by
wdenk4a9cbbe2002-08-27 09:48:53 +000031 * Wolfgang Denk <wd@denx.de>
32 *
33 * modified for 8260 by
34 * Murray Jensen <Murray.Jensen@cmst.csiro.au>
35 *
36 * added 8260 masks by
37 * Marius Groeger <mag@sysgo.de>
wdenk8564acf2003-07-14 22:13:32 +000038 *
39 * added HiP7 (8270/8275/8280) processors support by
40 * Yuli Barcohen <yuli@arabellasw.com>
wdenk4a9cbbe2002-08-27 09:48:53 +000041 */
42
43#include <common.h>
44#include <watchdog.h>
45#include <command.h>
46#include <mpc8260.h>
47#include <asm/processor.h>
48#include <asm/cpm_8260.h>
49
50int checkcpu (void)
51{
52 DECLARE_GLOBAL_DATA_PTR;
53
54 volatile immap_t *immap = (immap_t *) CFG_IMMR;
55 ulong clock = gd->cpu_clk;
56 uint pvr = get_pvr ();
57 uint immr, rev, m, k;
58 char buf[32];
59
60 puts ("CPU: ");
61
wdenk8564acf2003-07-14 22:13:32 +000062 switch (pvr) {
63 case PVR_8260:
64 case PVR_8260_HIP3:
65 k = 3;
66 break;
67 case PVR_8260_HIP4:
68 k = 4;
69 break;
70 case PVR_8260_HIP7:
71 k = 7;
72 break;
73 default:
wdenk4a9cbbe2002-08-27 09:48:53 +000074 return -1; /* whoops! not an MPC8260 */
wdenk8564acf2003-07-14 22:13:32 +000075 }
wdenk4a9cbbe2002-08-27 09:48:53 +000076 rev = pvr & 0xff;
77
78 immr = immap->im_memctl.memc_immr;
79 if ((immr & IMMR_ISB_MSK) != CFG_IMMR)
80 return -1; /* whoops! someone moved the IMMR */
81
wdenk8564acf2003-07-14 22:13:32 +000082 printf (CPU_ID_STR " (HiP%d Rev %02x, Mask ", k, rev);
wdenk4a9cbbe2002-08-27 09:48:53 +000083
84 /*
85 * the bottom 16 bits of the immr are the Part Number and Mask Number
86 * (4-34); the 16 bits at PROFF_REVNUM (0x8af0) in dual port ram is the
87 * RISC Microcode Revision Number (13-10).
88 * For the 8260, Motorola doesn't include the Microcode Revision
89 * in the mask.
90 */
91 m = immr & (IMMR_PARTNUM_MSK | IMMR_MASKNUM_MSK);
92 k = *((ushort *) & immap->im_dprambase[PROFF_REVNUM]);
93
94 switch (m) {
95 case 0x0000:
96 printf ("0.2 2J24M");
97 break;
98 case 0x0010:
99 printf ("A.0 K22A");
100 break;
101 case 0x0011:
102 printf ("A.1 1K22A-XC");
103 break;
104 case 0x0001:
105 printf ("B.1 1K23A");
106 break;
107 case 0x0021:
108 printf ("B.2 2K23A-XC");
109 break;
110 case 0x0023:
111 printf ("B.3 3K23A");
112 break;
113 case 0x0024:
114 printf ("C.2 6K23A");
115 break;
116 case 0x0060:
117 printf ("A.0(A) 2K25A");
118 break;
wdenk4532cb62003-04-27 22:52:51 +0000119 case 0x0062:
120 printf ("B.1 4K25A");
121 break;
wdenk8564acf2003-07-14 22:13:32 +0000122 case 0x0A00:
123 printf ("0.0 0K49M");
124 break;
125 case 0x0A01:
126 printf ("0.1 1K49M");
127 break;
wdenk4a9cbbe2002-08-27 09:48:53 +0000128 default:
129 printf ("unknown [immr=0x%04x,k=0x%04x]", m, k);
130 break;
131 }
132
133 printf (") at %s MHz\n", strmhz (buf, clock));
134
135 return 0;
136}
137
138/* ------------------------------------------------------------------------- */
139/* configures a UPM by writing into the UPM RAM array */
140/* uses bank 11 and a dummy physical address (=BRx_BA_MSK) */
141/* NOTE: the physical address chosen must not overlap into any other area */
142/* mapped by the memory controller because bank 11 has the lowest priority */
143
144void upmconfig (uint upm, uint * table, uint size)
145{
146 volatile immap_t *immap = (immap_t *) CFG_IMMR;
147 volatile memctl8260_t *memctl = &immap->im_memctl;
148 volatile uchar *dummy = (uchar *) BRx_BA_MSK; /* set all BA bits */
149 uint i;
150
151 /* first set up bank 11 to reference the correct UPM at a dummy address */
152
153 memctl->memc_or11 = ORxU_AM_MSK; /* set all AM bits */
154
155 switch (upm) {
156
157 case UPMA:
158 memctl->memc_br11 =
159 ((uint)dummy & BRx_BA_MSK) | BRx_PS_32 | BRx_MS_UPMA |
160 BRx_V;
161 memctl->memc_mamr = MxMR_OP_WARR;
162 break;
163
164 case UPMB:
165 memctl->memc_br11 =
166 ((uint)dummy & BRx_BA_MSK) | BRx_PS_32 | BRx_MS_UPMB |
167 BRx_V;
168 memctl->memc_mbmr = MxMR_OP_WARR;
169 break;
170
171 case UPMC:
172 memctl->memc_br11 =
173 ((uint)dummy & BRx_BA_MSK) | BRx_PS_32 | BRx_MS_UPMC |
174 BRx_V;
175 memctl->memc_mcmr = MxMR_OP_WARR;
176 break;
177
178 default:
179 panic ("upmconfig passed invalid UPM number (%u)\n", upm);
180 break;
181
182 }
183
184 /*
185 * at this point, the dummy address is set up to access the selected UPM,
186 * the MAD pointer is zero, and the MxMR OP is set for writing to RAM
187 *
188 * now we simply load the mdr with each word and poke the dummy address.
189 * the MAD is incremented on each access.
190 */
191
192 for (i = 0; i < size; i++) {
193 memctl->memc_mdr = table[i];
194 *dummy = 0;
195 }
196
197 /* now kill bank 11 */
198 memctl->memc_br11 = 0;
199}
200
201/* ------------------------------------------------------------------------- */
202
203int
wdenk8bde7f72003-06-27 21:31:46 +0000204do_reset (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
wdenk4a9cbbe2002-08-27 09:48:53 +0000205{
206 ulong msr, addr;
207
208 volatile immap_t *immap = (immap_t *) CFG_IMMR;
209
210 immap->im_clkrst.car_rmr = RMR_CSRE; /* Checkstop Reset enable */
211
212 /* Interrupts and MMU off */
213 __asm__ __volatile__ ("mfmsr %0":"=r" (msr):);
214
215 msr &= ~(MSR_ME | MSR_EE | MSR_IR | MSR_DR);
216 __asm__ __volatile__ ("mtmsr %0"::"r" (msr));
217
218 /*
219 * Trying to execute the next instruction at a non-existing address
220 * should cause a machine check, resulting in reset
221 */
222#ifdef CFG_RESET_ADDRESS
223 addr = CFG_RESET_ADDRESS;
224#else
225 /*
226 * note: when CFG_MONITOR_BASE points to a RAM address, CFG_MONITOR_BASE
227 * - sizeof (ulong) is usually a valid address. Better pick an address
228 * known to be invalid on your system and assign it to CFG_RESET_ADDRESS.
229 */
230 addr = CFG_MONITOR_BASE - sizeof (ulong);
231#endif
232 ((void (*)(void)) addr) ();
233 return 1;
234
235}
236
237/* ------------------------------------------------------------------------- */
238
239/*
240 * Get timebase clock frequency (like cpu_clk in Hz)
241 *
242 */
243unsigned long get_tbclk (void)
244{
245 DECLARE_GLOBAL_DATA_PTR;
246
247 ulong tbclk;
248
249 tbclk = (gd->bus_clk + 3L) / 4L;
250
251 return (tbclk);
252}
253
254/* ------------------------------------------------------------------------- */
255
256#if defined(CONFIG_WATCHDOG)
257void watchdog_reset (void)
258{
259 int re_enable = disable_interrupts ();
260
261 reset_8260_watchdog ((immap_t *) CFG_IMMR);
262 if (re_enable)
263 enable_interrupts ();
264}
265#endif /* CONFIG_WATCHDOG */
266
267/* ------------------------------------------------------------------------- */