wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2001 |
| 3 | * Stuart Hughes <stuarth@lineo.com> |
| 4 | * This file is based on similar values for other boards found in other |
| 5 | * U-Boot config files, and some that I found in the mpc8260ads manual. |
| 6 | * |
| 7 | * Note: my board is a PILOT rev. |
| 8 | * Note: the mpc8260ads doesn't come with a proper Ethernet MAC address. |
| 9 | * |
wdenk | cceb871 | 2003-06-23 18:12:28 +0000 | [diff] [blame] | 10 | * (C) Copyright 2003 Arabella Software Ltd. |
| 11 | * Yuli Barcohen <yuli@arabellasw.com> |
| 12 | * Added support for SDRAM DIMMs SPD EEPROM, MII. |
| 13 | * |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 14 | * See file CREDITS for list of people who contributed to this |
| 15 | * project. |
| 16 | * |
| 17 | * This program is free software; you can redistribute it and/or |
| 18 | * modify it under the terms of the GNU General Public License as |
| 19 | * published by the Free Software Foundation; either version 2 of |
| 20 | * the License, or (at your option) any later version. |
| 21 | * |
| 22 | * This program is distributed in the hope that it will be useful, |
| 23 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 24 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 25 | * GNU General Public License for more details. |
| 26 | * |
| 27 | * You should have received a copy of the GNU General Public License |
| 28 | * along with this program; if not, write to the Free Software |
| 29 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 30 | * MA 02111-1307 USA |
| 31 | */ |
| 32 | |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 33 | #ifndef __CONFIG_H |
| 34 | #define __CONFIG_H |
| 35 | |
| 36 | /* |
| 37 | * High Level Configuration Options |
| 38 | * (easy to change) |
| 39 | */ |
| 40 | |
| 41 | #define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ |
| 42 | #define CONFIG_MPC8260ADS 1 /* ...on motorola ads board */ |
| 43 | |
| 44 | #define CONFIG_BOARD_PRE_INIT 1 /* Call board_pre_init */ |
| 45 | |
| 46 | /* allow serial and ethaddr to be overwritten */ |
| 47 | #define CONFIG_ENV_OVERWRITE |
| 48 | |
| 49 | /* |
| 50 | * select serial console configuration |
| 51 | * |
| 52 | * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then |
| 53 | * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 |
| 54 | * for SCC). |
| 55 | * |
| 56 | * if CONFIG_CONS_NONE is defined, then the serial console routines must |
| 57 | * defined elsewhere (for example, on the cogent platform, there are serial |
| 58 | * ports on the motherboard which are used for the serial console - see |
| 59 | * cogent/cma101/serial.[ch]). |
| 60 | */ |
| 61 | #undef CONFIG_CONS_ON_SMC /* define if console on SMC */ |
| 62 | #define CONFIG_CONS_ON_SCC /* define if console on SCC */ |
| 63 | #undef CONFIG_CONS_NONE /* define if console on something else */ |
| 64 | #define CONFIG_CONS_INDEX 1 /* which serial channel for console */ |
| 65 | |
| 66 | /* |
| 67 | * select ethernet configuration |
| 68 | * |
| 69 | * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then |
| 70 | * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3 |
| 71 | * for FCC) |
| 72 | * |
| 73 | * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be |
| 74 | * defined elsewhere (as for the console), or CFG_CMD_NET must be removed |
| 75 | * from CONFIG_COMMANDS to remove support for networking. |
| 76 | */ |
| 77 | #undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ |
| 78 | #define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ |
| 79 | #undef CONFIG_ETHER_NONE /* define if ether on something else */ |
wdenk | 48b4261 | 2003-06-19 23:01:32 +0000 | [diff] [blame] | 80 | |
| 81 | #ifdef CONFIG_ETHER_ON_FCC |
| 82 | |
| 83 | #define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */ |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 84 | |
| 85 | #if (CONFIG_ETHER_INDEX == 2) |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 86 | /* |
| 87 | * - Rx-CLK is CLK13 |
| 88 | * - Tx-CLK is CLK14 |
| 89 | * - Select bus for bd/buffers (see 28-13) |
wdenk | 48b4261 | 2003-06-19 23:01:32 +0000 | [diff] [blame] | 90 | * - Full duplex |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 91 | */ |
| 92 | # define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) |
| 93 | # define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) |
| 94 | # define CFG_CPMFCR_RAMTYPE 0 |
wdenk | 48b4261 | 2003-06-19 23:01:32 +0000 | [diff] [blame] | 95 | # define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 96 | |
| 97 | #endif /* CONFIG_ETHER_INDEX */ |
| 98 | |
wdenk | 48b4261 | 2003-06-19 23:01:32 +0000 | [diff] [blame] | 99 | #define CONFIG_MII /* MII PHY management */ |
| 100 | #define CONFIG_BITBANGMII /* bit-bang MII PHY management */ |
| 101 | /* |
| 102 | * GPIO pins used for bit-banged MII communications |
| 103 | */ |
| 104 | #define MDIO_PORT 2 /* Port C */ |
| 105 | #define MDIO_ACTIVE (iop->pdir |= 0x00400000) |
| 106 | #define MDIO_TRISTATE (iop->pdir &= ~0x00400000) |
| 107 | #define MDIO_READ ((iop->pdat & 0x00400000) != 0) |
| 108 | |
| 109 | #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \ |
| 110 | else iop->pdat &= ~0x00400000 |
| 111 | |
| 112 | #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \ |
| 113 | else iop->pdat &= ~0x00200000 |
| 114 | |
| 115 | #define MIIDELAY udelay(1) |
| 116 | |
| 117 | #endif /* CONFIG_ETHER_ON_FCC */ |
| 118 | |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 119 | /* other options */ |
| 120 | #define CONFIG_HARD_I2C 1 /* To enable I2C support */ |
| 121 | #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ |
| 122 | #define CFG_I2C_SLAVE 0x7F |
| 123 | |
wdenk | db2f721f | 2003-03-06 00:58:30 +0000 | [diff] [blame] | 124 | #if defined(CONFIG_SPD_EEPROM) && !defined(CONFIG_SPD_ADDR) |
| 125 | #define CONFIG_SPD_ADDR 0x50 |
| 126 | #endif |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 127 | |
wdenk | db2f721f | 2003-03-06 00:58:30 +0000 | [diff] [blame] | 128 | #ifndef CONFIG_SDRAM_PBI |
| 129 | #define CONFIG_SDRAM_PBI 1 /* By default, use page-based interleaving */ |
| 130 | #endif |
| 131 | |
| 132 | #ifndef CONFIG_8260_CLKIN |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 133 | #define CONFIG_8260_CLKIN 66666666 /* in Hz */ |
wdenk | db2f721f | 2003-03-06 00:58:30 +0000 | [diff] [blame] | 134 | #endif |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 135 | #define CONFIG_BAUDRATE 115200 |
| 136 | |
| 137 | #define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \ |
| 138 | CFG_CMD_BEDBUG | \ |
wdenk | 824a1eb | 2003-04-20 16:49:37 +0000 | [diff] [blame] | 139 | CFG_CMD_BMP | \ |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 140 | CFG_CMD_BSP | \ |
| 141 | CFG_CMD_DATE | \ |
| 142 | CFG_CMD_DOC | \ |
| 143 | CFG_CMD_DTT | \ |
| 144 | CFG_CMD_EEPROM | \ |
| 145 | CFG_CMD_ELF | \ |
| 146 | CFG_CMD_FDC | \ |
wdenk | 2262cfe | 2002-11-18 00:14:45 +0000 | [diff] [blame] | 147 | CFG_CMD_FDOS | \ |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 148 | CFG_CMD_HWFLOW | \ |
| 149 | CFG_CMD_IDE | \ |
| 150 | CFG_CMD_JFFS2 | \ |
| 151 | CFG_CMD_KGDB | \ |
wdenk | 71f9511 | 2003-06-15 22:40:42 +0000 | [diff] [blame] | 152 | CFG_CMD_MMC | \ |
wdenk | cceb871 | 2003-06-23 18:12:28 +0000 | [diff] [blame] | 153 | CFG_CMD_NAND | \ |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 154 | CFG_CMD_PCI | \ |
| 155 | CFG_CMD_PCMCIA | \ |
| 156 | CFG_CMD_SCSI | \ |
wdenk | 1d0350e | 2002-11-11 21:14:20 +0000 | [diff] [blame] | 157 | CFG_CMD_SPI | \ |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 158 | CFG_CMD_VFD | \ |
| 159 | CFG_CMD_USB ) ) |
| 160 | |
| 161 | /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ |
| 162 | #include <cmd_confdefs.h> |
| 163 | |
| 164 | |
| 165 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ |
| 166 | #define CONFIG_BOOTCOMMAND "bootm 100000" /* autoboot command */ |
| 167 | #define CONFIG_BOOTARGS "root=/dev/ram rw" |
| 168 | |
| 169 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
| 170 | #undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ |
| 171 | #define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ |
| 172 | #undef CONFIG_KGDB_NONE /* define if kgdb on something else */ |
| 173 | #define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */ |
| 174 | #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */ |
| 175 | #endif |
| 176 | |
| 177 | #undef CONFIG_WATCHDOG /* disable platform specific watchdog */ |
| 178 | |
| 179 | /* |
| 180 | * Miscellaneous configurable options |
| 181 | */ |
| 182 | #define CFG_LONGHELP /* undef to save memory */ |
| 183 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ |
| 184 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
| 185 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
| 186 | #else |
| 187 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ |
| 188 | #endif |
| 189 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ |
| 190 | #define CFG_MAXARGS 16 /* max number of command args */ |
| 191 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ |
| 192 | |
| 193 | #define CFG_MEMTEST_START 0x00100000 /* memtest works on */ |
| 194 | #define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ |
| 195 | |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 196 | #define CFG_LOAD_ADDR 0x100000 /* default load address */ |
| 197 | |
| 198 | #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ |
| 199 | |
| 200 | #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } |
| 201 | |
| 202 | #define CFG_FLASH_BASE 0xff800000 |
| 203 | #define FLASH_BASE 0xff800000 |
| 204 | #define CFG_MAX_FLASH_BANKS 1 /* max num of memory banks */ |
| 205 | #define CFG_MAX_FLASH_SECT 32 /* max num of sects on one chip */ |
| 206 | #define CFG_FLASH_SIZE 8 |
| 207 | #define CFG_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */ |
| 208 | #define CFG_FLASH_WRITE_TOUT 5 /* Timeout for Flash Write (in ms) */ |
wdenk | 8564acf | 2003-07-14 22:13:32 +0000 | [diff] [blame^] | 209 | #define CFG_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */ |
| 210 | #define CFG_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */ |
| 211 | #define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ |
| 212 | |
| 213 | #define CFG_JFFS2_FIRST_SECTOR 1 |
| 214 | #define CFG_JFFS2_LAST_SECTOR 27 |
| 215 | #define CFG_JFFS2_SORT_FRAGMENTS |
| 216 | #define CFG_JFFS_CUSTOM_PART |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 217 | |
| 218 | /* this is stuff came out of the Motorola docs */ |
| 219 | #define CFG_DEFAULT_IMMR 0x0F010000 |
| 220 | |
wdenk | 5d232d0 | 2003-05-22 22:52:13 +0000 | [diff] [blame] | 221 | #define CFG_IMMR 0xF0000000 |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 222 | #define CFG_BCSR 0x04500000 |
| 223 | #define CFG_SDRAM_BASE 0x00000000 |
| 224 | #define CFG_LSDRAM_BASE 0x04000000 |
| 225 | |
| 226 | #define RS232EN_1 0x02000002 |
| 227 | #define RS232EN_2 0x01000001 |
| 228 | #define FETHIEN 0x08000008 |
| 229 | #define FETH_RST 0x04000004 |
| 230 | |
| 231 | #define CFG_INIT_RAM_ADDR CFG_IMMR |
| 232 | #define CFG_INIT_RAM_END 0x4000 /* End of used area in DPRAM */ |
| 233 | #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ |
| 234 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
| 235 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET |
| 236 | |
| 237 | |
| 238 | /* 0x0EA28205 */ |
| 239 | #define CFG_HRCW_MASTER ( ( HRCW_BPS11 | HRCW_CIP ) |\ |
| 240 | ( HRCW_L2CPC10 | HRCW_DPPC10 | HRCW_ISB010 ) |\ |
| 241 | ( HRCW_BMS | HRCW_APPC10 ) |\ |
| 242 | ( HRCW_MODCK_H0101 ) \ |
| 243 | ) |
| 244 | |
| 245 | /* no slaves */ |
| 246 | #define CFG_HRCW_SLAVE1 0 |
| 247 | #define CFG_HRCW_SLAVE2 0 |
| 248 | #define CFG_HRCW_SLAVE3 0 |
| 249 | #define CFG_HRCW_SLAVE4 0 |
| 250 | #define CFG_HRCW_SLAVE5 0 |
| 251 | #define CFG_HRCW_SLAVE6 0 |
| 252 | #define CFG_HRCW_SLAVE7 0 |
| 253 | |
| 254 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ |
| 255 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ |
| 256 | |
| 257 | #define CFG_MONITOR_BASE TEXT_BASE |
| 258 | #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) |
| 259 | # define CFG_RAMBOOT |
| 260 | #endif |
| 261 | |
| 262 | #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
| 263 | #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ |
| 264 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
| 265 | |
| 266 | #ifndef CFG_RAMBOOT |
| 267 | # define CFG_ENV_IS_IN_FLASH 1 |
wdenk | 48b4261 | 2003-06-19 23:01:32 +0000 | [diff] [blame] | 268 | # define CFG_ENV_SECT_SIZE 0x40000 |
| 269 | # define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_ENV_SECT_SIZE) |
wdenk | e221174 | 2002-11-02 23:30:20 +0000 | [diff] [blame] | 270 | #else |
| 271 | # define CFG_ENV_IS_IN_NVRAM 1 |
| 272 | # define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) |
| 273 | # define CFG_ENV_SIZE 0x200 |
| 274 | #endif /* CFG_RAMBOOT */ |
| 275 | |
| 276 | |
| 277 | #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ |
| 278 | #if (CONFIG_COMMANDS & CFG_CMD_KGDB) |
| 279 | # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
| 280 | #endif |
| 281 | |
| 282 | |
| 283 | #define CFG_HID0_INIT 0 |
| 284 | #define CFG_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE ) |
| 285 | |
| 286 | #define CFG_HID2 0 |
| 287 | |
| 288 | #define CFG_SYPCR 0xFFFFFFC3 |
| 289 | #define CFG_BCR 0x100C0000 |
| 290 | #define CFG_SIUMCR 0x0A200000 |
| 291 | #define CFG_SCCR 0x00000000 |
| 292 | #define CFG_BR0_PRELIM 0xFF801801 |
| 293 | #define CFG_OR0_PRELIM 0xFF800836 |
| 294 | #define CFG_BR1_PRELIM 0x04501801 |
| 295 | #define CFG_OR1_PRELIM 0xFFFF8010 |
| 296 | |
| 297 | #define CFG_RMR 0 |
| 298 | #define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) |
| 299 | #define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) |
| 300 | #define CFG_RCCR 0 |
| 301 | #define CFG_PSDMR 0x016EB452 |
| 302 | #define CFG_MPTPR 0x00001900 |
| 303 | #define CFG_PSRT 0x00000021 |
| 304 | |
| 305 | #define CFG_RESET_ADDRESS 0x04400000 |
| 306 | |
| 307 | #endif /* __CONFIG_H */ |