blob: e7838dcd2a6e73e3c1af7318e78d72129f6c8c34 [file] [log] [blame]
Heiko Schochereaf8c982014-01-25 07:53:48 +01001/*
2 * (C) Copyright 2013
3 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
4 *
5 * Based on:
6 * Copyright (c) 2011 IDS GmbH, Germany
7 * ids8313.c - ids8313 board support.
8 *
9 * Sergej Stepanov <ste@ids.de>
10 * Based on board/freescale/mpc8313erdb/mpc8313erdb.c
11 *
12 * SPDX-License-Identifier: GPL-2.0+
13 */
14
15#include <common.h>
16#include <mpc83xx.h>
17#include <spi.h>
18#include <libfdt.h>
19
20DECLARE_GLOBAL_DATA_PTR;
21/** CPLD contains the info about:
22 * - board type: *pCpld & 0xF0
23 * - hw-revision: *pCpld & 0x0F
24 * - cpld-revision: *pCpld+1
25 */
26int checkboard(void)
27{
28 char *pcpld = (char *)CONFIG_SYS_CPLD_BASE;
29 u8 u8Vers = readb(pcpld);
30 u8 u8Revs = readb(pcpld + 1);
31
32 printf("Board: ");
33 switch (u8Vers & 0xF0) {
34 case '\x40':
35 printf("CU73X");
36 break;
37 case '\x50':
38 printf("CC73X");
39 break;
40 default:
41 printf("unknown(0x%02X, 0x%02X)\n", u8Vers, u8Revs);
42 return 0;
43 }
44 printf("\nInfo: HW-Rev: %i, CPLD-Rev: %i\n",
45 u8Vers & 0x0F, u8Revs & 0xFF);
46 return 0;
47}
48
49/*
50 * fixed sdram init
51 */
52int fixed_sdram(unsigned long config)
53{
54 immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
55 u32 msize = CONFIG_SYS_DDR_SIZE << 20;
56
57#ifndef CONFIG_SYS_RAMBOOT
58 u32 msize_log2 = __ilog2(msize);
59
60 out_be32(&im->sysconf.ddrlaw[0].bar,
61 (CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000));
62 out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1));
63 out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE);
64 sync();
65
66 /*
67 * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
68 * or the DDR2 controller may fail to initialize correctly.
69 */
70 udelay(50000);
71
72 out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24);
73 out_be32(&im->ddr.cs_config[0], config);
74
75 /* currently we use only one CS, so disable the other banks */
76 out_be32(&im->ddr.cs_config[1], 0);
77 out_be32(&im->ddr.cs_config[2], 0);
78 out_be32(&im->ddr.cs_config[3], 0);
79
80 out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
81 out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
82 out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
83 out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
84
85 out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_SDRAM_CFG);
86 out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_SDRAM_CFG2);
87
88 out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
89 out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE_2);
90
91 out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
92 out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CNTL);
93 sync();
94 udelay(300);
95
96 /* enable DDR controller */
97 setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
98 /* now check the real size */
99 disable_addr_trans();
100 msize = get_ram_size(CONFIG_SYS_DDR_BASE, msize);
101 enable_addr_trans();
102#endif
103 return msize;
104}
105
106static int setup_sdram(void)
107{
108 u32 msize = CONFIG_SYS_DDR_SIZE << 20;
109 long int size_01, size_02;
110
111 size_01 = fixed_sdram(CONFIG_SYS_DDR_CONFIG);
112 size_02 = fixed_sdram(CONFIG_SYS_DDR_CONFIG_256);
113
114 if (size_01 > size_02)
115 msize = fixed_sdram(CONFIG_SYS_DDR_CONFIG);
116 else
117 msize = size_02;
118
119 return msize;
120}
121
122phys_size_t initdram(int board_type)
123{
124 immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
125 fsl_lbc_t *lbc = &im->im_lbc;
126 u32 msize = 0;
127
128 if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
129 return -1;
130
131 msize = setup_sdram();
132
133 out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
134 out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR);
135 sync();
136
137 return msize;
138}
139
140#if defined(CONFIG_OF_BOARD_SETUP)
Simon Glasse895a4b2014-10-23 18:58:47 -0600141int ft_board_setup(void *blob, bd_t *bd)
Heiko Schochereaf8c982014-01-25 07:53:48 +0100142{
143 ft_cpu_setup(blob, bd);
Simon Glasse895a4b2014-10-23 18:58:47 -0600144
145 return 0;
Heiko Schochereaf8c982014-01-25 07:53:48 +0100146}
147#endif
148
149/* gpio mask for spi_cs */
150#define IDSCPLD_SPI_CS_MASK 0x00000001
151/* spi_cs multiplexed through cpld */
152#define IDSCPLD_SPI_CS_BASE (CONFIG_SYS_CPLD_BASE + 0xf)
153
154#if defined(CONFIG_MISC_INIT_R)
155/* srp umcr mask for rts */
156#define IDSUMCR_RTS_MASK 0x04
157int misc_init_r(void)
158{
159 /*srp*/
160 duart83xx_t *uart1 = &((immap_t *)CONFIG_SYS_IMMR)->duart[0];
161 duart83xx_t *uart2 = &((immap_t *)CONFIG_SYS_IMMR)->duart[1];
162
163 gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
164 u8 *spi_base = (u8 *)IDSCPLD_SPI_CS_BASE;
165
166 /* deactivate spi_cs channels */
167 out_8(spi_base, 0);
168 /* deactivate the spi_cs */
169 setbits_be32(&iopd->dir, IDSCPLD_SPI_CS_MASK);
170 /*srp - deactivate rts*/
171 out_8(&uart1->umcr, IDSUMCR_RTS_MASK);
172 out_8(&uart2->umcr, IDSUMCR_RTS_MASK);
173
174
175 gd->fdt_blob = (void *)CONFIG_SYS_FLASH_BASE;
176 return 0;
177}
178#endif
179
180#ifdef CONFIG_MPC8XXX_SPI
181/*
182 * The following are used to control the SPI chip selects
183 */
184int spi_cs_is_valid(unsigned int bus, unsigned int cs)
185{
186 return bus == 0 && ((cs >= 0) && (cs <= 2));
187}
188
189void spi_cs_activate(struct spi_slave *slave)
190{
191 gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
192 u8 *spi_base = (u8 *)IDSCPLD_SPI_CS_BASE;
193
194 /* select the spi_cs channel */
195 out_8(spi_base, 1 << slave->cs);
196 /* activate the spi_cs */
197 clrbits_be32(&iopd->dat, IDSCPLD_SPI_CS_MASK);
198}
199
200void spi_cs_deactivate(struct spi_slave *slave)
201{
202 gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
203 u8 *spi_base = (u8 *)IDSCPLD_SPI_CS_BASE;
204
205 /* select the spi_cs channel */
206 out_8(spi_base, 1 << slave->cs);
207 /* deactivate the spi_cs */
208 setbits_be32(&iopd->dat, IDSCPLD_SPI_CS_MASK);
209}
210#endif /* CONFIG_HARD_SPI */