| Siew Chin Lim | 8a3244d | 2021-03-01 20:04:15 +0800 | [diff] [blame] | 1 | CONFIG_ARM=y |
| 2 | CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds" |
| 3 | CONFIG_ARCH_SOCFPGA=y |
| 4 | CONFIG_SYS_TEXT_BASE=0x200000 |
| Tom Rini | 9802154 | 2021-11-01 12:19:22 +0000 | [diff] [blame] | 5 | CONFIG_SYS_MALLOC_LEN=0x500000 |
| Siew Chin Lim | 8a3244d | 2021-03-01 20:04:15 +0800 | [diff] [blame] | 6 | CONFIG_NR_DRAM_BANKS=2 |
| 7 | CONFIG_ENV_SIZE=0x1000 |
| 8 | CONFIG_ENV_OFFSET=0x200 |
| Siew Chin Lim | 8a3244d | 2021-03-01 20:04:15 +0800 | [diff] [blame] | 9 | CONFIG_DM_GPIO=y |
| Tom Rini | 2bba780 | 2021-06-28 10:17:29 -0400 | [diff] [blame] | 10 | CONFIG_DEFAULT_DEVICE_TREE="socfpga_agilex_socdk" |
| Siew Chin Lim | 8a3244d | 2021-03-01 20:04:15 +0800 | [diff] [blame] | 11 | CONFIG_SPL_TEXT_BASE=0xFFE00000 |
| 12 | CONFIG_SOCFPGA_SECURE_VAB_AUTH=y |
| 13 | CONFIG_TARGET_SOCFPGA_AGILEX_SOCDK=y |
| 14 | CONFIG_IDENT_STRING="socfpga_agilex" |
| 15 | CONFIG_SPL_FS_FAT=y |
| Tom Rini | 49c8ef0 | 2021-08-23 10:25:31 -0400 | [diff] [blame] | 16 | CONFIG_SYS_LOAD_ADDR=0x02000000 |
| Tom Rini | d46e86d | 2022-04-08 13:36:51 -0400 | [diff] [blame] | 17 | CONFIG_REMAKE_ELF=y |
| Siew Chin Lim | 8a3244d | 2021-03-01 20:04:15 +0800 | [diff] [blame] | 18 | CONFIG_FIT=y |
| Siew Chin Lim | cdca986 | 2021-03-24 23:56:37 +0800 | [diff] [blame] | 19 | CONFIG_SPL_FIT_SIGNATURE=y |
| Siew Chin Lim | 8a3244d | 2021-03-01 20:04:15 +0800 | [diff] [blame] | 20 | CONFIG_SPL_LOAD_FIT=y |
| 21 | CONFIG_SPL_LOAD_FIT_ADDRESS=0x02000000 |
| 22 | # CONFIG_USE_SPL_FIT_GENERATOR is not set |
| Siew Chin Lim | 8a3244d | 2021-03-01 20:04:15 +0800 | [diff] [blame] | 23 | CONFIG_BOOTDELAY=5 |
| 24 | CONFIG_USE_BOOTARGS=y |
| 25 | CONFIG_BOOTARGS="earlycon" |
| 26 | CONFIG_USE_BOOTCOMMAND=y |
| 27 | CONFIG_BOOTCOMMAND="run fatscript; run mmcfitload; run mmcfitboot" |
| Simon Glass | 1e52db6 | 2021-07-14 17:05:32 -0500 | [diff] [blame] | 28 | CONFIG_SPL_CRC32=y |
| Siew Chin Lim | 8a3244d | 2021-03-01 20:04:15 +0800 | [diff] [blame] | 29 | CONFIG_SPL_CACHE=y |
| 30 | CONFIG_SPL_SPI_LOAD=y |
| Tom Rini | 3e5b62f | 2021-08-10 15:08:46 -0400 | [diff] [blame] | 31 | CONFIG_SYS_SPI_U_BOOT_OFFS=0x02000000 |
| Siew Chin Lim | 8a3244d | 2021-03-01 20:04:15 +0800 | [diff] [blame] | 32 | CONFIG_SPL_ATF=y |
| 33 | CONFIG_SPL_ATF_NO_PLATFORM_PARAM=y |
| 34 | CONFIG_HUSH_PARSER=y |
| 35 | CONFIG_SYS_PROMPT="SOCFPGA_AGILEX # " |
| 36 | CONFIG_CMD_MEMTEST=y |
| 37 | CONFIG_CMD_GPIO=y |
| 38 | CONFIG_CMD_I2C=y |
| 39 | CONFIG_CMD_MMC=y |
| 40 | CONFIG_CMD_SPI=y |
| 41 | CONFIG_CMD_USB=y |
| 42 | CONFIG_CMD_DHCP=y |
| 43 | CONFIG_CMD_MII=y |
| 44 | CONFIG_CMD_PING=y |
| 45 | CONFIG_CMD_CACHE=y |
| 46 | CONFIG_CMD_EXT4=y |
| 47 | CONFIG_CMD_FAT=y |
| 48 | CONFIG_CMD_FS_GENERIC=y |
| 49 | CONFIG_ENV_IS_IN_MMC=y |
| Tom Rini | fdfb17b | 2022-02-25 11:19:48 -0500 | [diff] [blame] | 50 | CONFIG_USE_BOOTFILE=y |
| 51 | CONFIG_BOOTFILE="kernel.itb" |
| Siew Chin Lim | 8a3244d | 2021-03-01 20:04:15 +0800 | [diff] [blame] | 52 | CONFIG_NET_RANDOM_ETHADDR=y |
| 53 | CONFIG_SPL_DM_SEQ_ALIAS=y |
| 54 | CONFIG_SPL_ALTERA_SDRAM=y |
| 55 | CONFIG_DWAPB_GPIO=y |
| 56 | CONFIG_DM_I2C=y |
| 57 | CONFIG_SYS_I2C_DW=y |
| Siew Chin Lim | 8a3244d | 2021-03-01 20:04:15 +0800 | [diff] [blame] | 58 | CONFIG_MMC_DW=y |
| 59 | CONFIG_MTD=y |
| 60 | CONFIG_SF_DEFAULT_MODE=0x2003 |
| 61 | CONFIG_SPI_FLASH_SPANSION=y |
| 62 | CONFIG_SPI_FLASH_STMICRO=y |
| 63 | CONFIG_PHY_MICREL=y |
| 64 | CONFIG_PHY_MICREL_KSZ90X1=y |
| 65 | CONFIG_DM_ETH=y |
| 66 | CONFIG_ETH_DESIGNWARE=y |
| 67 | CONFIG_MII=y |
| 68 | CONFIG_DM_RESET=y |
| 69 | CONFIG_SPI=y |
| 70 | CONFIG_CADENCE_QSPI=y |
| 71 | CONFIG_DESIGNWARE_SPI=y |
| 72 | CONFIG_USB=y |
| Siew Chin Lim | 8a3244d | 2021-03-01 20:04:15 +0800 | [diff] [blame] | 73 | CONFIG_USB_DWC2=y |
| 74 | CONFIG_USB_STORAGE=y |
| 75 | CONFIG_DESIGNWARE_WATCHDOG=y |
| 76 | CONFIG_WDT=y |
| 77 | # CONFIG_SPL_USE_TINY_PRINTF is not set |
| 78 | CONFIG_PANIC_HANG=y |