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Stefan Roesed96f41e2005-11-30 13:06:40 +01001/*
2 * (C) Copyright 2005
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * Wolfgang Denk <wd@denx.de>
6 * Copyright 2004 Freescale Semiconductor.
7 * (C) Copyright 2002,2003 Motorola,Inc.
8 * Xianghua Xiao <X.Xiao@motorola.com>
9 *
10 * See file CREDITS for list of people who contributed to this
11 * project.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * MA 02111-1307 USA
27 */
28
29/*
30 * TQM85xx (8560/40/55/41) board configuration file
31 */
32
33#ifndef __CONFIG_H
34#define __CONFIG_H
35
36/* High Level Configuration Options */
37#define CONFIG_BOOKE 1 /* BOOKE */
38#define CONFIG_E500 1 /* BOOKE e500 family */
39#define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */
40
41#define CONFIG_PCI
42#define CONFIG_TSEC_ENET /* tsec ethernet support */
43
44#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
45
46/*
47 * Only MPC8540 doesn't have CPM module
48 */
49#ifndef CONFIG_MPC8540
50#define CONFIG_CPM2 1 /* has CPM2 */
51#endif
52
53/*
54 * sysclk for MPC85xx
55 *
56 * Two valid values are:
57 * 33000000
58 * 66000000
59 *
60 * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
61 * is likely the desired value here, so that is now the default.
62 * The board, however, can run at 66MHz. In any event, this value
63 * must match the settings of some switches. Details can be found
64 * in the README.mpc85xxads.
65 */
66
67#ifndef CONFIG_SYS_CLK_FREQ
68#define CONFIG_SYS_CLK_FREQ 33333333
69#endif
70
71/*
72 * These can be toggled for performance analysis, otherwise use default.
73 */
74#define CONFIG_L2_CACHE /* toggle L2 cache */
75#define CONFIG_BTB /* toggle branch predition */
76#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
77
78#define CFG_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */
79
80#undef CFG_DRAM_TEST /* memory test, takes time */
81#define CFG_MEMTEST_START 0x00000000
82#define CFG_MEMTEST_END 0x10000000
83
84/*
85 * Base addresses -- Note these are effective addresses where the
86 * actual resources get mapped (not physical addresses)
87 */
88#define CFG_CCSRBAR_DEFAULT 0xFF700000 /* CCSRBAR Default */
89#define CFG_CCSRBAR 0xE0000000 /* relocated CCSRBAR */
90#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
91
92/*
93 * DDR Setup
94 */
95#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */
96#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
97#define CONFIG_ADD_RAM_INFO 1 /* print additional info*/
98
99#if defined(CONFIG_TQM8540) || defined(CONFIG_TQM8560)
100/* TQM8540 & 8560 need DLL-override */
101#define CONFIG_DDR_DLL /* DLL fix needed */
102#define CONFIG_DDR_DEFAULT_CL 25 /* CAS latency 2,5 */
103#endif /* defined(CONFIG_TQM8540) || defined(CONFIG_TQM8560) */
104
105#if defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555)
106#define CONFIG_DDR_DEFAULT_CL 30 /* CAS latency 3 */
107#endif /* defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555) */
108
109/*
110 * Flash on the Local Bus
111 */
112#define CFG_FLASH0 0xFC000000
113#define CFG_FLASH1 0xF8000000
114#define CFG_FLASH_BANKS_LIST { CFG_FLASH1, CFG_FLASH0 }
115
116#define CFG_LBC_FLASH_BASE CFG_FLASH1 /* Localbus flash start */
117#define CFG_FLASH_BASE CFG_LBC_FLASH_BASE /* start of FLASH */
118
119#define CFG_BR0_PRELIM 0xfc001801 /* port size 32bit */
120#define CFG_OR0_PRELIM 0xfc000040 /* 64MB Flash */
121#define CFG_BR1_PRELIM 0xf8001801 /* port size 32bit */
122#define CFG_OR1_PRELIM 0xfc000040 /* 64MB Flash */
123
124#define CFG_FLASH_CFI /* flash is CFI compat. */
125#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver*/
126#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector */
127#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash*/
128
129#define CFG_MAX_FLASH_BANKS 2 /* number of banks */
130#define CFG_MAX_FLASH_SECT 512 /* sectors per device */
131#undef CFG_FLASH_CHECKSUM
132#define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
133#define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
134
135#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
136
137#define CFG_LBC_LCRR 0x00030008 /* LB clock ratio reg */
138#define CFG_LBC_LBCR 0x00000000 /* LB config reg */
139#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
140#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/
141
142#define CONFIG_L1_INIT_RAM
143#define CFG_INIT_RAM_LOCK 1
144#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
145#define CFG_INIT_RAM_END 0x4000 /* End used area in RAM */
146
147#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data*/
148#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
149#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
150
151#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256kB for Mon*/
152#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
153
154/* Serial Port */
155#if defined(CONFIG_TQM8560)
156
157#define CONFIG_CONS_ON_SCC /* define if console on SCC */
158#undef CONFIG_CONS_NONE /* define if console on something else */
159#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
160
Wolfgang Denk966083e2006-07-21 15:24:56 +0200161#else /* ! TQM8560 */
Stefan Roesed96f41e2005-11-30 13:06:40 +0100162
163#define CONFIG_CONS_INDEX 1
164#undef CONFIG_SERIAL_SOFTWARE_FIFO
165#define CFG_NS16550
166#define CFG_NS16550_SERIAL
167#define CFG_NS16550_REG_SIZE 1
168#define CFG_NS16550_CLK get_bus_freq(0)
169
170#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
171#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
172
Wolfgang Denkbc8bb6d2006-06-16 16:40:54 +0200173/* PS/2 Keyboard */
Wolfgang Denkbd3143f2006-07-19 14:49:35 +0200174#if !defined(CONFIG_TQM8560)
Wolfgang Denkbc8bb6d2006-06-16 16:40:54 +0200175#define CONFIG_PS2KBD /* AT-PS/2 Keyboard */
176#define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */
177#define CONFIG_PS2SERIAL 2 /* .. on DUART2 */
178#define CONFIG_PS2MULT_DELAY (CFG_HZ/2) /* Initial delay */
179#define CONFIG_BOARD_EARLY_INIT_R 1
Wolfgang Denkbd3143f2006-07-19 14:49:35 +0200180#endif /* !CONFIG_TQM8560 */
Wolfgang Denkbc8bb6d2006-06-16 16:40:54 +0200181
Wolfgang Denk966083e2006-07-21 15:24:56 +0200182#endif /* CONFIG_TQM8560 */
183
184#define CONFIG_BAUDRATE 115200
185
186#define CFG_BAUDRATE_TABLE \
187 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
188
Wolfgang Denk2751a952006-10-28 02:29:14 +0200189#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
190#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */
Stefan Roesed96f41e2005-11-30 13:06:40 +0100191#ifdef CFG_HUSH_PARSER
Wolfgang Denk2751a952006-10-28 02:29:14 +0200192#define CFG_PROMPT_HUSH_PS2 "> "
Stefan Roesed96f41e2005-11-30 13:06:40 +0100193#endif
194
Jon Loeliger20476722006-10-20 15:50:15 -0500195
196/*
197 * I2C
198 */
199#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
Stefan Roesed96f41e2005-11-30 13:06:40 +0100200#define CONFIG_HARD_I2C /* I2C with hardware support */
201#undef CONFIG_SOFT_I2C /* I2C bit-banged */
202#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
203#define CFG_I2C_SLAVE 0x7F
204#define CFG_I2C_NOPROBES {0x48} /* Don't probe these addrs */
Jon Loeliger20476722006-10-20 15:50:15 -0500205#define CFG_I2C_OFFSET 0x3000
Stefan Roesed96f41e2005-11-30 13:06:40 +0100206
207/* I2C RTC */
208#define CONFIG_RTC_DS1337 /* Use ds1337 rtc via i2c */
209#define CFG_I2C_RTC_ADDR 0x68 /* at address 0x68 */
210
211/* I2C EEPROM */
212/*
213 * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work also).
214 */
215#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */
216#define CFG_I2C_EEPROM_ADDR_LEN 2
217#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
218#define CFG_EEPROM_PAGE_WRITE_ENABLE
219#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
220#define CFG_I2C_MULTI_EEPROMS 1 /* more than one eeprom */
221
222/* I2C SYSMON (LM75) */
223#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
224#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
225#define CFG_DTT_MAX_TEMP 70
226#define CFG_DTT_LOW_TEMP -30
227#define CFG_DTT_HYSTERESIS 3
228
229/* RapidIO MMU */
230#define CFG_RIO_MEM_BASE 0xc0000000 /* base address */
231#define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE
232#define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */
233
234/*
235 * General PCI
236 * Addresses are mapped 1-1.
237 */
238#define CFG_PCI1_MEM_BASE 0x80000000
239#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
240#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
241#define CFG_PCI1_IO_BASE 0xe2000000
242#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE
243#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */
244
245#if defined(CONFIG_PCI)
246
247#define CONFIG_PCI_PNP /* do pci plug-and-play */
248
249#define CONFIG_EEPRO100
250#undef CONFIG_TULIP
251
252#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
253#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
254
255#endif /* CONFIG_PCI */
256
257
258#define CONFIG_NET_MULTI 1
259
260#define CONFIG_MII 1 /* MII PHY management */
Kim Phillips255a35772007-05-16 16:52:19 -0500261#define CONFIG_TSEC1 1
262#define CONFIG_TSEC1_NAME "TSEC0"
263#define CONFIG_TSEC2 1
264#define CONFIG_TSEC2_NAME "TSEC1"
Stefan Roesed96f41e2005-11-30 13:06:40 +0100265#define TSEC1_PHY_ADDR 2
266#define TSEC2_PHY_ADDR 1
267#define TSEC1_PHYIDX 0
268#define TSEC2_PHYIDX 0
269#define FEC_PHY_ADDR 3
270#define FEC_PHYIDX 0
271#define CONFIG_HAS_ETH1
272#define CONFIG_HAS_ETH2
273
274/* Options are TSEC[0-1], FEC */
275#define CONFIG_ETHPRIME "TSEC0"
276
277#if defined(CONFIG_TQM8540)
278/*
279 * TQM8540 has 3 ethernet ports. 2 TSEC's and one FEC.
280 * The FEC port is connected on the same signals as the FCC3 port
281 * of the TQM8560 to the baseboard (STK85xx Starterkit).
282 *
283 * On the STK85xx Starterkit the X47/X50 jumper has to be set to
284 * a - d (X50.2 - 3) to enable the FEC port.
285 */
286#define CONFIG_MPC85XX_FEC 1
287#define CONFIG_MPC85XX_FEC_NAME "FEC"
288#endif
289
290#if defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555)
291/*
292 * TQM8541/55 have 4 ethernet ports. 2 TSEC's and 2 FCC's. Only one FCC port
293 * can be used at once, since only one FCC port is available on the STK85xx
294 * Starterkit.
295 *
296 * To use this port you have to configure U-Boot to use the FCC port 1...2
297 * and set the X47/X50 jumper to:
298 * FCC1: a - b (X47.2 - X50.2)
299 * FCC2: a - c (X50.2 - 1)
300 */
301#define CONFIG_ETHER_ON_FCC
302#define CONFIG_ETHER_INDEX 1 /* FCC channel for ethernet */
303#endif
304
305#if defined(CONFIG_TQM8560)
306/*
307 * TQM8560 has 5 ethernet ports. 2 TSEC's and 3 FCC's. Only one FCC port
308 * can be used at once, since only one FCC port is available on the STK85xx
309 * Starterkit.
310 *
311 * To use this port you have to configure U-Boot to use the FCC port 1...3
312 * and set the X47/X50 jumper to:
313 * FCC1: a - b (X47.2 - X50.2)
314 * FCC2: a - c (X50.2 - 1)
315 * FCC3: a - d (X50.2 - 3)
316 */
317#define CONFIG_ETHER_ON_FCC
318#define CONFIG_ETHER_INDEX 3 /* FCC channel for ethernet */
319#endif
320
321#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1)
322#define CONFIG_ETHER_ON_FCC1
323#define CFG_CMXFCR_MASK1 (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK)
324#define CFG_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK12)
325#define CFG_CPMFCR_RAMTYPE 0
326#define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
327#endif
328
329#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
330#define CONFIG_ETHER_ON_FCC2
331#define CFG_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
332#define CFG_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK16 | CMXFCR_TF2CS_CLK13)
333#define CFG_CPMFCR_RAMTYPE 0
334#define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
335#endif
336
337#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3)
338#define CONFIG_ETHER_ON_FCC3
339#define CFG_CMXFCR_MASK3 (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK)
340#define CFG_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15 | CMXFCR_TF3CS_CLK14)
341#define CFG_CPMFCR_RAMTYPE 0
342#define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB)
343#endif
344
345/*
346 * Environment
347 */
348#define CFG_ENV_IS_IN_FLASH 1
349#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x20000)
350#define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */
351#define CFG_ENV_SIZE 0x2000
352#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
353#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
354
355#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
356#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
357
358#define CONFIG_TIMESTAMP /* Print image info with ts */
359
Jon Loeliger2835e512007-06-13 13:22:08 -0500360
361/*
Jon Loeligera1aa0bb2007-07-10 09:22:23 -0500362 * BOOTP options
363 */
364#define CONFIG_BOOTP_BOOTFILESIZE
365#define CONFIG_BOOTP_BOOTPATH
366#define CONFIG_BOOTP_GATEWAY
367#define CONFIG_BOOTP_HOSTNAME
368
369
370/*
Jon Loeliger2835e512007-06-13 13:22:08 -0500371 * Command line configuration.
372 */
373#include <config_cmd_default.h>
374
375#define CONFIG_CMD_PING
376#define CONFIG_CMD_I2C
377#define CONFIG_CMD_DHCP
378#define CONFIG_CMD_NFS
379#define CONFIG_CMD_SNTP
380#define CONFIG_CMD_DATE
381#define CONFIG_CMD_EEPROM
382#define CONFIG_CMD_DTT
383#define CONFIG_CMD_MII
384
Stefan Roesed96f41e2005-11-30 13:06:40 +0100385#if defined(CONFIG_PCI)
Jon Loeliger2835e512007-06-13 13:22:08 -0500386 #define CONFIG_CMD_PCI
Stefan Roesed96f41e2005-11-30 13:06:40 +0100387#endif
388
Stefan Roesed96f41e2005-11-30 13:06:40 +0100389
390#undef CONFIG_WATCHDOG /* watchdog disabled */
391
392/*
393 * Miscellaneous configurable options
394 */
395#define CFG_LONGHELP /* undef to save memory */
396#define CFG_LOAD_ADDR 0x2000000 /* default load address */
397#define CFG_PROMPT "=> " /* Monitor Command Prompt */
398
Jon Loeliger2835e512007-06-13 13:22:08 -0500399#if defined(CONFIG_CMD_KGDB)
Stefan Roesed96f41e2005-11-30 13:06:40 +0100400 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
401#else
402 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
403#endif
404
405#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buf Size */
406#define CFG_MAXARGS 16 /* max number of command args */
407#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
408#define CFG_HZ 1000 /* decrementer freq: 1ms ticks */
409
410/*
411 * For booting Linux, the board info and command line data
412 * have to be in the first 8 MB of memory, since this is
413 * the maximum mapped by the Linux kernel during initialization.
414 */
415#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
416
417/* Cache Configuration */
418#define CFG_DCACHE_SIZE 32768
419#define CFG_CACHELINE_SIZE 32
Jon Loeliger2835e512007-06-13 13:22:08 -0500420#if defined(CONFIG_CMD_KGDB)
Stefan Roesed96f41e2005-11-30 13:06:40 +0100421#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value */
422#endif
423
424/*
425 * Internal Definitions
426 *
427 * Boot Flags
428 */
429#define BOOTFLAG_COLD 0x01 /* Power-On: Boot from FLASH */
430#define BOOTFLAG_WARM 0x02 /* Software reboot */
431
Jon Loeliger2835e512007-06-13 13:22:08 -0500432#if defined(CONFIG_CMD_KGDB)
Stefan Roesed96f41e2005-11-30 13:06:40 +0100433#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port*/
434#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
435#endif
436
437
438#define CONFIG_LOADADDR 200000 /* default addr for tftp & bootm*/
439
440#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */
441
442#define CONFIG_PREBOOT "echo;" \
Wolfgang Denkd8519dc2006-08-11 17:33:42 +0200443 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
Stefan Roesed96f41e2005-11-30 13:06:40 +0100444 "echo"
445
446#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
447
448#define CONFIG_EXTRA_ENV_SETTINGS \
449 CFG_BOOTFILE \
450 "netdev=eth0\0" \
451 "consdev=ttyS0\0" \
452 "nfsargs=setenv bootargs root=/dev/nfs rw " \
453 "nfsroot=$serverip:$rootpath\0" \
454 "ramargs=setenv bootargs root=/dev/ram rw\0" \
455 "addip=setenv bootargs $bootargs " \
456 "ip=$ipaddr:$serverip:$gatewayip:$netmask" \
457 ":$hostname:$netdev:off panic=1\0" \
458 "addcons=setenv bootargs $bootargs " \
459 "console=$consdev,$baudrate\0" \
460 "flash_nfs=run nfsargs addip addcons;" \
461 "bootm $kernel_addr\0" \
462 "flash_self=run ramargs addip addcons;" \
463 "bootm $kernel_addr $ramdisk_addr\0" \
464 "net_nfs=tftp $loadaddr $bootfile;" \
465 "run nfsargs addip addcons;bootm\0" \
466 "rootpath=/opt/eldk/ppc_85xx\0" \
467 "kernel_addr=FE000000\0" \
Wolfgang Denk015c2002006-08-11 17:29:38 +0200468 "ramdisk_addr=FE180000\0" \
Stefan Roesed96f41e2005-11-30 13:06:40 +0100469 "load=tftp 100000 /tftpboot/$hostname/u-boot.bin\0" \
470 "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
471 "cp.b 100000 fffc0000 40000;" \
472 "setenv filesize;saveenv\0" \
473 "upd=run load;run update\0" \
474 ""
475#define CONFIG_BOOTCOMMAND "run flash_self"
476
477#endif /* __CONFIG_H */