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wdenkdc7c9a12003-03-26 06:55:25 +00001/*
2 * (C) Copyright 2000, 2001, 2002
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific,
26 * for SinoVee Microsystems SC8xx series SBC
27 * http://www.fel.com.cn (Chinese)
28 * http://www.sinovee.com (English)
29 */
30
31#ifndef __CONFIG_H
32#define __CONFIG_H
33
34/* Custom configuration */
35/* SC823,SC850,SC860SAR, FEL8xx-AT(823/850/860) */
36/* SC85T,SC860T, FEL8xx-AT(855T/860T) */
37/*#define CONFIG_FEL8xx_AT */
38/*#define CONFIG_LCD */
39/* if core > 50MHz , un-comment CONFIG_BUS_DIV2 */
40/* #define CONFIG_50MHz */
41/* #define CONFIG_66MHz */
42/* #define CONFIG_75MHz */
43#define CONFIG_80MHz
44/*#define CONFIG_100MHz */
45/* #define CONFIG_BUS_DIV2 1 */
46/* for BOOT device port size */
47/* #define CONFIG_BOOT_8B */
48#define CONFIG_BOOT_16B
49/* #define CONFIG_BOOT_32B */
50/* #define CONFIG_CAN_DRIVER */
51/* #define DEBUG */
52#define CONFIG_FEC_ENET
53
54/* #define CONFIG_SDRAM_16M */
55#define CONFIG_SDRAM_32M
56/* #define CONFIG_SDRAM_64M */
57#define CFG_RESET_ADDRESS 0xffffffff
58/*
59 * High Level Configuration Options
60 * (easy to change)
61 */
62
63/* #define CONFIG_MPC823 1 */
64/* #define CONFIG_MPC850 1 */
65#define CONFIG_MPC855 1
66/* #define CONFIG_MPC860 1 */
67/* #define CONFIG_MPC860T 1 */
68
69#undef CONFIG_WATCHDOG /* watchdog */
70
71#define CONFIG_SVM_SC8xx 1 /* ...on SVM SC8xx series */
72
73#ifdef CONFIG_LCD /* with LCD controller ? */
wdenkfd3103b2003-11-25 16:55:19 +000074/* #define CONFIG_NEC_NL6448BC20 1 / * use NEC NL6448BC20 display */
wdenkdc7c9a12003-03-26 06:55:25 +000075#endif
76
77#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
78#undef CONFIG_8xx_CONS_SMC2
79#undef CONFIG_8xx_CONS_NONE
80#define CONFIG_BAUDRATE 19200 /* console baudrate = 115kbps */
81#if 0
82#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
83#else
84#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
85#endif
86
87#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
88
89#define CONFIG_BOARD_TYPES 1 /* support board types */
90
91#define CONFIG_PREBOOT "echo;echo Welcome to U-Boot SVM port;echo;echo Type \"? or help\" to get on-line help;echo"
92
93#undef CONFIG_BOOTARGS
94#define CONFIG_EXTRA_ENV_SETTINGS \
wdenk8bde7f72003-06-27 21:31:46 +000095 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010096 "nfsroot=${serverip}:${rootpath}\0" \
wdenk8bde7f72003-06-27 21:31:46 +000097 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010098 "addip=setenv bootargs ${bootargs} " \
99 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
100 ":${hostname}:${netdev}:off panic=1\0" \
wdenk8bde7f72003-06-27 21:31:46 +0000101 "flash_nfs=run nfsargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100102 "bootm ${kernel_addr}\0" \
wdenk8bde7f72003-06-27 21:31:46 +0000103 "flash_self=run ramargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100104 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
105 "net_nfs=tftp 0x210000 ${bootfile};run nfsargs addip;bootm\0" \
wdenk8bde7f72003-06-27 21:31:46 +0000106 "rootpath=/opt/sinovee/ppc8xx-linux-2.0/target\0" \
107 "bootfile=pImage-sc855t\0" \
108 "kernel_addr=48000000\0" \
109 "ramdisk_addr=48100000\0" \
110 ""
wdenkdc7c9a12003-03-26 06:55:25 +0000111#define CONFIG_BOOTCOMMAND \
Wolfgang Denkfe126d82005-11-20 21:40:11 +0100112 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
113 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
wdenkdc7c9a12003-03-26 06:55:25 +0000114 "tftpboot 0x210000 pImage-sc855t;bootm 0x210000"
115
116#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
117#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */
118
119
120#ifdef CONFIG_LCD
121# undef CONFIG_STATUS_LED /* disturbs display */
122#else
123# define CONFIG_STATUS_LED 1 /* Status LED enabled */
124#endif /* CONFIG_LCD */
125
126#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
127
Jon Loeligerd3b8c1a2007-07-09 21:57:31 -0500128/*
129 * BOOTP options
130 */
131#define CONFIG_BOOTP_SUBNETMASK
132#define CONFIG_BOOTP_GATEWAY
133#define CONFIG_BOOTP_HOSTNAME
134#define CONFIG_BOOTP_BOOTPATH
135#define CONFIG_BOOTP_BOOTFILESIZE
wdenkdc7c9a12003-03-26 06:55:25 +0000136
137#define CONFIG_MAC_PARTITION
138#define CONFIG_DOS_PARTITION
139
140#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
141
wdenkdc7c9a12003-03-26 06:55:25 +0000142
Jon Loeliger46da1e92007-07-04 22:33:30 -0500143/*
144 * Command line configuration.
145 */
146#include <config_cmd_default.h>
147
148#define CONFIG_CMD_ASKENV
149#define CONFIG_CMD_DHCP
150#define CONFIG_CMD_DOC
151#define CONFIG_CMD_DATE
152
153
Bartlomiej Siekaaddb2e12006-03-05 18:57:33 +0100154#define CFG_NAND_LEGACY
wdenkdc7c9a12003-03-26 06:55:25 +0000155
156/*
157 * Miscellaneous configurable options
158 */
159#define CFG_LONGHELP /* undef to save memory */
160#define CFG_PROMPT "=> " /* Monitor Command Prompt */
161
162#ifdef CFG_HUSH_PARSER
163#define CFG_PROMPT_HUSH_PS2 "> "
164#endif
165
Jon Loeliger46da1e92007-07-04 22:33:30 -0500166#if defined(CONFIG_CMD_KGDB)
wdenkdc7c9a12003-03-26 06:55:25 +0000167#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
168#else
169#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
170#endif
171#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
172#define CFG_MAXARGS 16 /* max number of command args */
173#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
174
175#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
176#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
177
178#define CFG_LOAD_ADDR 0x100000 /* default load address */
179
180#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
181
182#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
183
184/*
185 * Low Level Configuration Settings
186 * (address mappings, register initial values, etc.)
187 * You should know what you are doing if you make changes here.
188 */
189/*-----------------------------------------------------------------------
190 * Internal Memory Mapped Register
191 */
192#define CFG_IMMR 0xFF000000
193
194/*-----------------------------------------------------------------------
195 * Definitions for initial stack pointer and data area (in DPRAM)
196 */
197#define CFG_INIT_RAM_ADDR CFG_IMMR
198#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
199#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
200#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
201#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
202
203/*-----------------------------------------------------------------------
204 * Start addresses for the final memory configuration
205 * (Set up by the startup code)
206 * Please note that CFG_SDRAM_BASE _must_ start at 0
207 */
208#define CFG_SDRAM_BASE 0x00000000
209#define CFG_FLASH_BASE 0x40000000
210#define CFG_MONITOR_LEN (384 << 10) /* Reserve 192 kB for Monitor */
211#define CFG_MONITOR_BASE CFG_FLASH_BASE
212#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
213
214/*
215 * For booting Linux, the board info and command line data
216 * have to be in the first 8 MB of memory, since this is
217 * the maximum mapped by the Linux kernel during initialization.
218 */
219#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
220
221/*-----------------------------------------------------------------------
222 * FLASH organization
223 */
224#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
225#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
226
227#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
228#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
229
230#define CFG_ENV_IS_IN_FLASH 1
231
232#ifdef CONFIG_BOOT_8B
233#define CFG_ENV_OFFSET 0x10000 /* Offset of Environment Sector */
234#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
235#elif defined (CONFIG_BOOT_16B)
236#define CFG_ENV_OFFSET 0x10000 /* Offset of Environment Sector */
237#define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
238#elif defined (CONFIG_BOOT_32B)
239#define CFG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
240#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
241#endif
242
243/* Address and size of Redundant Environment Sector */
244#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SIZE)
245#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
246
247
248/*-----------------------------------------------------------------------
249 * Hardware Information Block
250 */
251#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
252#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */
253#define CFG_HWINFO_MAGIC 0x46454C38 /* 'SVM8' */
254
255/*-----------------------------------------------------------------------
256 * Cache Configuration
257 */
258#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeliger46da1e92007-07-04 22:33:30 -0500259#if defined(CONFIG_CMD_KGDB)
wdenkdc7c9a12003-03-26 06:55:25 +0000260#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */
261#endif
262
263/*-----------------------------------------------------------------------
264 * SYPCR - System Protection Control 11-9
265 * SYPCR can only be written once after reset!
266 *-----------------------------------------------------------------------
267 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
268 */
269#if defined(CONFIG_WATCHDOG)
270/*#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
271 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
272*/
273#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_SWF | \
274 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
275#else
276#define CFG_SYPCR 0xffffff88
277#endif
278
279/*-----------------------------------------------------------------------
280 * SIUMCR - SIU Module Configuration 11-6
281 *-----------------------------------------------------------------------
282 * PCMCIA config., multi-function pin tri-state
283 */
284#ifndef CONFIG_CAN_DRIVER
285/*#define CFG_SIUMCR 0x00610c00 */
wdenk8bde7f72003-06-27 21:31:46 +0000286#define CFG_SIUMCR 0x00000000
wdenkdc7c9a12003-03-26 06:55:25 +0000287#else /* we must activate GPL5 in the SIUMCR for CAN */
288#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
289#endif /* CONFIG_CAN_DRIVER */
290
291/*-----------------------------------------------------------------------
292 * TBSCR - Time Base Status and Control 11-26
293 *-----------------------------------------------------------------------
294 * Clear Reference Interrupt Status, Timebase freezing enabled
295 */
296#define CFG_TBSCR 0x0001
297
298/*-----------------------------------------------------------------------
299 * RTCSC - Real-Time Clock Status and Control Register 11-27
300 *-----------------------------------------------------------------------
301 */
302#define CFG_RTCSC 0x00c3
303
304/*-----------------------------------------------------------------------
305 * PISCR - Periodic Interrupt Status and Control 11-31
306 *-----------------------------------------------------------------------
307 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
308 */
309#define CFG_PISCR 0x0000
310
311/*-----------------------------------------------------------------------
312 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
313 *-----------------------------------------------------------------------
314 * Reset PLL lock status sticky bit, timer expired status bit and timer
315 * interrupt status bit
316 */
317#if defined (CONFIG_100MHz)
318#define CFG_PLPRCR 0x06301000
319#define CONFIG_8xx_GCLK_FREQ 100000000
320#elif defined (CONFIG_80MHz)
321#define CFG_PLPRCR 0x04f01000
322#define CONFIG_8xx_GCLK_FREQ 80000000
wdenk8bde7f72003-06-27 21:31:46 +0000323#elif defined(CONFIG_75MHz)
324#define CFG_PLPRCR 0x04a00100
wdenkdc7c9a12003-03-26 06:55:25 +0000325#define CONFIG_8xx_GCLK_FREQ 75000000
wdenk8bde7f72003-06-27 21:31:46 +0000326#elif defined(CONFIG_66MHz)
327#define CFG_PLPRCR 0x04101000
wdenkdc7c9a12003-03-26 06:55:25 +0000328#define CONFIG_8xx_GCLK_FREQ 66000000
wdenk8bde7f72003-06-27 21:31:46 +0000329#elif defined(CONFIG_50MHz)
330#define CFG_PLPRCR 0x03101000
wdenkdc7c9a12003-03-26 06:55:25 +0000331#define CONFIG_8xx_GCLK_FREQ 50000000
wdenk8bde7f72003-06-27 21:31:46 +0000332#endif
wdenkdc7c9a12003-03-26 06:55:25 +0000333
334/*-----------------------------------------------------------------------
335 * SCCR - System Clock and reset Control Register 15-27
336 *-----------------------------------------------------------------------
337 * Set clock output, timebase and RTC source and divider,
338 * power management and some other internal clocks
339 */
340#define SCCR_MASK SCCR_EBDF11
wdenk8bde7f72003-06-27 21:31:46 +0000341#ifdef CONFIG_BUS_DIV2
wdenkdc7c9a12003-03-26 06:55:25 +0000342#define CFG_SCCR 0x02020000 | SCCR_RTSEL
343#else /* up to 50 MHz we use a 1:1 clock */
344#define CFG_SCCR 0x02000000 | SCCR_RTSEL
wdenk8bde7f72003-06-27 21:31:46 +0000345#endif
wdenkdc7c9a12003-03-26 06:55:25 +0000346
347/*-----------------------------------------------------------------------
348 * PCMCIA stuff
349 *-----------------------------------------------------------------------
350 *
351 */
352#define CFG_PCMCIA_MEM_ADDR (0xE0000000)
353#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 )
354#define CFG_PCMCIA_DMA_ADDR (0xE4000000)
355#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 )
356#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000)
357#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 )
358#define CFG_PCMCIA_IO_ADDR (0xEC000000)
359#define CFG_PCMCIA_IO_SIZE ( 64 << 20 )
360
361/*-----------------------------------------------------------------------
362 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
363 *-----------------------------------------------------------------------
364 */
365
366#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
367
368#define CONFIG_IDE_8xx_DIRECT 1 /* Direct IDE not supported */
369#undef CONFIG_IDE_LED /* LED for ide not supported */
370#undef CONFIG_IDE_RESET /* reset for ide not supported */
371
372#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
373#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
374
375#define CFG_ATA_BASE_ADDR 0xFE100010
376#define CFG_ATA_IDE0_OFFSET 0x0000
377/*#define CFG_ATA_IDE1_OFFSET 0x0C00 */
378#define CFG_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O
379 */
380#define CFG_ATA_REG_OFFSET 0x0200 /* Offset for normal register accesses
381 */
382#define CFG_ATA_ALT_OFFSET 0x0210 /* Offset for alternate registers
383 */
wdenk8bde7f72003-06-27 21:31:46 +0000384#define CONFIG_ATAPI
wdenkdc7c9a12003-03-26 06:55:25 +0000385#define CFG_PIO_MODE 0
386
387/*-----------------------------------------------------------------------
388 *
389 *-----------------------------------------------------------------------
390 *
391 */
392/*#define CFG_DER 0x2002000F*/
393#define CFG_DER 0x0
394
395/*
396 * Init Memory Controller:
397 *
398 * BR0/1 and OR0/1 (FLASH)
399 */
400
401#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
402#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
403
404/* used to re-map FLASH both when starting from SRAM or FLASH:
405 * restrict access enough to keep SRAM working (if any)
406 * but not too much to meddle with FLASH accesses
407 */
408#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */
409#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
410
411/*
412 * FLASH timing:
413 */
wdenk8bde7f72003-06-27 21:31:46 +0000414#if defined(CONFIG_100MHz)
415#define CFG_OR_TIMING_FLASH 0x000002f4
416#define CFG_OR_TIMING_DOC 0x000002f4
wdenkdc7c9a12003-03-26 06:55:25 +0000417#define CFG_MxMR_PTx 0x61000000
418#define CFG_MPTPR 0x400
419
420#elif defined(CONFIG_80MHz)
wdenk8bde7f72003-06-27 21:31:46 +0000421#define CFG_OR_TIMING_FLASH 0x00000ff4
422#define CFG_OR_TIMING_DOC 0x000001f4
wdenkdc7c9a12003-03-26 06:55:25 +0000423#define CFG_MxMR_PTx 0x4e000000
424#define CFG_MPTPR 0x400
425
wdenk8bde7f72003-06-27 21:31:46 +0000426#elif defined(CONFIG_75MHz)
427#define CFG_OR_TIMING_FLASH 0x000008f4
428#define CFG_OR_TIMING_DOC 0x000002f4
wdenkdc7c9a12003-03-26 06:55:25 +0000429#define CFG_MxMR_PTx 0x49000000
430#define CFG_MPTPR 0x400
431
432#elif defined(CONFIG_66MHz)
433#define CFG_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
wdenk8bde7f72003-06-27 21:31:46 +0000434 OR_SCY_3_CLK | OR_EHTR | OR_BI)
wdenkdc7c9a12003-03-26 06:55:25 +0000435/*#define CFG_OR_TIMING_FLASH 0x000001f4 */
wdenk8bde7f72003-06-27 21:31:46 +0000436#define CFG_OR_TIMING_DOC 0x000003f4
wdenkdc7c9a12003-03-26 06:55:25 +0000437#define CFG_MxMR_PTx 0x40000000
438#define CFG_MPTPR 0x400
439
440#else /* 50 MHz */
441#define CFG_OR_TIMING_FLASH 0x00000ff4
wdenk8bde7f72003-06-27 21:31:46 +0000442#define CFG_OR_TIMING_DOC 0x000001f4
wdenkdc7c9a12003-03-26 06:55:25 +0000443#define CFG_MxMR_PTx 0x30000000
444#define CFG_MPTPR 0x400
445#endif /*CONFIG_??MHz */
446
447
448#if defined (CONFIG_BOOT_8B) /* 512K X 8 ,29F040 , 2MB space */
449#define CFG_OR0_PRELIM (0xffe00000 | CFG_OR_TIMING_FLASH)
450#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_8)
451#elif defined (CONFIG_BOOT_16B) /* 29lv160 X 16 , 4MB space */
452#define CFG_OR0_PRELIM (0xffc00000 | CFG_OR_TIMING_FLASH)
453#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_16)
454#elif defined( CONFIG_BOOT_32B ) /* 29lv160 X 2 X 32, 4/8/16MB , 64MB space */
455#define CFG_OR0_PRELIM (0xfc000000 | CFG_OR_TIMING_FLASH)
456#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
457#else
458#error Boot device port size missing.
459#endif
460
461/*
462 * Disk-On-Chip configuration
463 */
464
465#define CFG_DOC_SHORT_TIMEOUT
466#define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
467
468#define CFG_DOC_SUPPORT_2000
469#define CFG_DOC_SUPPORT_MILLENNIUM
470#define CFG_DOC_BASE 0x80000000
471
472
473/*
474 * Internal Definitions
475 *
476 * Boot Flags
477 */
478#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
479#define BOOTFLAG_WARM 0x02 /* Software reboot */
480
481#endif /* __CONFIG_H */