blob: 0f35caa9be664ebc2138f53f89db3ba272dffe6a [file] [log] [blame]
wdenk3d3befa2004-03-14 15:06:13 +00001/*
2 * (C) Copyright 2002
3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
5 *
6 * (C) Copyright 2002
7 * David Mueller, ELSOFT AG, <d.mueller@elsoft.ch>
8 *
9 * (C) Copyright 2003
10 * Texas Instruments, <www.ti.com>
11 * Kshitij Gupta <Kshitij@ti.com>
12 *
13 * (C) Copyright 2004
14 * ARM Ltd.
15 * Philippe Robin, <philippe.robin@arm.com>
16 *
17 * See file CREDITS for list of people who contributed to this
18 * project.
19 *
20 * This program is free software; you can redistribute it and/or
21 * modify it under the terms of the GNU General Public License as
22 * published by the Free Software Foundation; either version 2 of
23 * the License, or (at your option) any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; if not, write to the Free Software
32 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
33 * MA 02111-1307 USA
34 */
35
36#include <common.h>
37
Wolfgang Denkd87080b2006-03-31 18:32:53 +020038DECLARE_GLOBAL_DATA_PTR;
39
wdenk3d3befa2004-03-14 15:06:13 +000040#if defined(CONFIG_SHOW_BOOT_PROGRESS)
41void show_boot_progress(int progress)
42{
43 printf("Boot reached stage %d\n", progress);
44}
45#endif
46
47#define COMP_MODE_ENABLE ((unsigned int)0x0000EAEF)
48
49static inline void delay (unsigned long loops)
50{
51 __asm__ volatile ("1:\n"
52 "subs %0, %1, #1\n"
53 "bne 1b":"=r" (loops):"0" (loops));
54}
55
56/*
57 * Miscellaneous platform dependent initialisations
58 */
59
60int board_init (void)
61{
wdenk3d3befa2004-03-14 15:06:13 +000062 /*
63 * set clock frequency:
64 * VERSATILE_REFCLK is 32KHz
65 * VERSATILE_TIMCLK is 1MHz
66 */
67 *(volatile unsigned int *)(VERSATILE_SCTL_BASE) |=
68 ((VERSATILE_TIMCLK << VERSATILE_TIMER1_EnSel) | (VERSATILE_TIMCLK << VERSATILE_TIMER2_EnSel) |
69 (VERSATILE_TIMCLK << VERSATILE_TIMER3_EnSel) | (VERSATILE_TIMCLK << VERSATILE_TIMER4_EnSel));
70
71 /* arch number of Versatile Board */
wdenk731215e2004-10-10 18:41:04 +000072 gd->bd->bi_arch_number = MACH_TYPE_VERSATILE_PB;
wdenk3d3befa2004-03-14 15:06:13 +000073
74 /* adress of boot parameters */
75 gd->bd->bi_boot_params = 0x00000100;
76
wdenkbc54f302004-07-11 18:10:30 +000077 gd->flags = 0;
78
wdenk3d3befa2004-03-14 15:06:13 +000079 icache_enable ();
80
wdenk3d3befa2004-03-14 15:06:13 +000081 return 0;
82}
83
84
85int misc_init_r (void)
86{
87 setenv("verify", "n");
88 return (0);
89}
90
91/******************************
92 Routine:
93 Description:
94******************************/
wdenk3d3befa2004-03-14 15:06:13 +000095int dram_init (void)
96{
97 return 0;
98}