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wdenk1d589e32001-01-20 01:23:52 +00001/*
2 * (C) Copyright 2000
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * defines for Cogent Motherboards
26 */
27
28#ifndef _COGENT_MB_H
29#define _COGENT_MB_H
30
31/*
32 * Cogent Motherboard Address Map
33 *
34 * The size of a Cogent motherboard address space is 256 Mbytes (i.e. 28 bits).
35 *
36 * The first 32 Mbyte (0x0000000-0x1FFFFFF) is usually RAM. The following
37 * 3 x 32 Mbyte areas (0x2000000-0x3FFFFFF, 0x4000000-0x5FFFFFF and
38 * 0x6000000-0x7FFFFFF) are general I/O "slots" (slots 1, 2 and 3).
39 * Most other motherboard devices have registers mapped into the area
40 * 0xE000000-0xFFFFFFF (Motherboard I/O slot?). The area 0x8000000-0xDFFFFFF
41 * is free for whatever.
42 *
43 * The location of the motherboard address space in the physical address space
44 * of the cpu is given by CMA_MB_BASE. This value is determined by the cpu
45 * module plugged into the motherboard and is configured above.
46 *
47 * Motherboard I/O devices mapped into the area (0xE000000-0xFFFFFFF)
48 * generally only use byte lane 0 (D0-7) for their transfers, i.e. only
49 * 8 bit, or 1 byte, transfers can take place, so all the registers are
50 * only 8 bits wide. The exceptions are the motherboard flash, which uses
51 * byte lanes 0 and 1 (i.e. 16 bits), and the mapped PCI address space.
52 *
53 * I/O registers within the mapped motherboard devices are 64 bit aligned
54 * i.e. they are 8 bytes apart. For big endian addressing, the 8 bit register
55 * will be at byte 7 (the address + 7). For little endian addressing, the
56 * register will be at byte 0 (the address + 0). To learn the endianess
wdenkda93ed82004-09-29 11:02:56 +000057 * we must include <endian.h>
wdenk1d589e32001-01-20 01:23:52 +000058 *
59 * Take the CMA102 and CMA111 motherboards as examples...
60 *
61 * The CMA102 has three CMABus I/O Expansion slots and no PCI bridge. The 3
62 * CMABus slots are each mapped directly onto the three general I/O slots.
63 *
64 * The CMA111 has only one CMABus I/O Expansion slot, but has a V360EPC PCI
65 * bridge. The CMABus slot is mapped onto general I/O slot 1. The standard
66 * PCI Bus space is mapped onto general I/O slot 2, with a small area at the
67 * top reserved for access to the V360EPC registers (0x5FF0000-0x5FFFFFF).
68 * I/O slot 3 is unused. The extended PCI Bus space is mapped onto the area
69 * 0xA000000-0xDFFFFFF.
70 */
71
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020072#define CMA_MB_RAM_BASE (CONFIG_SYS_CMA_MB_BASE+0x0000000)
wdenk1d589e32001-01-20 01:23:52 +000073#define CMA_MB_RAM_SIZE 0x2000000 /* dip sws set actual size */
74
75#if (CMA_MB_CAPS & CMA_MB_CAP_SLOT1)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020076#define CMA_MB_SLOT1_BASE (CONFIG_SYS_CMA_MB_BASE+0x2000000)
wdenk1d589e32001-01-20 01:23:52 +000077#define CMA_MB_SLOT1_SIZE 0x2000000
78#endif
79
80#if (CMA_MB_CAPS & CMA_MB_CAP_SLOT2)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020081#define CMA_MB_SLOT2_BASE (CONFIG_SYS_CMA_MB_BASE+0x4000000)
wdenk1d589e32001-01-20 01:23:52 +000082#define CMA_MB_SLOT2_SIZE 0x2000000
83#endif
84#if (CMA_MB_CAPS & CMA_MB_CAP_PCI)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020085#define CMA_MB_STDPCI_BASE (CONFIG_SYS_CMA_MB_BASE+0x4000000)
wdenk1d589e32001-01-20 01:23:52 +000086#define CMA_MB_STDPCI_SIZE 0x1ff0000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020087#define CMA_MB_V360EPC_BASE (CONFIG_SYS_CMA_MB_BASE+0x5ff0000)
wdenk1d589e32001-01-20 01:23:52 +000088#define CMA_MB_V360EPC_SIZE 0x10000
89#endif
90
91#if (CMA_MB_CAPS & CMA_MB_CAP_SLOT3)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020092#define CMA_MB_SLOT3_BASE (CONFIG_SYS_CMA_MB_BASE+0x6000000)
wdenk1d589e32001-01-20 01:23:52 +000093#define CMA_MB_SLOT3_SIZE 0x2000000
94#endif
95
96#if (CMA_MB_CAPS & CMA_MB_CAP_PCI_EXT)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020097#define CMA_MB_EXTPCI_BASE (CONFIG_SYS_CMA_MB_BASE+0xa000000)
wdenk1d589e32001-01-20 01:23:52 +000098#define CMA_MB_EXTPCI_SIZE 0x4000000
99#endif
100
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200101#define CMA_MB_ROMLOW_BASE (CONFIG_SYS_CMA_MB_BASE+0xe000000)
wdenk1d589e32001-01-20 01:23:52 +0000102#define CMA_MB_ROMLOW_SIZE 0x800000
103#if (CMA_MB_CAPS & CMA_MB_CAP_FLASH)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200104#define CMA_MB_FLLOW_EXEC_BASE (CONFIG_SYS_CMA_MB_BASE+0xe000000)
wdenk1d589e32001-01-20 01:23:52 +0000105#define CMA_MB_FLLOW_EXEC_SIZE 0x100000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200106#define CMA_MB_FLLOW_RDWR_BASE (CONFIG_SYS_CMA_MB_BASE+0xe400000)
wdenk1d589e32001-01-20 01:23:52 +0000107#define CMA_MB_FLLOW_RDWR_SIZE 0x400000
108#endif
109
110#if (CMA_MB_CAPS & CMA_MB_CAP_RTC)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200111#define CMA_MB_RTC_BASE (CONFIG_SYS_CMA_MB_BASE+0xe800000)
wdenk1d589e32001-01-20 01:23:52 +0000112#define CMA_MB_RTC_SIZE 0x4000
113#endif
114
115#if (CMA_MB_CAPS & CMA_MB_CAP_SERPAR)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200116#define CMA_MB_SERPAR_BASE (CONFIG_SYS_CMA_MB_BASE+0xe900000)
wdenk1d589e32001-01-20 01:23:52 +0000117#define CMA_MB_SERIALB_BASE (CMA_MB_SERPAR_BASE+0x00)
118#define CMA_MB_SERIALA_BASE (CMA_MB_SERPAR_BASE+0x40)
119#define CMA_MB_PARALLEL_BASE (CMA_MB_SERPAR_BASE+0x80)
120#define CMA_MB_SERPAR_SIZE 0xa0
121#endif
122
123#if (CMA_MB_CAPS & CMA_MB_CAP_KBM)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200124#define CMA_MB_PKBM_BASE (CONFIG_SYS_CMA_MB_BASE+0xe900100)
wdenk1d589e32001-01-20 01:23:52 +0000125#define CMA_MB_PKBM_SIZE 0x10
126#endif
127
128#if (CMA_MB_CAPS & CMA_MB_CAP_LCD)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200129#define CMA_MB_LCD_BASE (CONFIG_SYS_CMA_MB_BASE+0xeb00000)
wdenk1d589e32001-01-20 01:23:52 +0000130#define CMA_MB_LCD_SIZE 0x10
131#endif
132
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200133#define CMA_MB_DIPSW_BASE (CONFIG_SYS_CMA_MB_BASE+0xec00000)
wdenk1d589e32001-01-20 01:23:52 +0000134#define CMA_MB_DIPSW_SIZE 0x10
135
136#if (CMA_MB_CAPS & (CMA_MB_CAP_SLOT1|CMA_MB_CAP_SER2|CMA_MB_CAP_KBM))
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200137#define CMA_MB_SLOT1CFG_BASE (CONFIG_SYS_CMA_MB_BASE+0xf100000)
wdenk1d589e32001-01-20 01:23:52 +0000138#if (CMA_MB_CAPS & CMA_MB_CAP_SER2)
139#define CMA_MB_SER2_BASE (CMA_MB_SLOT1CFG_BASE+0x80)
140#define CMA_MB_SER2B_BASE (CMA_MB_SER2_BASE+0x00)
141#define CMA_MB_SER2A_BASE (CMA_MB_SER2_BASE+0x40)
142#endif
143#if defined(CONFIG_CMA302) && defined(CONFIG_CMA302_SLOT1)
144#define CMA_MB_S1KBM_BASE (CMA_MB_SLOT1CFG_BASE+0x200)
145#endif
146#if (CMA_MB_CAPS & CMA_MB_CAP_KBM) && !defined(COGENT_CMA150)
147#define CMA_MB_IREQ1STAT_BASE (CMA_MB_SLOT1CFG_BASE+0x100)
148#define CMA_MB_AKBM_BASE (CMA_MB_SLOT1CFG_BASE+0x200)
149#define CMA_MB_IREQ1MASK_BASE (CMA_MB_SLOT1CFG_BASE+0x300)
150#endif
151#define CMA_MB_SLOT1CFG_SIZE 0x400
152#endif
153
154#if (CMA_MB_CAPS & CMA_MB_CAP_SLOT2)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200155#define CMA_MB_SLOT2CFG_BASE (CONFIG_SYS_CMA_MB_BASE+0xf200000)
wdenk1d589e32001-01-20 01:23:52 +0000156#if defined(CONFIG_CMA302) && defined(CONFIG_CMA302_SLOT2)
157#define CMA_MB_S2KBM_BASE (CMA_MB_SLOT2CFG_BASE+0x200)
158#endif
159#define CMA_MB_SLOT2CFG_SIZE 0x400
160#endif
161
162#if (CMA_MB_CAPS & CMA_MB_CAP_PCI)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200163#define CMA_MB_PCICTL_BASE (CONFIG_SYS_CMA_MB_BASE+0xf200000)
wdenk1d589e32001-01-20 01:23:52 +0000164#define CMA_MB_PCI_V3CTL_BASE (CMA_MB_PCICTL_BASE+0x100)
165#define CMA_MB_PCI_IDSEL_BASE (CMA_MB_PCICTL_BASE+0x200)
166#define CMA_MB_PCI_IMASK_BASE (CMA_MB_PCICTL_BASE+0x300)
167#define CMA_MB_PCI_ISTAT_BASE (CMA_MB_PCICTL_BASE+0x400)
168#define CMA_MB_PCI_MBID_BASE (CMA_MB_PCICTL_BASE+0x500)
169#define CMA_MB_PCI_MBREV_BASE (CMA_MB_PCICTL_BASE+0x600)
170#define CMA_MB_PCICTL_SIZE 0x700
171#endif
172
173#if (CMA_MB_CAPS & CMA_MB_CAP_SLOT3)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200174#define CMA_MB_SLOT3CFG_BASE (CONFIG_SYS_CMA_MB_BASE+0xf300000)
wdenk1d589e32001-01-20 01:23:52 +0000175#if defined(CONFIG_CMA302) && defined(CONFIG_CMA302_SLOT3)
176#define CMA_MB_S3KBM_BASE (CMA_MB_SLOT3CFG_BASE+0x200)
177#endif
178#define CMA_MB_SLOT3CFG_SIZE 0x400
179#endif
180
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200181#define CMA_MB_ROMHIGH_BASE (CONFIG_SYS_CMA_MB_BASE+0xf800000)
wdenk1d589e32001-01-20 01:23:52 +0000182#define CMA_MB_ROMHIGH_SIZE 0x800000
183#if (CMA_MB_CAPS & CMA_MB_CAP_FLASH)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200184#define CMA_MB_FLHIGH_EXEC_BASE (CONFIG_SYS_CMA_MB_BASE+0xf800000)
wdenk1d589e32001-01-20 01:23:52 +0000185#define CMA_MB_FLHIGH_EXEC_SIZE 0x100000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200186#define CMA_MB_FLHIGH_RDWR_BASE (CONFIG_SYS_CMA_MB_BASE+0xfc00000)
wdenk1d589e32001-01-20 01:23:52 +0000187#define CMA_MB_FLHIGH_RDWR_SIZE 0x400000
188#endif
189
190#if (CMA_MB_CAPS & CMA_MB_CAP_PCI)
191
192/* PCI Control Register bits */
193
194/* V360EPC Control register bits */
195#define CMA_MB_PCI_V3CTL_RESET 0x01
196#define CMA_MB_PCI_V3CTL_EXTADD 0x08
197
198/* PCI ID Select register bits */
199#define CMA_MB_PCI_IDSEL_SLOTA 0x01
200#define CMA_MB_PCI_IDSEL_SLOTB 0x02
201#define CMA_MB_PCI_IDSEL_GD82559 0x04
202#define CMA_MB_PCI_IDSEL_B69000 0x08
203#define CMA_MB_PCI_IDSEL_PD6832 0x10
204
205/* PCI Interrupt Mask/Status register bits */
206#define CMA_MB_PCI_IMS_INTA 0x01
207#define CMA_MB_PCI_IMS_INTB 0x02
208#define CMA_MB_PCI_IMS_INTC 0x04
209#define CMA_MB_PCI_IMS_INTD 0x08
210#define CMA_MB_PCI_IMS_CBINT 0x10
211#define CMA_MB_PCI_IMS_V3LINT 0x80
212
213#endif
214
215#if (CMA_MB_CAPS & (CMA_MB_CAP_KBM|CMA_MB_CAP_SER2)) && !defined(COGENT_CMA150)
216
217/*
218 * IREQ1 Interrupt Mask/Status register bits
219 * (Note: not available on CMA150 - must poll HT6542B interrupt register)
220 */
221
222#define IREQ1_MINT 0x01
223#define IREQ1_KINT 0x02
224#if (CMA_MB_CAPS & CMA_MB_CAP_SER2)
225#define IREQ1_SINT2 0x04
226#define IREQ1_SINT3 0x08
227#endif
228
229#endif
230
231#ifndef __ASSEMBLY__
232
wdenkda93ed82004-09-29 11:02:56 +0000233#ifdef USE_HOSTCC
234#include <endian.h> /* avoid using private kernel header files */
235#else
236#include <asm/byteorder.h> /* use U-Boot provided headers */
237#endif
wdenk1d589e32001-01-20 01:23:52 +0000238
239/* a single CMA10x motherboard i/o register */
240typedef
241 struct {
wdenkda93ed82004-09-29 11:02:56 +0000242#if __BYTE_ORDER == __LITTLE_ENDIAN
wdenk1d589e32001-01-20 01:23:52 +0000243 unsigned char value;
244#endif
245 unsigned char filler[7];
wdenkda93ed82004-09-29 11:02:56 +0000246#if __BYTE_ORDER == __BIG_ENDIAN
wdenk1d589e32001-01-20 01:23:52 +0000247 unsigned char value;
248#endif
249 }
250cma_mb_reg;
251
252extern __inline__ unsigned char
253cma_mb_reg_read(volatile cma_mb_reg *reg)
254{
255 unsigned char data = reg->value;
256 __asm__ __volatile__ ("eieio" : : : "memory");
257 return data;
258}
259
260extern __inline__ void
261cma_mb_reg_write(volatile cma_mb_reg *reg, unsigned char data)
262{
263 reg->value = data;
264 __asm__ __volatile__ ("eieio" : : : "memory");
265}
266
267#if (CMA_MB_CAPS & CMA_MB_CAP_RTC)
268
269/* MK48T02 RTC registers */
270typedef
271 struct {
272 cma_mb_reg sram[2040];/* Battery-Backed SRAM */
273 cma_mb_reg clk_ctl; /* Clock Control Register */
274 cma_mb_reg clk_sec; /* Clock Seconds Register */
275 cma_mb_reg clk_min; /* Clock Minutes Register */
276 cma_mb_reg clk_hour; /* Clock Hour Register */
277 cma_mb_reg clk_day; /* Clock Day Register */
278 cma_mb_reg clk_date; /* Clock Date Register */
279 cma_mb_reg clk_month; /* Clock Month Register */
280 cma_mb_reg clk_year; /* Clock Year Register */
281 }
282cma_mb_rtc;
283
284#endif
285
286#if (CMA_MB_CAPS & CMA_MB_CAP_SERPAR)
287
288/* ST16C522 Serial I/O */
289typedef
290 struct {
291 cma_mb_reg ser_rhr; /* Receive Holding Register (R, DLAB=0) */
292 cma_mb_reg ser_ier; /* Interrupt Enable Register (R/W, DLAB=0) */
293 cma_mb_reg ser_isr; /* Interrupt Status Register (R) */
294 cma_mb_reg ser_lcr; /* Line Control Register (R/W) */
295 cma_mb_reg ser_mcr; /* Modem Control Register (R/W) */
296 cma_mb_reg ser_lsr; /* Line Status Register (R) */
297 cma_mb_reg ser_msr; /* Modem Status Register (R/W) */
298 cma_mb_reg ser_spr; /* Scratch Pad Register (R/W) */
299 }
300cma_mb_serial;
301
302#define ser_thr ser_rhr /* Transmit Holding Register (W, DLAB=0) */
303#define ser_brl ser_rhr /* Baud Rate Divisor Low Byte (R/W, DLAB=1) */
304#define ser_brh ser_ier /* Baud Rate Divisor High Byte (R/W, DLAB=1) */
305#define ser_fcr ser_isr /* FIFO Control Register (W) */
306#define ser_nop ser_lsr /* No Operation (W) */
307
308/* ST16C522 Parallel I/O */
309typedef
310 struct {
311 cma_mb_reg par_rdr; /* Port Read Data Register (R) */
312 cma_mb_reg par_sr; /* Status Register (R) */
313 cma_mb_reg par_cmd; /* Command Register (R) */
314 }
315cma_mb_parallel;
316
317#define par_wdr par_rdr /* Port Write Data Register (W) */
318#define par_ios par_sr /* I/O Select Register (W) */
319#define par_ctl par_cmd /* Control Register (W) */
320
321#endif
322
323#if (CMA_MB_CAPS & CMA_MB_CAP_KBM) || defined(CONFIG_CMA302)
324
325/* HT6542B PS/2 Keyboard/Mouse Controller */
326typedef
327 struct {
328 cma_mb_reg kbm_rdr; /* Read Data Register (R) */
329 cma_mb_reg kbm_sr; /* Status Register (R) */
330 }
331cma_mb_kbm;
332
333#define kbm_wdr kbm_rdr /* Write Data Register (W) */
334#define kbm_cmd kbm_sr /* Command Register (W) */
335
336#endif
337
338#if (CMA_MB_CAPS & CMA_MB_CAP_LCD)
339
340/* HD44780 LCD Display */
341typedef
342 struct {
343 cma_mb_reg lcd_ccr; /* Current Character Register (R/W) */
344 cma_mb_reg lcd_bsr; /* Busy Status Register (R) */
345 }
346cma_mb_lcd;
347
348#define lcd_cmd lcd_bsr /* Command Register (W) */
349
350#endif
351
352/* 8-Position Configuration Switch */
353typedef
354 struct {
355 cma_mb_reg dip_val; /* Dip Switch value (R) */
356 }
357cma_mb_dipsw;
358
359#if (CMA_MB_CAPS & CMA_MB_CAP_PCI)
360
361/* V360EPC PCI Bridge */
362typedef
363 struct {
wdenkda93ed82004-09-29 11:02:56 +0000364#if __BYTE_ORDER == __LITTLE_ENDIAN
wdenk1d589e32001-01-20 01:23:52 +0000365 unsigned short v3_pci_vendor; /* 0x00 */
366 unsigned short v3_pci_device;
367 unsigned short v3_pci_cmd; /* 0x04 */
368 unsigned short v3_pci_stat;
369 unsigned long v3_pci_cc_rev; /* 0x08 */
370 unsigned long v3_pci_hdr_cfg; /* 0x0c */
371 unsigned long v3_pci_io_base; /* 0x10 */
372 unsigned long v3_pci_base0; /* 0x14 */
373 unsigned long v3_pci_base1; /* 0x18 */
374 unsigned long reserved1[4]; /* 0x1c */
375 unsigned short v3_pci_sub_vendor; /* 0x2c */
376 unsigned short v3_pci_sub_id;
377 unsigned long v3_pci_rom; /* 0x30 */
378 unsigned long reserved2[2]; /* 0x34 */
379 unsigned long v3_pci_bparam; /* 0x3c */
380 unsigned long v3_pci_map0; /* 0x40 */
381 unsigned long v3_pci_map1; /* 0x44 */
382 unsigned long v3_pci_int_stat; /* 0x48 */
383 unsigned long v3_pci_int_cfg; /* 0x4c */
384 unsigned long reserved3[1]; /* 0x50 */
385 unsigned long v3_lb_base0; /* 0x54 */
386 unsigned long v3_lb_base1; /* 0x58 */
387 unsigned short reserved4; /* 0x5c */
388 unsigned short v3_lb_map0;
389 unsigned short reserved5; /* 0x60 */
390 unsigned short v3_lb_map1;
391 unsigned short v3_lb_base2; /* 0x64 */
392 unsigned short v3_lb_map2;
393 unsigned long v3_lb_size; /* 0x68 */
394 unsigned short reserved6; /* 0x6c */
395 unsigned short v3_lb_io_base;
396 unsigned short v3_fifo_cfg; /* 0x70 */
397 unsigned short v3_fifo_priority;
398 unsigned short v3_fifo_stat; /* 0x74 */
399 unsigned char v3_lb_istat;
400 unsigned char v3_lb_imask;
401 unsigned short v3_system; /* 0x78 */
402 unsigned short v3_lb_cfg;
403 unsigned short v3_pci_cfg; /* 0x7c */
404 unsigned short reserved7;
405 unsigned long v3_dma_pci_addr0; /* 0x80 */
406 unsigned long v3_dma_local_addr0; /* 0x84 */
407 unsigned long v3_dma_length0:24; /* 0x88 */
408 unsigned long v3_dma_csr0:8;
409 unsigned long v3_dma_ctlb_adr0; /* 0x8c */
410 unsigned long v3_dma_pci_addr1; /* 0x90 */
411 unsigned long v3_dma_local_addr1; /* 0x94 */
412 unsigned long v3_dma_length1:24; /* 0x98 */
413 unsigned long v3_dma_csr1:8;
414 unsigned long v3_dma_ctlb_adr1; /* 0x9c */
415 unsigned long v3_i20_mups[8]; /* 0xa0 */
416 unsigned char v3_mail_data0; /* 0xc0 */
417 unsigned char v3_mail_data1;
418 unsigned char v3_mail_data2;
419 unsigned char v3_mail_data3;
420 unsigned char v3_mail_data4; /* 0xc4 */
421 unsigned char v3_mail_data5;
422 unsigned char v3_mail_data6;
423 unsigned char v3_mail_data7;
424 unsigned char v3_mail_data8; /* 0xc8 */
425 unsigned char v3_mail_data9;
426 unsigned char v3_mail_data10;
427 unsigned char v3_mail_data11;
428 unsigned char v3_mail_data12; /* 0xcc */
429 unsigned char v3_mail_data13;
430 unsigned char v3_mail_data14;
431 unsigned char v3_mail_data15;
432 unsigned short v3_pci_mail_iewr; /* 0xd0 */
433 unsigned short v3_pci_mail_ierd;
434 unsigned short v3_lb_mail_iewr; /* 0xd4 */
435 unsigned short v3_lb_mail_ierd;
436 unsigned short v3_mail_wr_stat; /* 0xd8 */
437 unsigned short v3_mail_rd_stat;
438 unsigned long v3_qba_map; /* 0xdc */
439 unsigned long v3_dma_delay:8; /* 0xe0 */
440 unsigned long reserved8:24;
441 unsigned long reserved9[7]; /* 0xe4 */
442#endif
wdenkda93ed82004-09-29 11:02:56 +0000443#if __BYTE_ORDER == __BIG_ENDIAN
wdenk1d589e32001-01-20 01:23:52 +0000444 unsigned short v3_pci_device; /* 0x00 */
445 unsigned short v3_pci_vendor;
446 unsigned short v3_pci_stat; /* 0x04 */
447 unsigned short v3_pci_cmd;
448 unsigned long v3_pci_cc_rev; /* 0x08 */
449 unsigned long v3_pci_hdr_cfg; /* 0x0c */
450 unsigned long v3_pci_io_base; /* 0x10 */
451 unsigned long v3_pci_base0; /* 0x14 */
452 unsigned long v3_pci_base1; /* 0x18 */
453 unsigned long reserved1[4]; /* 0x1c */
454 unsigned short v3_pci_sub_id; /* 0x2c */
455 unsigned short v3_pci_sub_vendor;
456 unsigned long v3_pci_rom; /* 0x30 */
457 unsigned long reserved2[2]; /* 0x34 */
458 unsigned long v3_pci_bparam; /* 0x3c */
459 unsigned long v3_pci_map0; /* 0x40 */
460 unsigned long v3_pci_map1; /* 0x44 */
461 unsigned long v3_pci_int_stat; /* 0x48 */
462 unsigned long v3_pci_int_cfg; /* 0x4c */
463 unsigned long reserved3; /* 0x50 */
464 unsigned long v3_lb_base0; /* 0x54 */
465 unsigned long v3_lb_base1; /* 0x58 */
466 unsigned short v3_lb_map0; /* 0x5c */
467 unsigned short reserved4;
468 unsigned short v3_lb_map1; /* 0x60 */
469 unsigned short reserved5;
470 unsigned short v3_lb_map2; /* 0x64 */
471 unsigned short v3_lb_base2;
472 unsigned long v3_lb_size; /* 0x68 */
473 unsigned short v3_lb_io_base; /* 0x6c */
474 unsigned short reserved6;
475 unsigned short v3_fifo_priority; /* 0x70 */
476 unsigned short v3_fifo_cfg;
477 unsigned char v3_lb_imask; /* 0x74 */
478 unsigned char v3_lb_istat;
479 unsigned short v3_fifo_stat;
480 unsigned short v3_lb_cfg; /* 0x78 */
481 unsigned short v3_system;
482 unsigned short reserved7; /* 0x7c */
483 unsigned short v3_pci_cfg;
484 unsigned long v3_dma_pci_addr0; /* 0x80 */
485 unsigned long v3_dma_local_addr0; /* 0x84 */
486 unsigned long v3_dma_csr0:8; /* 0x88 */
487 unsigned long v3_dma_length0:24;
488 unsigned long v3_dma_ctlb_adr0; /* 0x8c */
489 unsigned long v3_dma_pci_addr1; /* 0x90 */
490 unsigned long v3_dma_local_addr1; /* 0x94 */
491 unsigned long v3_dma_csr1:8; /* 0x98 */
492 unsigned long v3_dma_length1:24;
493 unsigned long v3_dma_ctlb_adr1; /* 0x9c */
494 unsigned long v3_i20_mups[8]; /* 0xa0 */
495 unsigned char v3_mail_data3; /* 0xc0 */
496 unsigned char v3_mail_data2;
497 unsigned char v3_mail_data1;
498 unsigned char v3_mail_data0;
499 unsigned char v3_mail_data7; /* 0xc4 */
500 unsigned char v3_mail_data6;
501 unsigned char v3_mail_data5;
502 unsigned char v3_mail_data4;
503 unsigned char v3_mail_data11; /* 0xc8 */
504 unsigned char v3_mail_data10;
505 unsigned char v3_mail_data9;
506 unsigned char v3_mail_data8;
507 unsigned char v3_mail_data15; /* 0xcc */
508 unsigned char v3_mail_data14;
509 unsigned char v3_mail_data13;
510 unsigned char v3_mail_data12;
511 unsigned short v3_pci_mail_ierd; /* 0xd0 */
512 unsigned short v3_pci_mail_iewr;
513 unsigned short v3_lb_mail_ierd; /* 0xd4 */
514 unsigned short v3_lb_mail_iewr;
515 unsigned short v3_mail_rd_stat; /* 0xd8 */
516 unsigned short v3_mail_wr_stat;
517 unsigned long v3_qba_map; /* 0xdc */
518 unsigned long reserved8:24; /* 0xe0 */
519 unsigned long v3_dma_delay:8;
520 unsigned long reserved9[7]; /* 0xe4 */
521#endif
522 } /* 0x100 */
523cma_mb_v360epc;
524
525#endif
526
527#endif /* __ASSEMBLY__ */
528
529#endif /* _COGENT_MB_H */