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Stefan Roese4745aca2007-02-20 10:57:08 +01001/*
2 * (C) Copyright 2007
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * (C) Copyright 2004 Paul Reynolds <PaulReynolds@lhsolutions.com>
6 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02007 * SPDX-License-Identifier: GPL-2.0+
Stefan Roese4745aca2007-02-20 10:57:08 +01008 */
9
10/************************************************************************
11 * katmai.h - configuration for AMCC Katmai (440SPe)
12 ***********************************************************************/
13
14#ifndef __CONFIG_H
15#define __CONFIG_H
Wolfgang Denk83b4cfa2007-06-20 18:14:24 +020016
Stefan Roese4745aca2007-02-20 10:57:08 +010017/*-----------------------------------------------------------------------
18 * High Level Configuration Options
19 *----------------------------------------------------------------------*/
20#define CONFIG_KATMAI 1 /* Board is Katmai */
21#define CONFIG_4xx 1 /* ... PPC4xx family */
22#define CONFIG_440 1 /* ... PPC440 family */
23#define CONFIG_440SPE 1 /* Specifc SPe support */
Stefan Roese2a72e9e2010-04-09 14:03:59 +020024#define CONFIG_440SPE_REVA 1 /* Support old Rev A. */
Stefan Roese4745aca2007-02-20 10:57:08 +010025#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020026#define CONFIG_SYS_4xx_RESET_TYPE 0x2 /* use chip reset on this board */
Stefan Roese490f2042008-06-06 15:55:03 +020027
Wolfgang Denk2ae18242010-10-06 09:05:45 +020028#define CONFIG_SYS_TEXT_BASE 0xFFFA0000
29
Stefan Roese490f2042008-06-06 15:55:03 +020030/*
Stefan Roese5d812b82008-07-09 17:33:57 +020031 * Enable this board for more than 2GB of SDRAM
32 */
33#define CONFIG_PHYS_64BIT
34#define CONFIG_VERY_BIG_RAM
Stefan Roese5d812b82008-07-09 17:33:57 +020035
36/*
Stefan Roese490f2042008-06-06 15:55:03 +020037 * Include common defines/options for all AMCC eval boards
38 */
39#define CONFIG_HOSTNAME katmai
40#include "amcc-common.h"
Stefan Roese4745aca2007-02-20 10:57:08 +010041
42#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
Stefan Roese4745aca2007-02-20 10:57:08 +010043#undef CONFIG_SHOW_BOOT_PROGRESS
44
45/*-----------------------------------------------------------------------
46 * Base addresses -- Note these are effective addresses where the
47 * actual resources get mapped (not physical addresses)
48 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020049#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020050#define CONFIG_SYS_ISRAM_BASE 0x90000000 /* internal SRAM */
Stefan Roese4745aca2007-02-20 10:57:08 +010051
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020052#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped PCI memory */
53#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */
54#define CONFIG_SYS_PCI_TARGBASE CONFIG_SYS_PCI_MEMBASE
Stefan Roese4745aca2007-02-20 10:57:08 +010055
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020056#define CONFIG_SYS_PCIE_MEMBASE 0xb0000000 /* mapped PCIe memory */
57#define CONFIG_SYS_PCIE_MEMSIZE 0x08000000 /* smallest incr for PCIe port */
58#define CONFIG_SYS_PCIE_BASE 0xe0000000 /* PCIe UTL regs */
Stefan Roese4745aca2007-02-20 10:57:08 +010059
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020060#define CONFIG_SYS_PCIE0_CFGBASE 0xc0000000
61#define CONFIG_SYS_PCIE1_CFGBASE 0xc1000000
62#define CONFIG_SYS_PCIE2_CFGBASE 0xc2000000
63#define CONFIG_SYS_PCIE0_XCFGBASE 0xc3000000
64#define CONFIG_SYS_PCIE1_XCFGBASE 0xc3001000
65#define CONFIG_SYS_PCIE2_XCFGBASE 0xc3002000
Stefan Roese4745aca2007-02-20 10:57:08 +010066
Stefan Roese97923772007-10-05 09:18:23 +020067/* base address of inbound PCIe window */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020068#define CONFIG_SYS_PCIE_INBOUND_BASE 0x0000000000000000ULL
Stefan Roese97923772007-10-05 09:18:23 +020069
Stefan Roese4745aca2007-02-20 10:57:08 +010070/* System RAM mapped to PCI space */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020071#define CONFIG_PCI_SYS_MEM_BUS CONFIG_SYS_SDRAM_BASE
72#define CONFIG_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE
Stefan Roese4745aca2007-02-20 10:57:08 +010073#define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024)
74
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020075#define CONFIG_SYS_ACE_BASE 0xfe000000 /* Xilinx ACE controller - Compact Flash */
Stefan Roese4745aca2007-02-20 10:57:08 +010076
77/*-----------------------------------------------------------------------
78 * Initial RAM & stack pointer (placed in internal SRAM)
79 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020080#define CONFIG_SYS_TEMP_STACK_OCM 1
81#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE
82#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */
Wolfgang Denk553f0982010-10-26 13:32:32 +020083#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM */
Stefan Roese4745aca2007-02-20 10:57:08 +010084
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +020085#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Michael Zaidman800eb092010-09-20 08:51:53 +020086#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
Stefan Roese4745aca2007-02-20 10:57:08 +010087
88/*-----------------------------------------------------------------------
89 * Serial Port
90 *----------------------------------------------------------------------*/
Stefan Roese550650d2010-09-20 16:05:31 +020091#define CONFIG_CONS_INDEX 1 /* Use UART0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020092#undef CONFIG_SYS_EXT_SERIAL_CLOCK
Stefan Roese4745aca2007-02-20 10:57:08 +010093
94/*-----------------------------------------------------------------------
95 * DDR SDRAM
96 *----------------------------------------------------------------------*/
97#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */
Stefan Roeseba58e4c2007-03-01 21:11:36 +010098#define SPD_EEPROM_ADDRESS {0x51, 0x52} /* SPD i2c spd addresses*/
Stefan Roese2721a682007-03-08 10:07:18 +010099#define CONFIG_DDR_ECC 1 /* with ECC support */
Stefan Roese845c6c92008-01-05 09:12:41 +0100100#define CONFIG_DDR_RQDC_FIXED 0x80000038 /* optimal value found by GDA*/
Stefan Roese4745aca2007-02-20 10:57:08 +0100101#undef CONFIG_STRESS
Stefan Roese4745aca2007-02-20 10:57:08 +0100102
103/*-----------------------------------------------------------------------
104 * I2C
105 *----------------------------------------------------------------------*/
Dirk Eibach880540d2013-04-25 02:40:01 +0000106#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
Stefan Roese4745aca2007-02-20 10:57:08 +0100107
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200108#define CONFIG_SYS_SPD_BUS_NUM 0 /* The I2C bus for SPD */
Stefan Roese4745aca2007-02-20 10:57:08 +0100109
110#define IIC0_BOOTPROM_ADDR 0x50
111#define IIC0_ALT_BOOTPROM_ADDR 0x54
112
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200113#define CONFIG_SYS_I2C_MULTI_EEPROMS
114#define CONFIG_SYS_I2C_EEPROM_ADDR (0x50)
115#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
116#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
117#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
Stefan Roese4745aca2007-02-20 10:57:08 +0100118
Stefan Roeseefe12bc2009-11-09 14:15:42 +0100119/* I2C bootstrap EEPROM */
120#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x50
121#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0
122#define CONFIG_4xx_CONFIG_BLOCKSIZE 8
123
Stefan Roese4745aca2007-02-20 10:57:08 +0100124/* I2C RTC */
125#define CONFIG_RTC_M41T11 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200126#define CONFIG_SYS_RTC_BUS_NUM 1 /* The I2C bus for RTC */
127#define CONFIG_SYS_I2C_RTC_ADDR 0x68
128#define CONFIG_SYS_M41T11_BASE_YEAR 1900 /* play along with linux */
Stefan Roese4745aca2007-02-20 10:57:08 +0100129
130/* I2C DTT */
131#define CONFIG_DTT_ADM1021 1 /* ADM1021 temp sensor support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200132#define CONFIG_SYS_DTT_BUS_NUM 1 /* The I2C bus for DTT */
Stefan Roese4745aca2007-02-20 10:57:08 +0100133/*
134 * standard dtt sensor configuration - bottom bit will determine local or
135 * remote sensor of the ADM1021, the rest determines index into
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200136 * CONFIG_SYS_DTT_ADM1021 array below.
Stefan Roese4745aca2007-02-20 10:57:08 +0100137 */
138#define CONFIG_DTT_SENSORS { 0, 1 }
139
140/*
141 * ADM1021 temp sensor configuration (see dtt/adm1021.c for details).
142 * there will be one entry in this array for each two (dummy) sensors in
143 * CONFIG_DTT_SENSORS.
144 *
145 * For Katmai board:
146 * - only one ADM1021
147 * - i2c addr 0x18
148 * - conversion rate 0x02 = 0.25 conversions/second
149 * - ALERT ouput disabled
150 * - local temp sensor enabled, min set to 0 deg, max set to 85 deg
151 * - remote temp sensor enabled, min set to 0 deg, max set to 85 deg
152 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200153#define CONFIG_SYS_DTT_ADM1021 { { 0x18, 0x02, 0, 1, 0, 85, 1, 0, 58} }
Stefan Roese4745aca2007-02-20 10:57:08 +0100154
155/*-----------------------------------------------------------------------
156 * Environment
157 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200158#define CONFIG_ENV_IS_IN_FLASH 1 /* Environment uses flash */
Stefan Roese4745aca2007-02-20 10:57:08 +0100159
Stefan Roese490f2042008-06-06 15:55:03 +0200160/*
161 * Default environment variables
162 */
Stefan Roese4745aca2007-02-20 10:57:08 +0100163#define CONFIG_EXTRA_ENV_SETTINGS \
Stefan Roese490f2042008-06-06 15:55:03 +0200164 CONFIG_AMCC_DEF_ENV \
165 CONFIG_AMCC_DEF_ENV_POWERPC \
Stefan Roese490f2042008-06-06 15:55:03 +0200166 CONFIG_AMCC_DEF_ENV_NOR_UPD \
Stefan Roesefc21cd52010-08-03 10:29:50 +0200167 "kernel_addr=ff000000\0" \
168 "fdt_addr=ff1e0000\0" \
169 "ramdisk_addr=ff200000\0" \
Grzegorz Bernacki6efc1fc2007-09-07 18:35:37 +0200170 "pciconfighost=1\0" \
Stefan Roesed4cb2d12007-10-13 16:43:23 +0200171 "pcie_mode=RP:RP:RP\0" \
Stefan Roese4745aca2007-02-20 10:57:08 +0100172 ""
Stefan Roese4745aca2007-02-20 10:57:08 +0100173
Jon Loeligerbc234c12007-07-04 22:32:51 -0500174/*
Stefan Roese490f2042008-06-06 15:55:03 +0200175 * Commands additional to the ones defined in amcc-common.h
Jon Loeliger079a1362007-07-10 10:12:10 -0500176 */
Stefan Roeseefe12bc2009-11-09 14:15:42 +0100177#define CONFIG_CMD_CHIP_CONFIG
Jon Loeligerbc234c12007-07-04 22:32:51 -0500178#define CONFIG_CMD_DATE
Stefan Roesee3722862010-07-22 19:06:14 +0200179#define CONFIG_CMD_ECCTEST
Stefan Roeseefe12bc2009-11-09 14:15:42 +0100180#define CONFIG_CMD_EXT2
181#define CONFIG_CMD_FAT
Jon Loeligerbc234c12007-07-04 22:32:51 -0500182#define CONFIG_CMD_PCI
Jon Loeligerbc234c12007-07-04 22:32:51 -0500183#define CONFIG_CMD_SDRAM
Stefan Roeseafe9fa52007-10-22 16:24:44 +0200184#define CONFIG_CMD_SNTP
Stefan Roese4745aca2007-02-20 10:57:08 +0100185
186#define CONFIG_IBM_EMAC4_V4 1 /* 440SPe has this EMAC version */
Stefan Roese4745aca2007-02-20 10:57:08 +0100187#define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
188#define CONFIG_HAS_ETH0
189#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
190#define CONFIG_PHY_RESET_DELAY 1000
191#define CONFIG_CIS8201_PHY 1 /* Enable 'special' RGMII mode for Cicada phy */
192#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
Stefan Roese4745aca2007-02-20 10:57:08 +0100193
194/*-----------------------------------------------------------------------
195 * FLASH related
196 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200197#define CONFIG_SYS_FLASH_CFI
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200198#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200199#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
200#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
Stefan Roese4745aca2007-02-20 10:57:08 +0100201
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200202#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
203#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
204#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
Stefan Roese4745aca2007-02-20 10:57:08 +0100205
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200206#undef CONFIG_SYS_FLASH_CHECKSUM
207#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
208#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
Stefan Roese4745aca2007-02-20 10:57:08 +0100209
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200210#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200211#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200212#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
Stefan Roese4745aca2007-02-20 10:57:08 +0100213
214/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200215#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
216#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Stefan Roese4745aca2007-02-20 10:57:08 +0100217
218/*-----------------------------------------------------------------------
219 * PCI stuff
220 *-----------------------------------------------------------------------
221 */
222/* General PCI */
223#define CONFIG_PCI /* include pci support */
Gabor Juhos842033e2013-05-30 07:06:12 +0000224#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
Stefan Roese4745aca2007-02-20 10:57:08 +0100225#define CONFIG_PCI_PNP 1 /* do pci plug-and-play */
226#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
Grzegorz Bernacki6efc1fc2007-09-07 18:35:37 +0200227#define CONFIG_PCI_CONFIG_HOST_BRIDGE
Stefan Roese4745aca2007-02-20 10:57:08 +0100228
229/* Board-specific PCI */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200230#define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */
231#undef CONFIG_SYS_PCI_MASTER_INIT
Stefan Roese4745aca2007-02-20 10:57:08 +0100232
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200233#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
234#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
235/* #define CONFIG_SYS_PCI_SUBSYS_ID CONFIG_SYS_PCI_SUBSYS_DEVICEID */
Stefan Roese4745aca2007-02-20 10:57:08 +0100236
237/*
238 * NETWORK Support (PCI):
239 */
240/* Support for Intel 82557/82559/82559ER chips. */
241#define CONFIG_EEPRO100
242
243/*-----------------------------------------------------------------------
244 * Xilinx System ACE support
245 *----------------------------------------------------------------------*/
246#define CONFIG_SYSTEMACE 1 /* Enable SystemACE support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200247#define CONFIG_SYS_SYSTEMACE_WIDTH 16 /* Data bus width is 16 */
248#define CONFIG_SYS_SYSTEMACE_BASE CONFIG_SYS_ACE_BASE
Stefan Roese4745aca2007-02-20 10:57:08 +0100249#define CONFIG_DOS_PARTITION 1
250
251/*-----------------------------------------------------------------------
252 * External Bus Controller (EBC) Setup
253 *----------------------------------------------------------------------*/
254
255/* Memory Bank 0 (Flash) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200256#define CONFIG_SYS_EBC_PB0AP (EBC_BXAP_BME_DISABLED | \
Stefan Roese4745aca2007-02-20 10:57:08 +0100257 EBC_BXAP_TWT_ENCODE(7) | \
258 EBC_BXAP_BCE_DISABLE | \
259 EBC_BXAP_BCT_2TRANS | \
260 EBC_BXAP_CSN_ENCODE(0) | \
261 EBC_BXAP_OEN_ENCODE(0) | \
262 EBC_BXAP_WBN_ENCODE(0) | \
263 EBC_BXAP_WBF_ENCODE(0) | \
264 EBC_BXAP_TH_ENCODE(0) | \
265 EBC_BXAP_RE_DISABLED | \
266 EBC_BXAP_SOR_DELAYED | \
267 EBC_BXAP_BEM_WRITEONLY | \
268 EBC_BXAP_PEN_DISABLED)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200269#define CONFIG_SYS_EBC_PB0CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | \
Stefan Roese4745aca2007-02-20 10:57:08 +0100270 EBC_BXCR_BS_16MB | \
271 EBC_BXCR_BU_RW | \
272 EBC_BXCR_BW_16BIT)
273
274/* Memory Bank 1 (Xilinx System ACE controller) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200275#define CONFIG_SYS_EBC_PB1AP (EBC_BXAP_BME_DISABLED | \
Stefan Roesed2168622007-04-19 09:53:52 +0200276 EBC_BXAP_TWT_ENCODE(4) | \
277 EBC_BXAP_BCE_DISABLE | \
278 EBC_BXAP_BCT_2TRANS | \
279 EBC_BXAP_CSN_ENCODE(0) | \
280 EBC_BXAP_OEN_ENCODE(0) | \
281 EBC_BXAP_WBN_ENCODE(0) | \
282 EBC_BXAP_WBF_ENCODE(0) | \
283 EBC_BXAP_TH_ENCODE(0) | \
284 EBC_BXAP_RE_DISABLED | \
285 EBC_BXAP_SOR_NONDELAYED | \
286 EBC_BXAP_BEM_WRITEONLY | \
287 EBC_BXAP_PEN_DISABLED)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200288#define CONFIG_SYS_EBC_PB1CR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_ACE_BASE) | \
Stefan Roese4745aca2007-02-20 10:57:08 +0100289 EBC_BXCR_BS_1MB | \
290 EBC_BXCR_BU_RW | \
291 EBC_BXCR_BW_16BIT)
292
293/*-------------------------------------------------------------------------
294 * Initialize EBC CONFIG -
295 * Keep the Default value, but the bit PDT which has to be set to 1 ?TBC
296 * default value : 0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000
297 *-------------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200298#define CONFIG_SYS_EBC_CFG (EBC_CFG_LE_UNLOCK | \
Stefan Roese4745aca2007-02-20 10:57:08 +0100299 EBC_CFG_PTD_ENABLE | \
300 EBC_CFG_RTC_16PERCLK | \
301 EBC_CFG_ATC_PREVIOUS | \
302 EBC_CFG_DTC_PREVIOUS | \
303 EBC_CFG_CTC_PREVIOUS | \
304 EBC_CFG_OEO_PREVIOUS | \
305 EBC_CFG_EMC_DEFAULT | \
306 EBC_CFG_PME_DISABLE | \
307 EBC_CFG_PR_16)
308
Stefan Roeseba58e4c2007-03-01 21:11:36 +0100309/*-----------------------------------------------------------------------
310 * GPIO Setup
311 *----------------------------------------------------------------------*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200312#define CONFIG_SYS_GPIO_PCIE_PRESENT0 17
313#define CONFIG_SYS_GPIO_PCIE_PRESENT1 21
314#define CONFIG_SYS_GPIO_PCIE_PRESENT2 23
315#define CONFIG_SYS_GPIO_RS232_FORCEOFF 30
Stefan Roeseba58e4c2007-03-01 21:11:36 +0100316
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200317#define CONFIG_SYS_PFC0 (GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT0) | \
318 GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT1) | \
319 GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT2) | \
320 GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF))
321#define CONFIG_SYS_GPIO_OR GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF)
322#define CONFIG_SYS_GPIO_TCR GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF)
323#define CONFIG_SYS_GPIO_ODR 0
Stefan Roeseba58e4c2007-03-01 21:11:36 +0100324
Stefan Roese4745aca2007-02-20 10:57:08 +0100325#endif /* __CONFIG_H */