blob: edf65434430bca65e41f098eadd57aa750268b97 [file] [log] [blame]
Sanjeev Premi39708842011-10-25 06:11:30 +00001/*
2 * Common configuration settings for the TI OMAP3 EVM board.
3 *
4 * Copyright (C) 2006-2011 Texas Instruments Incorporated - http://www.ti.com/
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Sanjeev Premi39708842011-10-25 06:11:30 +00007 */
8
9#ifndef __OMAP3_EVM_COMMON_H
10#define __OMAP3_EVM_COMMON_H
11
12/*
13 * High level configuration options
14 */
15#define CONFIG_OMAP /* This is TI OMAP core */
16#define CONFIG_OMAP34XX /* belonging to 34XX family */
Marek Vasut308252a2012-07-21 05:02:23 +000017#define CONFIG_OMAP_GPIO
Lokesh Vutla806d2792013-07-30 11:36:30 +053018#define CONFIG_OMAP_COMMON
Sanjeev Premi39708842011-10-25 06:11:30 +000019
20#define CONFIG_SDRC /* The chip has SDRC controller */
21
22#define CONFIG_OMAP3_EVM /* This is a OMAP3 EVM */
Sanjeev Premi39708842011-10-25 06:11:30 +000023#define CONFIG_TWL4030_POWER /* with TWL4030 PMIC */
24
Sanjeev Premi39708842011-10-25 06:11:30 +000025/*
26 * Clock related definitions
27 */
28#define V_OSCK 26000000 /* Clock output from T2 */
29#define V_SCLK (V_OSCK >> 1)
30
31/*
32 * OMAP3 has 12 GP timers, they can be driven by the system clock
33 * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
34 * This rate is divided by a local divisor.
35 */
36#define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
37#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
38#define CONFIG_SYS_HZ 1000
39
40/* Size of environment - 128KB */
41#define CONFIG_ENV_SIZE (128 << 10)
42
43/* Size of malloc pool */
44#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
45
46/*
Sanjeev Premi39708842011-10-25 06:11:30 +000047 * Physical Memory Map
48 * Note 1: CS1 may or may not be populated
49 * Note 2: SDRAM size is expected to be at least 32MB
50 */
51#define CONFIG_NR_DRAM_BANKS 2
52#define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
Sanjeev Premi39708842011-10-25 06:11:30 +000053#define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
54
Sanjeev Premi39708842011-10-25 06:11:30 +000055/* Limits for memtest */
56#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0)
57#define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
58 0x01F00000) /* 31MB */
59
60/* Default load address */
61#define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0)
62
63/* -----------------------------------------------------------------------------
64 * Hardware drivers
65 * -----------------------------------------------------------------------------
66 */
67
68/*
69 * NS16550 Configuration
70 */
71#define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
72
73#define CONFIG_SYS_NS16550
74#define CONFIG_SYS_NS16550_SERIAL
75#define CONFIG_SYS_NS16550_REG_SIZE (-4)
76#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
77
78/*
79 * select serial console configuration
80 */
81#define CONFIG_CONS_INDEX 1
82#define CONFIG_SERIAL1 1 /* UART1 on OMAP3 EVM */
83#define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1
84#define CONFIG_BAUDRATE 115200
85#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
86 115200}
87
88/*
89 * I2C
90 */
91#define CONFIG_HARD_I2C
92#define CONFIG_DRIVER_OMAP34XX_I2C
93
94#define CONFIG_SYS_I2C_SPEED 100000
95#define CONFIG_SYS_I2C_SLAVE 1
Sanjeev Premi39708842011-10-25 06:11:30 +000096
97/*
98 * PISMO support
99 */
100#define PISMO1_NAND_SIZE GPMC_SIZE_128M
101#define PISMO1_ONEN_SIZE GPMC_SIZE_128M
102
103/* Monitor at start of flash - Reserve 2 sectors */
104#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
105
106#define CONFIG_SYS_MONITOR_LEN (256 << 10)
107
108/* Start location & size of environment */
109#define ONENAND_ENV_OFFSET 0x260000
110#define SMNAND_ENV_OFFSET 0x260000
111
112#define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB */
113
114/*
115 * NAND
116 */
117/* Physical address to access NAND */
118#define CONFIG_SYS_NAND_ADDR NAND_BASE
119
120/* Physical address to access NAND at CS0 */
121#define CONFIG_SYS_NAND_BASE NAND_BASE
122
123/* Max number of NAND devices */
124#define CONFIG_SYS_MAX_NAND_DEVICE 1
125
126/* Timeout values (in ticks) */
127#define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
128#define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
129
130/* Flash banks JFFS2 should use */
131#define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
132 CONFIG_SYS_MAX_NAND_DEVICE)
133
134#define CONFIG_SYS_JFFS2_MEM_NAND
135#define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
136#define CONFIG_SYS_JFFS2_NUM_BANKS 1
137
138#define CONFIG_JFFS2_NAND
139/* nand device jffs2 lives on */
140#define CONFIG_JFFS2_DEV "nand0"
141/* Start of jffs2 partition */
142#define CONFIG_JFFS2_PART_OFFSET 0x680000
143/* Size of jffs2 partition */
144#define CONFIG_JFFS2_PART_SIZE 0xf980000
145
146/*
147 * USB
148 */
149#ifdef CONFIG_USB_OMAP3
150
151#ifdef CONFIG_MUSB_HCD
152#define CONFIG_CMD_USB
153
154#define CONFIG_USB_STORAGE
155#define CONGIG_CMD_STORAGE
156#define CONFIG_CMD_FAT
157
158#ifdef CONFIG_USB_KEYBOARD
159#define CONFIG_SYS_USB_EVENT_POLL
160#define CONFIG_PREBOOT "usb start"
161#endif /* CONFIG_USB_KEYBOARD */
162
163#endif /* CONFIG_MUSB_HCD */
164
165#ifdef CONFIG_MUSB_UDC
166/* USB device configuration */
167#define CONFIG_USB_DEVICE
168#define CONFIG_USB_TTY
169#define CONFIG_SYS_CONSOLE_IS_IN_ENV
170
171/* Change these to suit your needs */
172#define CONFIG_USBD_VENDORID 0x0451
173#define CONFIG_USBD_PRODUCTID 0x5678
174#define CONFIG_USBD_MANUFACTURER "Texas Instruments"
175#define CONFIG_USBD_PRODUCT_NAME "EVM"
176#endif /* CONFIG_MUSB_UDC */
177
178#endif /* CONFIG_USB_OMAP3 */
179
180/* ----------------------------------------------------------------------------
181 * U-boot features
182 * ----------------------------------------------------------------------------
183 */
184#define CONFIG_SYS_PROMPT "OMAP3_EVM # "
Sanjeev Premi39708842011-10-25 06:11:30 +0000185#define CONFIG_SYS_MAXARGS 16 /* max args for a command */
186
187#define CONFIG_MISC_INIT_R
188
189#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
190#define CONFIG_SETUP_MEMORY_TAGS
191#define CONFIG_INITRD_TAG
192#define CONFIG_REVISION_TAG
193
194/* Size of Console IO buffer */
195#define CONFIG_SYS_CBSIZE 512
196
197/* Size of print buffer */
198#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
199 sizeof(CONFIG_SYS_PROMPT) + 16)
200
201/* Size of bootarg buffer */
202#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
203
204#define CONFIG_BOOTFILE "uImage"
205
206/*
207 * NAND / OneNAND
208 */
209#if defined(CONFIG_CMD_NAND)
210#define CONFIG_SYS_FLASH_BASE PISMO1_NAND_BASE
211
212#define CONFIG_NAND_OMAP_GPMC
213#define GPMC_NAND_ECC_LP_x16_LAYOUT
Sanjeev Premi39708842011-10-25 06:11:30 +0000214#define CONFIG_ENV_OFFSET SMNAND_ENV_OFFSET
215#elif defined(CONFIG_CMD_ONENAND)
216#define CONFIG_SYS_FLASH_BASE PISMO1_ONEN_BASE
217#define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
Sanjeev Premiedc633e2011-10-25 06:11:33 +0000218#endif
Sanjeev Premi39708842011-10-25 06:11:30 +0000219
Sanjeev Premiedc633e2011-10-25 06:11:33 +0000220#if !defined(CONFIG_ENV_IS_NOWHERE)
221#if defined(CONFIG_CMD_NAND)
222#define CONFIG_ENV_IS_IN_NAND
223#elif defined(CONFIG_CMD_ONENAND)
Sanjeev Premi39708842011-10-25 06:11:30 +0000224#define CONFIG_ENV_IS_IN_ONENAND
225#define CONFIG_ENV_OFFSET ONENAND_ENV_OFFSET
226#endif
Sanjeev Premiedc633e2011-10-25 06:11:33 +0000227#endif /* CONFIG_ENV_IS_NOWHERE */
Sanjeev Premi39708842011-10-25 06:11:30 +0000228
229#define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET
230
231#if defined(CONFIG_CMD_NET)
232
233/* Ethernet (SMSC9115 from SMSC9118 family) */
Sanjeev Premi39708842011-10-25 06:11:30 +0000234#define CONFIG_SMC911X
235#define CONFIG_SMC911X_32_BIT
236#define CONFIG_SMC911X_BASE 0x2C000000
237
238/* BOOTP fields */
239#define CONFIG_BOOTP_SUBNETMASK 0x00000001
240#define CONFIG_BOOTP_GATEWAY 0x00000002
241#define CONFIG_BOOTP_HOSTNAME 0x00000004
242#define CONFIG_BOOTP_BOOTPATH 0x00000010
243
244#endif /* CONFIG_CMD_NET */
245
246/* Support for relocation */
247#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
248#define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
249#define CONFIG_SYS_INIT_RAM_SIZE 0x800
250#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
251 CONFIG_SYS_INIT_RAM_SIZE - \
252 GENERATED_GBL_DATA_SIZE)
253
254/* -----------------------------------------------------------------------------
255 * Board specific
256 * -----------------------------------------------------------------------------
257 */
258#define CONFIG_SYS_NO_FLASH
259
260/* Uncomment to define the board revision statically */
261/* #define CONFIG_STATIC_BOARD_REV OMAP3EVM_BOARD_GEN_2 */
262
Aneesh V8e408522011-11-21 23:38:59 +0000263#define CONFIG_SYS_CACHELINE_SIZE 64
264
Tom Rini673283f2011-11-18 12:48:09 +0000265/* Defines for SPL */
266#define CONFIG_SPL
Tom Rini47f7bca2012-08-13 12:03:19 -0700267#define CONFIG_SPL_FRAMEWORK
Tom Rini673283f2011-11-18 12:48:09 +0000268#define CONFIG_SPL_TEXT_BASE 0x40200800
Tom Rinie0820cc2012-05-08 07:29:31 +0000269#define CONFIG_SPL_MAX_SIZE (54 * 1024) /* 8 KB for stack */
Tom Rini673283f2011-11-18 12:48:09 +0000270#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
271
272#define CONFIG_SPL_BSS_START_ADDR 0x80000000
273#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
274
Tom Rini49175c42012-05-08 07:29:32 +0000275#define CONFIG_SPL_BOARD_INIT
Tom Rini673283f2011-11-18 12:48:09 +0000276#define CONFIG_SPL_LIBCOMMON_SUPPORT
277#define CONFIG_SPL_LIBDISK_SUPPORT
278#define CONFIG_SPL_I2C_SUPPORT
279#define CONFIG_SPL_LIBGENERIC_SUPPORT
280#define CONFIG_SPL_SERIAL_SUPPORT
281#define CONFIG_SPL_POWER_SUPPORT
282#define CONFIG_SPL_OMAP3_ID_NAND
283#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds"
284
285/*
286 * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
287 * 64 bytes before this address should be set aside for u-boot.img's
288 * header. That is 0x800FFFC0--0x80100000 should not be used for any
289 * other needs.
290 */
291#define CONFIG_SYS_TEXT_BASE 0x80100000
292#define CONFIG_SYS_SPL_MALLOC_START 0x80208000
293#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
294
Sanjeev Premi39708842011-10-25 06:11:30 +0000295#endif /* __OMAP3_EVM_COMMON_H */