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Lei Wenaf62a552011-06-28 21:50:06 +00001/*
2 * Copyright 2011, Marvell Semiconductor Inc.
3 * Lei Wen <leiwen@marvell.com>
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Lei Wenaf62a552011-06-28 21:50:06 +00006 *
7 * Back ported to the 8xx platform (from the 8260 platform) by
8 * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
9 */
10#ifndef __SDHCI_HW_H
11#define __SDHCI_HW_H
12
13#include <asm/io.h>
Lei Wen6cf1b172011-10-08 04:14:56 +000014#include <mmc.h>
15
Lei Wenaf62a552011-06-28 21:50:06 +000016/*
17 * Controller registers
18 */
19
20#define SDHCI_DMA_ADDRESS 0x00
21
22#define SDHCI_BLOCK_SIZE 0x04
23#define SDHCI_MAKE_BLKSZ(dma, blksz) (((dma & 0x7) << 12) | (blksz & 0xFFF))
24
25#define SDHCI_BLOCK_COUNT 0x06
26
27#define SDHCI_ARGUMENT 0x08
28
29#define SDHCI_TRANSFER_MODE 0x0C
30#define SDHCI_TRNS_DMA 0x01
31#define SDHCI_TRNS_BLK_CNT_EN 0x02
32#define SDHCI_TRNS_ACMD12 0x04
33#define SDHCI_TRNS_READ 0x10
34#define SDHCI_TRNS_MULTI 0x20
35
36#define SDHCI_COMMAND 0x0E
37#define SDHCI_CMD_RESP_MASK 0x03
38#define SDHCI_CMD_CRC 0x08
39#define SDHCI_CMD_INDEX 0x10
40#define SDHCI_CMD_DATA 0x20
41#define SDHCI_CMD_ABORTCMD 0xC0
42
43#define SDHCI_CMD_RESP_NONE 0x00
44#define SDHCI_CMD_RESP_LONG 0x01
45#define SDHCI_CMD_RESP_SHORT 0x02
46#define SDHCI_CMD_RESP_SHORT_BUSY 0x03
47
48#define SDHCI_MAKE_CMD(c, f) (((c & 0xff) << 8) | (f & 0xff))
49#define SDHCI_GET_CMD(c) ((c>>8) & 0x3f)
50
51#define SDHCI_RESPONSE 0x10
52
53#define SDHCI_BUFFER 0x20
54
55#define SDHCI_PRESENT_STATE 0x24
56#define SDHCI_CMD_INHIBIT 0x00000001
57#define SDHCI_DATA_INHIBIT 0x00000002
58#define SDHCI_DOING_WRITE 0x00000100
59#define SDHCI_DOING_READ 0x00000200
60#define SDHCI_SPACE_AVAILABLE 0x00000400
61#define SDHCI_DATA_AVAILABLE 0x00000800
62#define SDHCI_CARD_PRESENT 0x00010000
Joe Hershberger470dcc72012-08-17 10:18:55 +000063#define SDHCI_CARD_STATE_STABLE 0x00020000
64#define SDHCI_CARD_DETECT_PIN_LEVEL 0x00040000
Lei Wenaf62a552011-06-28 21:50:06 +000065#define SDHCI_WRITE_PROTECT 0x00080000
66
67#define SDHCI_HOST_CONTROL 0x28
68#define SDHCI_CTRL_LED 0x01
69#define SDHCI_CTRL_4BITBUS 0x02
70#define SDHCI_CTRL_HISPD 0x04
71#define SDHCI_CTRL_DMA_MASK 0x18
72#define SDHCI_CTRL_SDMA 0x00
73#define SDHCI_CTRL_ADMA1 0x08
74#define SDHCI_CTRL_ADMA32 0x10
75#define SDHCI_CTRL_ADMA64 0x18
Joe Hershberger470dcc72012-08-17 10:18:55 +000076#define SDHCI_CTRL_8BITBUS 0x20
77#define SDHCI_CTRL_CD_TEST_INS 0x40
78#define SDHCI_CTRL_CD_TEST 0x80
Lei Wenaf62a552011-06-28 21:50:06 +000079
80#define SDHCI_POWER_CONTROL 0x29
81#define SDHCI_POWER_ON 0x01
82#define SDHCI_POWER_180 0x0A
83#define SDHCI_POWER_300 0x0C
84#define SDHCI_POWER_330 0x0E
85
86#define SDHCI_BLOCK_GAP_CONTROL 0x2A
87
88#define SDHCI_WAKE_UP_CONTROL 0x2B
89#define SDHCI_WAKE_ON_INT 0x01
90#define SDHCI_WAKE_ON_INSERT 0x02
91#define SDHCI_WAKE_ON_REMOVE 0x04
92
93#define SDHCI_CLOCK_CONTROL 0x2C
94#define SDHCI_DIVIDER_SHIFT 8
95#define SDHCI_DIVIDER_HI_SHIFT 6
96#define SDHCI_DIV_MASK 0xFF
97#define SDHCI_DIV_MASK_LEN 8
98#define SDHCI_DIV_HI_MASK 0x300
99#define SDHCI_CLOCK_CARD_EN 0x0004
100#define SDHCI_CLOCK_INT_STABLE 0x0002
101#define SDHCI_CLOCK_INT_EN 0x0001
102
103#define SDHCI_TIMEOUT_CONTROL 0x2E
104
105#define SDHCI_SOFTWARE_RESET 0x2F
106#define SDHCI_RESET_ALL 0x01
107#define SDHCI_RESET_CMD 0x02
108#define SDHCI_RESET_DATA 0x04
109
110#define SDHCI_INT_STATUS 0x30
111#define SDHCI_INT_ENABLE 0x34
112#define SDHCI_SIGNAL_ENABLE 0x38
113#define SDHCI_INT_RESPONSE 0x00000001
114#define SDHCI_INT_DATA_END 0x00000002
115#define SDHCI_INT_DMA_END 0x00000008
116#define SDHCI_INT_SPACE_AVAIL 0x00000010
117#define SDHCI_INT_DATA_AVAIL 0x00000020
118#define SDHCI_INT_CARD_INSERT 0x00000040
119#define SDHCI_INT_CARD_REMOVE 0x00000080
120#define SDHCI_INT_CARD_INT 0x00000100
121#define SDHCI_INT_ERROR 0x00008000
122#define SDHCI_INT_TIMEOUT 0x00010000
123#define SDHCI_INT_CRC 0x00020000
124#define SDHCI_INT_END_BIT 0x00040000
125#define SDHCI_INT_INDEX 0x00080000
126#define SDHCI_INT_DATA_TIMEOUT 0x00100000
127#define SDHCI_INT_DATA_CRC 0x00200000
128#define SDHCI_INT_DATA_END_BIT 0x00400000
129#define SDHCI_INT_BUS_POWER 0x00800000
130#define SDHCI_INT_ACMD12ERR 0x01000000
131#define SDHCI_INT_ADMA_ERROR 0x02000000
132
133#define SDHCI_INT_NORMAL_MASK 0x00007FFF
134#define SDHCI_INT_ERROR_MASK 0xFFFF8000
135
136#define SDHCI_INT_CMD_MASK (SDHCI_INT_RESPONSE | SDHCI_INT_TIMEOUT | \
137 SDHCI_INT_CRC | SDHCI_INT_END_BIT | SDHCI_INT_INDEX)
138#define SDHCI_INT_DATA_MASK (SDHCI_INT_DATA_END | SDHCI_INT_DMA_END | \
139 SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL | \
140 SDHCI_INT_DATA_TIMEOUT | SDHCI_INT_DATA_CRC | \
141 SDHCI_INT_DATA_END_BIT | SDHCI_INT_ADMA_ERROR)
142#define SDHCI_INT_ALL_MASK ((unsigned int)-1)
143
144#define SDHCI_ACMD12_ERR 0x3C
145
146/* 3E-3F reserved */
147
148#define SDHCI_CAPABILITIES 0x40
149#define SDHCI_TIMEOUT_CLK_MASK 0x0000003F
150#define SDHCI_TIMEOUT_CLK_SHIFT 0
151#define SDHCI_TIMEOUT_CLK_UNIT 0x00000080
152#define SDHCI_CLOCK_BASE_MASK 0x00003F00
153#define SDHCI_CLOCK_V3_BASE_MASK 0x0000FF00
154#define SDHCI_CLOCK_BASE_SHIFT 8
155#define SDHCI_MAX_BLOCK_MASK 0x00030000
156#define SDHCI_MAX_BLOCK_SHIFT 16
157#define SDHCI_CAN_DO_8BIT 0x00040000
158#define SDHCI_CAN_DO_ADMA2 0x00080000
159#define SDHCI_CAN_DO_ADMA1 0x00100000
160#define SDHCI_CAN_DO_HISPD 0x00200000
161#define SDHCI_CAN_DO_SDMA 0x00400000
162#define SDHCI_CAN_VDD_330 0x01000000
163#define SDHCI_CAN_VDD_300 0x02000000
164#define SDHCI_CAN_VDD_180 0x04000000
165#define SDHCI_CAN_64BIT 0x10000000
166
167#define SDHCI_CAPABILITIES_1 0x44
168
169#define SDHCI_MAX_CURRENT 0x48
170
171/* 4C-4F reserved for more max current */
172
173#define SDHCI_SET_ACMD12_ERROR 0x50
174#define SDHCI_SET_INT_ERROR 0x52
175
176#define SDHCI_ADMA_ERROR 0x54
177
178/* 55-57 reserved */
179
180#define SDHCI_ADMA_ADDRESS 0x58
181
182/* 60-FB reserved */
183
184#define SDHCI_SLOT_INT_STATUS 0xFC
185
186#define SDHCI_HOST_VERSION 0xFE
187#define SDHCI_VENDOR_VER_MASK 0xFF00
188#define SDHCI_VENDOR_VER_SHIFT 8
189#define SDHCI_SPEC_VER_MASK 0x00FF
190#define SDHCI_SPEC_VER_SHIFT 0
191#define SDHCI_SPEC_100 0
192#define SDHCI_SPEC_200 1
193#define SDHCI_SPEC_300 2
194
Jaehoon Chung113e5df2013-07-19 17:44:49 +0900195#define SDHCI_GET_VERSION(x) (x->version & SDHCI_SPEC_VER_MASK)
196
Lei Wenaf62a552011-06-28 21:50:06 +0000197/*
198 * End of controller registers.
199 */
200
201#define SDHCI_MAX_DIV_SPEC_200 256
202#define SDHCI_MAX_DIV_SPEC_300 2046
203
204/*
205 * quirks
206 */
207#define SDHCI_QUIRK_32BIT_DMA_ADDR (1 << 0)
Ajay Bhargav5af9a562011-11-13 23:43:12 +0000208#define SDHCI_QUIRK_REG32_RW (1 << 1)
Jaehoon Chung3a638322012-04-23 02:36:25 +0000209#define SDHCI_QUIRK_BROKEN_R1B (1 << 2)
Jaehoon Chung236bfec2012-04-23 02:36:26 +0000210#define SDHCI_QUIRK_NO_HISPD_BIT (1 << 3)
211#define SDHCI_QUIRK_BROKEN_VOLTAGE (1 << 4)
Joe Hershberger470dcc72012-08-17 10:18:55 +0000212#define SDHCI_QUIRK_NO_CD (1 << 5)
Tushar Behera13243f22012-09-20 20:31:57 +0000213#define SDHCI_QUIRK_WAIT_SEND_CMD (1 << 6)
Mela Custodio688c2d12012-11-03 17:40:16 +0000214#define SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER (1 << 7)
Jaehoon Chung113e5df2013-07-19 17:44:49 +0900215#define SDHCI_QUIRK_USE_WIDE8 (1 << 8)
Lei Wenaf62a552011-06-28 21:50:06 +0000216
Lei Wen0d2f15f2011-10-08 04:14:55 +0000217/* to make gcc happy */
218struct sdhci_host;
219
Lei Wenaf62a552011-06-28 21:50:06 +0000220/*
221 * Host SDMA buffer boundary. Valid values from 4K to 512K in powers of 2.
222 */
223#define SDHCI_DEFAULT_BOUNDARY_SIZE (512 * 1024)
224#define SDHCI_DEFAULT_BOUNDARY_ARG (7)
225struct sdhci_ops {
226#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
227 u32 (*read_l)(struct sdhci_host *host, int reg);
228 u16 (*read_w)(struct sdhci_host *host, int reg);
229 u8 (*read_b)(struct sdhci_host *host, int reg);
230 void (*write_l)(struct sdhci_host *host, u32 val, int reg);
231 void (*write_w)(struct sdhci_host *host, u16 val, int reg);
232 void (*write_b)(struct sdhci_host *host, u8 val, int reg);
233#endif
234};
235
236struct sdhci_host {
237 char *name;
238 void *ioaddr;
239 unsigned int quirks;
Jaehoon Chung236bfec2012-04-23 02:36:26 +0000240 unsigned int host_caps;
Lei Wenaf62a552011-06-28 21:50:06 +0000241 unsigned int version;
242 unsigned int clock;
Lei Wen6cf1b172011-10-08 04:14:56 +0000243 struct mmc *mmc;
Lei Wenaf62a552011-06-28 21:50:06 +0000244 const struct sdhci_ops *ops;
Jaehoon Chungb09ed6e2012-08-30 16:24:11 +0000245 int index;
Jaehoon Chung236bfec2012-04-23 02:36:26 +0000246
247 void (*set_control_reg)(struct sdhci_host *host);
Jaehoon Chungb09ed6e2012-08-30 16:24:11 +0000248 void (*set_clock)(int dev_index, unsigned int div);
Jaehoon Chung236bfec2012-04-23 02:36:26 +0000249 uint voltages;
Lei Wenaf62a552011-06-28 21:50:06 +0000250};
251
252#ifdef CONFIG_MMC_SDHCI_IO_ACCESSORS
253
254static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
255{
256 if (unlikely(host->ops->write_l))
257 host->ops->write_l(host, val, reg);
258 else
259 writel(val, host->ioaddr + reg);
260}
261
262static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
263{
264 if (unlikely(host->ops->write_w))
265 host->ops->write_w(host, val, reg);
266 else
267 writew(val, host->ioaddr + reg);
268}
269
270static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
271{
272 if (unlikely(host->ops->write_b))
273 host->ops->write_b(host, val, reg);
274 else
275 writeb(val, host->ioaddr + reg);
276}
277
278static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
279{
280 if (unlikely(host->ops->read_l))
281 return host->ops->read_l(host, reg);
282 else
283 return readl(host->ioaddr + reg);
284}
285
286static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
287{
288 if (unlikely(host->ops->read_w))
289 return host->ops->read_w(host, reg);
290 else
291 return readw(host->ioaddr + reg);
292}
293
294static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
295{
296 if (unlikely(host->ops->read_b))
297 return host->ops->read_b(host, reg);
298 else
299 return readb(host->ioaddr + reg);
300}
301
302#else
303
304static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg)
305{
306 writel(val, host->ioaddr + reg);
307}
308
309static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg)
310{
311 writew(val, host->ioaddr + reg);
312}
313
314static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg)
315{
316 writeb(val, host->ioaddr + reg);
317}
318static inline u32 sdhci_readl(struct sdhci_host *host, int reg)
319{
320 return readl(host->ioaddr + reg);
321}
322
323static inline u16 sdhci_readw(struct sdhci_host *host, int reg)
324{
325 return readw(host->ioaddr + reg);
326}
327
328static inline u8 sdhci_readb(struct sdhci_host *host, int reg)
329{
330 return readb(host->ioaddr + reg);
331}
332#endif
333
334int add_sdhci(struct sdhci_host *host, u32 max_clk, u32 min_clk);
335#endif /* __SDHCI_HW_H */