blob: 199264ac8e7fc9c83ff40e6b0b573f2d73c9cf8c [file] [log] [blame]
Peter Crosthwaite9757b652014-08-28 21:16:39 +10001/*
2 * Digilent ZYBO board DTS
3 *
Michal Simek999667c2015-07-22 11:12:10 +02004 * Copyright (C) 2011 - 2015 Xilinx
5 * Copyright (C) 2012 National Instruments Corp.
Peter Crosthwaite9757b652014-08-28 21:16:39 +10006 *
7 * SPDX-License-Identifier: GPL-2.0+
8 */
9/dts-v1/;
10#include "zynq-7000.dtsi"
11
12/ {
Michal Simek999667c2015-07-22 11:12:10 +020013 model = "Zynq ZYBO Development Board";
14 compatible = "digilent,zynq-zybo", "xlnx,zynq-7000";
Peter Crosthwaite9757b652014-08-28 21:16:39 +100015
16 aliases {
Michal Simek999667c2015-07-22 11:12:10 +020017 ethernet0 = &gem0;
Peter Crosthwaite9757b652014-08-28 21:16:39 +100018 serial0 = &uart1;
Michal Simek86472192015-12-08 11:56:23 +010019 mmc0 = &sdhci0;
Peter Crosthwaite9757b652014-08-28 21:16:39 +100020 };
21
22 memory {
23 device_type = "memory";
Michal Simek999667c2015-07-22 11:12:10 +020024 reg = <0x0 0x20000000>;
Peter Crosthwaite9757b652014-08-28 21:16:39 +100025 };
Michal Simek999667c2015-07-22 11:12:10 +020026
27 chosen {
28 bootargs = "earlyprintk";
29 stdout-path = "serial0:115200n8";
30 };
31
32};
33
34&clkc {
35 ps-clk-frequency = <50000000>;
36};
37
38&gem0 {
39 status = "okay";
40 phy-mode = "rgmii-id";
41 phy-handle = <&ethernet_phy>;
42
43 ethernet_phy: ethernet-phy@0 {
44 reg = <0>;
45 };
46};
47
48&sdhci0 {
Michal Simek86472192015-12-08 11:56:23 +010049 u-boot,dm-pre-reloc;
Michal Simek999667c2015-07-22 11:12:10 +020050 status = "okay";
51};
52
53&uart1 {
Simon Glass035c6b22015-10-17 19:41:24 -060054 u-boot,dm-pre-reloc;
Michal Simek999667c2015-07-22 11:12:10 +020055 status = "okay";
Peter Crosthwaite9757b652014-08-28 21:16:39 +100056};