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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 864aa6a6a466fcb92bf32b1d7dba79cd709b52c9 / . / include / asm-blackfin / arch-common / def_LPBlackfin.h
blob: ebeeea0321411d314cea4f9228ad135bac048678 [file] [log] [blame]
Wolfgang Denk6cb142f2006-03-12 02:12:27 +0100[diff] [blame]1/*
2 * def_LPBlackfin.h
3 *
4 * This file is subject to the terms and conditions of the GNU Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Non-GPL License also available as part of VisualDSP++
9 *
10 * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html
11 *
12 * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved
13 *
14 * This file under source code control, please send bugs or changes to:
15 * dsptools.support@analog.com
16 *
17 */
18
19/* LP Blackfin CORE REGISTER BIT & ADDRESS DEFINITIONS FOR ADSP-BF532 */
20
21#ifndef _DEF_LPBLACKFIN_H
22#define _DEF_LPBLACKFIN_H
23
Wolfgang Denk8e7b7032006-03-12 02:55:22 +0100[diff] [blame]24/*
Wolfgang Denk6cb142f2006-03-12 02:12:27 +0100[diff] [blame]25 * #if !defined(__ADSPLPBLACKFIN__)
26 * #warning def_LPBlackfin.h should only be included for 532 compatible chips.
27 * #endif
28 */
29
30#define MK_BMSK_( x ) (1<<x) /* Make a bit mask from a bit position */
31
32/*
33 * System Register Bits
34 */
35
36/*
37 * ASTAT register
38 */
39
40/* definitions of ASTAT bit positions */
41#define ASTAT_AZ_P 0x00000000 /* Result of last ALU0 or shifter operation is zero */
42#define ASTAT_AN_P 0x00000001 /* Result of last ALU0 or shifter operation is negative */
43#define ASTAT_CC_P 0x00000005 /* Condition Code, used for holding comparison results */
44#define ASTAT_AQ_P 0x00000006 /* Quotient Bit */
45#define ASTAT_RND_MOD_P 0x00000008 /* Rounding mode, set for biased, clear for unbiased */
46#define ASTAT_AC0_P 0x0000000C /* Result of last ALU0 operation generated a carry */
47#define ASTAT_AC0_COPY_P 0x00000002 /* Result of last ALU0 operation generated a carry */
48#define ASTAT_AC1_P 0x0000000D /* Result of last ALU1 operation generated a carry */
49#define ASTAT_AV0_P 0x00000010 /* Result of last ALU0 or MAC0 operation overflowed, sticky for MAC */
50#define ASTAT_AV0S_P 0x00000011 /* Sticky version of ASTAT_AV0 */
51#define ASTAT_AV1_P 0x00000012 /* Result of last MAC1 operation overflowed, sticky for MAC */
52#define ASTAT_AV1S_P 0x00000013 /* Sticky version of ASTAT_AV1 */
53#define ASTAT_V_P 0x00000018 /* Result of last ALU0 or MAC0 operation overflowed */
54#define ASTAT_V_COPY_P 0x00000003 /* Result of last ALU0 or MAC0 operation overflowed */
55#define ASTAT_VS_P 0x00000019 /* Sticky version of ASTAT_V */
56
57/* ** Masks */
58#define ASTAT_AZ MK_BMSK_(ASTAT_AZ_P) /* Result of last ALU0 or shifter operation is zero */
59#define ASTAT_AN MK_BMSK_(ASTAT_AN_P) /* Result of last ALU0 or shifter operation is negative */
60#define ASTAT_AC0 MK_BMSK_(ASTAT_AC0_P) /* Result of last ALU0 operation generated a carry */
61#define ASTAT_AC0_COPY MK_BMSK_(ASTAT_AC0_COPY_P) /* Result of last ALU0 operation generated a carry */
62#define ASTAT_AC1 MK_BMSK_(ASTAT_AC1_P) /* Result of last ALU0 operation generated a carry */
63#define ASTAT_AV0 MK_BMSK_(ASTAT_AV0_P) /* Result of last ALU0 or MAC0 operation overflowed, sticky for MAC */
64#define ASTAT_AV1 MK_BMSK_(ASTAT_AV1_P) /* Result of last MAC1 operation overflowed, sticky for MAC */
65#define ASTAT_CC MK_BMSK_(ASTAT_CC_P) /* Condition Code, used for holding comparison results */
66#define ASTAT_AQ MK_BMSK_(ASTAT_AQ_P) /* Quotient Bit */
67#define ASTAT_RND_MOD MK_BMSK_(ASTAT_RND_MOD_P) /* Rounding mode, set for biased, clear for unbiased */
68#define ASTAT_V MK_BMSK_(ASTAT_V_P) /* Overflow Bit */
69#define ASTAT_V_COPY MK_BMSK_(ASTAT_V_COPY_P) /* Overflow Bit */
70
71/*
72 * SEQSTAT register
73 */
74
75/* ** Bit Positions */
76#define SEQSTAT_EXCAUSE0_P 0x00000000 /* Last exception cause bit 0 */
77#define SEQSTAT_EXCAUSE1_P 0x00000001 /* Last exception cause bit 1 */
78#define SEQSTAT_EXCAUSE2_P 0x00000002 /* Last exception cause bit 2 */
79#define SEQSTAT_EXCAUSE3_P 0x00000003 /* Last exception cause bit 3 */
80#define SEQSTAT_EXCAUSE4_P 0x00000004 /* Last exception cause bit 4 */
81#define SEQSTAT_EXCAUSE5_P 0x00000005 /* Last exception cause bit 5 */
82#define SEQSTAT_IDLE_REQ_P 0x0000000C /* Pending idle mode request, set by IDLE instruction */
83#define SEQSTAT_SFTRESET_P 0x0000000D /* Indicates whether the last reset was a software reset (=1) */
84#define SEQSTAT_HWERRCAUSE0_P 0x0000000E /* Last hw error cause bit 0 */
85#define SEQSTAT_HWERRCAUSE1_P 0x0000000F /* Last hw error cause bit 1 */
86#define SEQSTAT_HWERRCAUSE2_P 0x00000010 /* Last hw error cause bit 2 */
87#define SEQSTAT_HWERRCAUSE3_P 0x00000011 /* Last hw error cause bit 3 */
88#define SEQSTAT_HWERRCAUSE4_P 0x00000012 /* Last hw error cause bit 4 */
89#define SEQSTAT_HWERRCAUSE5_P 0x00000013 /* Last hw error cause bit 5 */
90#define SEQSTAT_HWERRCAUSE6_P 0x00000014 /* Last hw error cause bit 6 */
91#define SEQSTAT_HWERRCAUSE7_P 0x00000015 /* Last hw error cause bit 7 */
92
93/* ** Masks */
94/* Exception cause */
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800[diff] [blame]95#define SEQSTAT_EXCAUSE ( MK_BMSK_(SEQSTAT_EXCAUSE0_P ) | \
Wolfgang Denk6cb142f2006-03-12 02:12:27 +0100[diff] [blame]96 MK_BMSK_(SEQSTAT_EXCAUSE1_P ) | \
97 MK_BMSK_(SEQSTAT_EXCAUSE2_P ) | \
98 MK_BMSK_(SEQSTAT_EXCAUSE3_P ) | \
99 MK_BMSK_(SEQSTAT_EXCAUSE4_P ) | \
100 MK_BMSK_(SEQSTAT_EXCAUSE5_P ) | \
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800[diff] [blame]101 0 )
Wolfgang Denk6cb142f2006-03-12 02:12:27 +0100[diff] [blame]102
103/* Indicates whether the last reset was a software reset (=1) */
104#define SEQSTAT_SFTRESET MK_BMSK_(SEQSTAT_SFTRESET_P )
105
106/* Last hw error cause */
107#define SEQSTAT_HWERRCAUSE MK_BMSK_(SEQSTAT_HWERRCAUSE0_P ) | \
108 MK_BMSK_(SEQSTAT_HWERRCAUSE1_P ) | \
109 MK_BMSK_(SEQSTAT_HWERRCAUSE2_P ) | \
110 MK_BMSK_(SEQSTAT_HWERRCAUSE3_P ) | \
111 MK_BMSK_(SEQSTAT_HWERRCAUSE4_P ) | \
112 0
113
114/*
115 * SYSCFG register
116 */
117
118/* ** Bit Positions */
119#define SYSCFG_SSSTEP_P 0x00000000 /* Supervisor single step, when set it forces an exception for each instruction executed */
120#define SYSCFG_CCEN_P 0x00000001 /* Enable cycle counter (=1) */
121#define SYSCFG_SNEN_P 0x00000002 /* Self nesting Interrupt Enable */
122
123/* ** Masks */
124#define SYSCFG_SSSTEP MK_BMSK_(SYSCFG_SSSTEP_P) /* Supervisor single step, when set it forces an exception for each instruction executed */
125#define SYSCFG_CCEN MK_BMSK_(SYSCFG_CCEN_P) /* Enable cycle counter (=1) */
126#define SYSCFG_SNEN MK_BMSK_(SYSCFG_SNEN_P /* Self Nesting Interrupt Enable */
127
128/* Backward-compatibility for typos in prior releases */
129#define SYSCFG_SSSSTEP SYSCFG_SSSTEP
130#define SYSCFG_CCCEN SYSCFG_CCEN
131
132/*
133 * Core MMR Register Map
134 */
135
136/* Data Cache & SRAM Memory (0xFFE00000 - 0xFFE00404) */
137#define SRAM_BASE_ADDRESS 0xFFE00000 /* SRAM Base Address Register */
138#define DMEM_CONTROL 0xFFE00004 /* Data memory control */
139#define DCPLB_STATUS 0xFFE00008 /* Data Cache Programmable Look-Aside Buffer Status */
140#define DCPLB_FAULT_STATUS 0xFFE00008 /* "" (older define) */
141#define DCPLB_FAULT_ADDR 0xFFE0000C /* Data Cache Programmable Look-Aside Buffer Fault Address */
142#define DCPLB_ADDR0 0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */
143#define DCPLB_ADDR1 0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */
144#define DCPLB_ADDR2 0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */
145#define DCPLB_ADDR3 0xFFE0010C /* Data Cacheability Protection Lookaside Buffer 3 */
146#define DCPLB_ADDR4 0xFFE00110 /* Data Cacheability Protection Lookaside Buffer 4 */
147#define DCPLB_ADDR5 0xFFE00114 /* Data Cacheability Protection Lookaside Buffer 5 */
148#define DCPLB_ADDR6 0xFFE00118 /* Data Cacheability Protection Lookaside Buffer 6 */
149#define DCPLB_ADDR7 0xFFE0011C /* Data Cacheability Protection Lookaside Buffer 7 */
150#define DCPLB_ADDR8 0xFFE00120 /* Data Cacheability Protection Lookaside Buffer 8 */
151#define DCPLB_ADDR9 0xFFE00124 /* Data Cacheability Protection Lookaside Buffer 9 */
152#define DCPLB_ADDR10 0xFFE00128 /* Data Cacheability Protection Lookaside Buffer 10 */
153#define DCPLB_ADDR11 0xFFE0012C /* Data Cacheability Protection Lookaside Buffer 11 */
154#define DCPLB_ADDR12 0xFFE00130 /* Data Cacheability Protection Lookaside Buffer 12 */
155#define DCPLB_ADDR13 0xFFE00134 /* Data Cacheability Protection Lookaside Buffer 13 */
156#define DCPLB_ADDR14 0xFFE00138 /* Data Cacheability Protection Lookaside Buffer 14 */
157#define DCPLB_ADDR15 0xFFE0013C /* Data Cacheability Protection Lookaside Buffer 15 */
158#define DCPLB_DATA0 0xFFE00200 /* Data Cache 0 Status */
159#define DCPLB_DATA1 0xFFE00204 /* Data Cache 1 Status */
160#define DCPLB_DATA2 0xFFE00208 /* Data Cache 2 Status */
161#define DCPLB_DATA3 0xFFE0020C /* Data Cache 3 Status */
162#define DCPLB_DATA4 0xFFE00210 /* Data Cache 4 Status */
163#define DCPLB_DATA5 0xFFE00214 /* Data Cache 5 Status */
164#define DCPLB_DATA6 0xFFE00218 /* Data Cache 6 Status */
165#define DCPLB_DATA7 0xFFE0021C /* Data Cache 7 Status */
166#define DCPLB_DATA8 0xFFE00220 /* Data Cache 8 Status */
167#define DCPLB_DATA9 0xFFE00224 /* Data Cache 9 Status */
168#define DCPLB_DATA10 0xFFE00228 /* Data Cache 10 Status */
169#define DCPLB_DATA11 0xFFE0022C /* Data Cache 11 Status */
170#define DCPLB_DATA12 0xFFE00230 /* Data Cache 12 Status */
171#define DCPLB_DATA13 0xFFE00234 /* Data Cache 13 Status */
172#define DCPLB_DATA14 0xFFE00238 /* Data Cache 14 Status */
173#define DCPLB_DATA15 0xFFE0023C /* Data Cache 15 Status */
174#define DTEST_COMMAND 0xFFE00300 /* Data Test Command Register */
175#define DTEST_DATA0 0xFFE00400 /* Data Test Data Register */
176#define DTEST_DATA1 0xFFE00404 /* Data Test Data Register */
177
178/* Instruction Cache & SRAM Memory (0xFFE01004 - 0xFFE01404) */
179#define IMEM_CONTROL 0xFFE01004 /* Instruction Memory Control */
180#define ICPLB_STATUS 0xFFE01008 /* Instruction Cache miss status */
181#define CODE_FAULT_STATUS 0xFFE01008 /* "" (older define) */
182#define ICPLB_FAULT_ADDR 0xFFE0100C /* Instruction Cache miss address */
183#define CODE_FAULT_ADDR 0xFFE0100C /* "" (older define) */
184#define ICPLB_ADDR0 0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */
185#define ICPLB_ADDR1 0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */
186#define ICPLB_ADDR2 0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */
187#define ICPLB_ADDR3 0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */
188#define ICPLB_ADDR4 0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */
189#define ICPLB_ADDR5 0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */
190#define ICPLB_ADDR6 0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */
191#define ICPLB_ADDR7 0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */
192#define ICPLB_ADDR8 0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */
193#define ICPLB_ADDR9 0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */
194#define ICPLB_ADDR10 0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */
195#define ICPLB_ADDR11 0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */
196#define ICPLB_ADDR12 0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */
197#define ICPLB_ADDR13 0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */
198#define ICPLB_ADDR14 0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */
199#define ICPLB_ADDR15 0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */
200#define ICPLB_DATA0 0xFFE01200 /* Instruction Cache 0 Status */
201#define ICPLB_DATA1 0xFFE01204 /* Instruction Cache 1 Status */
202#define ICPLB_DATA2 0xFFE01208 /* Instruction Cache 2 Status */
203#define ICPLB_DATA3 0xFFE0120C /* Instruction Cache 3 Status */
204#define ICPLB_DATA4 0xFFE01210 /* Instruction Cache 4 Status */
205#define ICPLB_DATA5 0xFFE01214 /* Instruction Cache 5 Status */
206#define ICPLB_DATA6 0xFFE01218 /* Instruction Cache 6 Status */
207#define ICPLB_DATA7 0xFFE0121C /* Instruction Cache 7 Status */
208#define ICPLB_DATA8 0xFFE01220 /* Instruction Cache 8 Status */
209#define ICPLB_DATA9 0xFFE01224 /* Instruction Cache 9 Status */
210#define ICPLB_DATA10 0xFFE01228 /* Instruction Cache 10 Status */
211#define ICPLB_DATA11 0xFFE0122C /* Instruction Cache 11 Status */
212#define ICPLB_DATA12 0xFFE01230 /* Instruction Cache 12 Status */
213#define ICPLB_DATA13 0xFFE01234 /* Instruction Cache 13 Status */
214#define ICPLB_DATA14 0xFFE01238 /* Instruction Cache 14 Status */
215#define ICPLB_DATA15 0xFFE0123C /* Instruction Cache 15 Status */
216#define ITEST_COMMAND 0xFFE01300 /* Instruction Test Command Register */
217#define ITEST_DATA0 0xFFE01400 /* Instruction Test Data Register */
218#define ITEST_DATA1 0xFFE01404 /* Instruction Test Data Register */
219
220/* Event/Interrupt Controller Registers (0xFFE02000 - 0xFFE02110) */
221#define EVT0 0xFFE02000 /* Event Vector 0 ESR Address */
222#define EVT1 0xFFE02004 /* Event Vector 1 ESR Address */
223#define EVT2 0xFFE02008 /* Event Vector 2 ESR Address */
224#define EVT3 0xFFE0200C /* Event Vector 3 ESR Address */
225#define EVT4 0xFFE02010 /* Event Vector 4 ESR Address */
226#define EVT5 0xFFE02014 /* Event Vector 5 ESR Address */
227#define EVT6 0xFFE02018 /* Event Vector 6 ESR Address */
228#define EVT7 0xFFE0201C /* Event Vector 7 ESR Address */
229#define EVT8 0xFFE02020 /* Event Vector 8 ESR Address */
230#define EVT9 0xFFE02024 /* Event Vector 9 ESR Address */
231#define EVT10 0xFFE02028 /* Event Vector 10 ESR Address */
232#define EVT11 0xFFE0202C /* Event Vector 11 ESR Address */
233#define EVT12 0xFFE02030 /* Event Vector 12 ESR Address */
234#define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */
235#define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */
236#define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */
237#define IMASK 0xFFE02104 /* Interrupt Mask Register */
238#define IPEND 0xFFE02108 /* Interrupt Pending Register */
239#define ILAT 0xFFE0210C /* Interrupt Latch Register */
240#define IPRIO 0xFFE02110 /* Core Interrupt Priority Register */
241
242/* Core Timer Registers (0xFFE03000 - 0xFFE0300C) */
243#define TCNTL 0xFFE03000 /* Core Timer Control Register */
244#define TPERIOD 0xFFE03004 /* Core Timer Period Register */
245#define TSCALE 0xFFE03008 /* Core Timer Scale Register */
246#define TCOUNT 0xFFE0300C /* Core Timer Count Register */
247
248/* Debug/MP/Emulation Registers (0xFFE05000 - 0xFFE05008) */
249#define DSPID 0xFFE05000 /* DSP Processor ID Register for MP implementations */
250#define DBGSTAT 0xFFE05008 /* Debug Status Register */
251
252/* Trace Buffer Registers (0xFFE06000 - 0xFFE06100) */
253#define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */
254#define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */
255#define TBUF 0xFFE06100 /* Trace Buffer */
256
257/* Watchpoint Control Registers (0xFFE07000 - 0xFFE07200) */
258#define WPIACTL 0xFFE07000 /* Watchpoint Instruction Address Control Register */
259#define WPIA0 0xFFE07040 /* Watchpoint Instruction Address Register 0 */
260#define WPIA1 0xFFE07044 /* Watchpoint Instruction Address Register 1 */
261#define WPIA2 0xFFE07048 /* Watchpoint Instruction Address Register 2 */
262#define WPIA3 0xFFE0704C /* Watchpoint Instruction Address Register 3 */
263#define WPIA4 0xFFE07050 /* Watchpoint Instruction Address Register 4 */
264#define WPIA5 0xFFE07054 /* Watchpoint Instruction Address Register 5 */
265#define WPIACNT0 0xFFE07080 /* Watchpoint Instruction Address Count Register 0 */
266#define WPIACNT1 0xFFE07084 /* Watchpoint Instruction Address Count Register 1 */
267#define WPIACNT2 0xFFE07088 /* Watchpoint Instruction Address Count Register 2 */
268#define WPIACNT3 0xFFE0708C /* Watchpoint Instruction Address Count Register 3 */
269#define WPIACNT4 0xFFE07090 /* Watchpoint Instruction Address Count Register 4 */
270#define WPIACNT5 0xFFE07094 /* Watchpoint Instruction Address Count Register 5 */
271#define WPDACTL 0xFFE07100 /* Watchpoint Data Address Control Register */
272#define WPDA0 0xFFE07140 /* Watchpoint Data Address Register 0 */
273#define WPDA1 0xFFE07144 /* Watchpoint Data Address Register 1 */
274#define WPDACNT0 0xFFE07180 /* Watchpoint Data Address Count Value Register 0 */
275#define WPDACNT1 0xFFE07184 /* Watchpoint Data Address Count Value Register 1 */
276#define WPSTAT 0xFFE07200 /* Watchpoint Status Register */
277
278/* Performance Monitor Registers (0xFFE08000 - 0xFFE08104) */
279#define PFCTL 0xFFE08000 /* Performance Monitor Control Register */
280#define PFCNTR0 0xFFE08100 /* Performance Monitor Counter Register 0 */
281#define PFCNTR1 0xFFE08104 /* Performance Monitor Counter Register 1 */
282
283/*
284 * Core MMR Register Bits
285 */
286
287/*
288 * EVT registers (ILAT, IMASK, and IPEND).
289 */
290
291/* ** Bit Positions */
292#define EVT_EMU_P 0x00000000 /* Emulator interrupt bit position */
293#define EVT_RST_P 0x00000001 /* Reset interrupt bit position */
294#define EVT_NMI_P 0x00000002 /* Non Maskable interrupt bit position */
295#define EVT_EVX_P 0x00000003 /* Exception bit position */
296#define EVT_IRPTEN_P 0x00000004 /* Global interrupt enable bit position */
297#define EVT_IVHW_P 0x00000005 /* Hardware Error interrupt bit position */
298#define EVT_IVTMR_P 0x00000006 /* Timer interrupt bit position */
299#define EVT_IVG7_P 0x00000007 /* IVG7 interrupt bit position */
300#define EVT_IVG8_P 0x00000008 /* IVG8 interrupt bit position */
301#define EVT_IVG9_P 0x00000009 /* IVG9 interrupt bit position */
302#define EVT_IVG10_P 0x0000000a /* IVG10 interrupt bit position */
303#define EVT_IVG11_P 0x0000000b /* IVG11 interrupt bit position */
304#define EVT_IVG12_P 0x0000000c /* IVG12 interrupt bit position */
305#define EVT_IVG13_P 0x0000000d /* IVG13 interrupt bit position */
306#define EVT_IVG14_P 0x0000000e /* IVG14 interrupt bit position */
307#define EVT_IVG15_P 0x0000000f /* IVG15 interrupt bit position */
308
309/* ** Masks */
310#define EVT_EMU MK_BMSK_(EVT_EMU_P ) /* Emulator interrupt mask */
311#define EVT_RST MK_BMSK_(EVT_RST_P ) /* Reset interrupt mask */
312#define EVT_NMI MK_BMSK_(EVT_NMI_P ) /* Non Maskable interrupt mask */
313#define EVT_EVX MK_BMSK_(EVT_EVX_P ) /* Exception mask */
314#define EVT_IRPTEN MK_BMSK_(EVT_IRPTEN_P) /* Global interrupt enable mask */
315#define EVT_IVHW MK_BMSK_(EVT_IVHW_P ) /* Hardware Error interrupt mask */
316#define EVT_IVTMR MK_BMSK_(EVT_IVTMR_P ) /* Timer interrupt mask */
317#define EVT_IVG7 MK_BMSK_(EVT_IVG7_P ) /* IVG7 interrupt mask */
318#define EVT_IVG8 MK_BMSK_(EVT_IVG8_P ) /* IVG8 interrupt mask */
319#define EVT_IVG9 MK_BMSK_(EVT_IVG9_P ) /* IVG9 interrupt mask */
320#define EVT_IVG10 MK_BMSK_(EVT_IVG10_P ) /* IVG10 interrupt mask */
321#define EVT_IVG11 MK_BMSK_(EVT_IVG11_P ) /* IVG11 interrupt mask */
322#define EVT_IVG12 MK_BMSK_(EVT_IVG12_P ) /* IVG12 interrupt mask */
323#define EVT_IVG13 MK_BMSK_(EVT_IVG13_P ) /* IVG13 interrupt mask */
324#define EVT_IVG14 MK_BMSK_(EVT_IVG14_P ) /* IVG14 interrupt mask */
325#define EVT_IVG15 MK_BMSK_(EVT_IVG15_P ) /* IVG15 interrupt mask */
326
327/*
328 * DMEM_CONTROL Register
329 */
330
331/* ** Bit Positions */
332#define ENDM_P 0x00 /* (doesn't really exist) Enable Data Memory L1 */
333#define DMCTL_ENDM_P 0x00 /* "" (older define) */
334#define DMC0_P 0x01 /* Data Memory Configuration, 00 - A SRAM, B SRAM */
335#define DMCTL_DMC0_P 0x01 /* "" (older define) */
336#define DMC1_P 0x02 /* Data Memory Configuration, 10 - A SRAM, B SRAM */
337#define DMCTL_DMC1_P 0x02 /* "" (older define) */
338#define DMC2_P 0x03 /* Data Memory Configuration, 11 - A CACHE, B CACHE */
339#define DMCTL_DMC2_P 0x03 /* "" (older define) */
340#define DCBS_P 0x04 /* L1 Data Cache Bank Select */
341#define PORT_PREF0_P 0x12 /* DAG0 Port Preference */
342#define PORT_PREF1_P 0x13 /* DAG1 Port Preference */
343
344/* ** Masks */
345#define ENDM 0x00000001 /* (doesn't really exist) Enable Data Memory L1 */
346#define ENDCPLB 0x00000002 /* Enable DCPLB */
Wolfgang Denk8e7b7032006-03-12 02:55:22 +0100[diff] [blame]347#define ASRAM_BSRAM 0x00000000
Wolfgang Denk6cb142f2006-03-12 02:12:27 +0100[diff] [blame]348#define ACACHE_BSRAM 0x00000008
Wolfgang Denk8e7b7032006-03-12 02:55:22 +0100[diff] [blame]349#define ACACHE_BCACHE 0x0000000C
Wolfgang Denk6cb142f2006-03-12 02:12:27 +0100[diff] [blame]350#define DCBS 0x00000010 /* L1 Data Cache Bank Select */
351#define PORT_PREF0 0x00001000 /* DAG0 Port Preference */
352#define PORT_PREF1 0x00002000 /* DAG1 Port Preference */
353
354/* IMEM_CONTROL Register */
355/* ** Bit Positions */
356#define ENIM_P 0x00 /* Enable L1 Code Memory */
357#define IMCTL_ENIM_P 0x00 /* "" (older define) */
358#define ENICPLB_P 0x01 /* Enable ICPLB */
359#define IMCTL_ENICPLB_P 0x01 /* "" (older define) */
360#define IMC_P 0x02 /* Enable */
361#define IMCTL_IMC_P 0x02 /* Configure L1 code memory as cache (0=SRAM) */
362#define ILOC0_P 0x03 /* Lock Way 0 */
363#define ILOC1_P 0x04 /* Lock Way 1 */
364#define ILOC2_P 0x05 /* Lock Way 2 */
365#define ILOC3_P 0x06 /* Lock Way 3 */
366#define LRUPRIORST_P 0x0D /* Least Recently Used Replacement Priority */
367
368/* ** Masks */
369#define ENIM 0x00000001 /* Enable L1 Code Memory */
370#define ENICPLB 0x00000002 /* Enable ICPLB */
371#define IMC 0x00000004 /* Configure L1 code memory as cache (0=SRAM) */
372#define ILOC0 0x00000008 /* Lock Way 0 */
373#define ILOC1 0x00000010 /* Lock Way 1 */
374#define ILOC2 0x00000020 /* Lock Way 2 */
375#define ILOC3 0x00000040 /* Lock Way 3 */
376#define LRUPRIORST 0x00002000 /* Least Recently Used Replacement Priority */
377
378/* TCNTL Masks */
379#define TMPWR 0x00000001 /* Timer Low Power Control, 0=low power mode, 1=active state */
380#define TMREN 0x00000002 /* Timer enable, 0=disable, 1=enable */
381#define TAUTORLD 0x00000004 /* Timer auto reload */
382#define TINT 0x00000008 /* Timer generated interrupt 0=no interrupt has been generated, 1=interrupt has been generated (sticky) */
383
384/* TCNTL Bit Positions */
385#define TMPWR_P 0x00000000 /* Timer Low Power Control, 0=low power mode, 1=active state */
386#define TMREN_P 0x00000001 /* Timer enable, 0=disable, 1=enable */
387#define TAUTORLD_P 0x00000002 /* Timer auto reload */
388#define TINT_P 0x00000003 /* Timer generated interrupt 0=no interrupt has been generated, 1=interrupt has been generated (sticky) */
389
390/* DCPLB_DATA and ICPLB_DATA Registers */
391/* ** Bit Positions */
392#define CPLB_VALID_P 0x00000000 /* 0=invalid entry, 1=valid entry */
393#define CPLB_LOCK_P 0x00000001 /* 0=entry may be replaced, 1=entry locked */
394#define CPLB_USER_RD_P 0x00000002 /* 0=no read access, 1=read access allowed (user mode) */
395
396/* ** Masks */
397#define CPLB_VALID 0x00000001 /* 0=invalid entry, 1=valid entry */
398#define CPLB_LOCK 0x00000002 /* 0=entry may be replaced, 1=entry locked */
399#define CPLB_USER_RD 0x00000004 /* 0=no read access, 1=read access allowed (user mode) */
400#define PAGE_SIZE_1KB 0x00000000 /* 1 KB page size */
401#define PAGE_SIZE_4KB 0x00010000 /* 4 KB page size */
402#define PAGE_SIZE_1MB 0x00020000 /* 1 MB page size */
403#define PAGE_SIZE_4MB 0x00030000 /* 4 MB page size */
404#define CPLB_L1SRAM 0x00000020 /* 0=SRAM mapped in L1, 0=SRAM not mapped to L1 */
405#define CPLB_PORTPRIO 0x00000200 /* 0=low priority port, 1= high priority port */
406#define CPLB_L1_CHBL 0x00001000 /* 0=non-cacheable in L1, 1=cacheable in L1 */
407
408/* ICPLB_DATA only */
409#define CPLB_LRUPRIO 0x00000100 /* 0=can be replaced by any line, 1=priority for non-replacement */
410
411/* DCPLB_DATA only */
412#define CPLB_USER_WR 0x00000008 /* 0=no write access, 0=write access allowed (user mode) */
413#define CPLB_SUPV_WR 0x00000010 /* 0=no write access, 0=write access allowed (supervisor mode) */
414#define CPLB_DIRTY 0x00000080 /* 1=dirty, 0=clean */
415#define CPLB_L1_AOW 0x00008000 /* 0=do not allocate cache lines on write-through writes */
416 /* 1= allocate cache lines on write-through writes. */
417#define CPLB_WT 0x00004000 /* 0=write-back, 1=write-through */
418
419/* ITEST_COMMAND and DTEST_COMMAND Registers */
420/* ** Masks */
421#define TEST_READ 0x00000000 /* Read Access */
422#define TEST_WRITE 0x00000002 /* Write Access */
423#define TEST_TAG 0x00000000 /* Access TAG */
424#define TEST_DATA 0x00000004 /* Access DATA */
425#define TEST_DW0 0x00000000 /* Select Double Word 0 */
426#define TEST_DW1 0x00000008 /* Select Double Word 1 */
427#define TEST_DW2 0x00000010 /* Select Double Word 2 */
428#define TEST_DW3 0x00000018 /* Select Double Word 3 */
429#define TEST_MB0 0x00000000 /* Select Mini-Bank 0 */
430#define TEST_MB1 0x00010000 /* Select Mini-Bank 1 */
431#define TEST_MB2 0x00020000 /* Select Mini-Bank 2 */
432#define TEST_MB3 0x00030000 /* Select Mini-Bank 3 */
433#define TEST_SET(x) ((x << 5) & 0x03E0) /* Set Index 0->31 */
434#define TEST_WAY0 0x00000000 /* Access Way0 */
435#define TEST_WAY1 0x04000000 /* Access Way1 */
436
437/* ** ITEST_COMMAND only */
438#define TEST_WAY2 0x08000000 /* Access Way2 */
439#define TEST_WAY3 0x0C000000 /* Access Way3 */
440
441/* ** DTEST_COMMAND only */
442#define TEST_BNKSELA 0x00000000 /* Access SuperBank A */
443#define TEST_BNKSELB 0x00800000 /* Access SuperBank B */
444
445#endif /* _DEF_LPBLACKFIN_H */