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Anup Patel3fda0262019-02-25 08:15:19 +00001// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (c) 2019 Western Digital Corporation or its affiliates.
4 *
5 * Authors:
6 * Anup Patel <anup.patel@wdc.com>
7 */
8
Anup Patel3fda0262019-02-25 08:15:19 +00009#include <dm.h>
Simon Glass09140112020-05-10 11:40:03 -060010#include <env.h>
Simon Glass691d7192020-05-10 11:40:02 -060011#include <init.h>
Pragnesh Patel88eec612020-05-29 11:33:22 +053012#include <log.h>
Jagan Teki868e2952020-07-15 15:38:58 +053013#include <linux/bitops.h>
Simon Glasseb41d8a2020-05-10 11:40:08 -060014#include <linux/bug.h>
Anup Patel9f2a0c02019-06-25 06:31:44 +000015#include <linux/delay.h>
16#include <linux/io.h>
Pragnesh Patel88eec612020-05-29 11:33:22 +053017#include <misc.h>
Pragnesh Patel01cdef22020-05-29 11:33:35 +053018#include <spl.h>
Pragnesh Patel5ce50202020-05-29 12:14:51 +053019#include <asm/arch/cache.h>
Pragnesh Patel88eec612020-05-29 11:33:22 +053020
21/*
22 * This define is a value used for error/unknown serial.
23 * If we really care about distinguishing errors and 0 is
24 * valid, we'll need a different one.
25 */
26#define ERROR_READING_SERIAL_NUMBER 0
Anup Patel9f2a0c02019-06-25 06:31:44 +000027
28#ifdef CONFIG_MISC_INIT_R
29
Pragnesh Patel88eec612020-05-29 11:33:22 +053030#if CONFIG_IS_ENABLED(SIFIVE_OTP)
31static u32 otp_read_serialnum(struct udevice *dev)
Anup Patel9f2a0c02019-06-25 06:31:44 +000032{
33 int ret;
34 u32 serial[2] = {0};
35
36 for (int i = 0xfe * 4; i > 0; i -= 8) {
Pragnesh Patel88eec612020-05-29 11:33:22 +053037 ret = misc_read(dev, i, serial, sizeof(serial));
38
39 if (ret != sizeof(serial)) {
40 printf("%s: error reading serial from OTP\n", __func__);
Anup Patel9f2a0c02019-06-25 06:31:44 +000041 break;
42 }
Pragnesh Patel88eec612020-05-29 11:33:22 +053043
Anup Patel9f2a0c02019-06-25 06:31:44 +000044 if (serial[0] == ~serial[1])
45 return serial[0];
46 }
47
Pragnesh Patel88eec612020-05-29 11:33:22 +053048 return ERROR_READING_SERIAL_NUMBER;
49}
50#endif
51
52static u32 fu540_read_serialnum(void)
53{
54 u32 serial = ERROR_READING_SERIAL_NUMBER;
55
56#if CONFIG_IS_ENABLED(SIFIVE_OTP)
57 struct udevice *dev;
58 int ret;
59
60 /* init OTP */
61 ret = uclass_get_device_by_driver(UCLASS_MISC,
62 DM_GET_DRIVER(sifive_otp), &dev);
63
64 if (ret) {
65 debug("%s: could not find otp device\n", __func__);
66 return serial;
67 }
68
69 /* read serial from OTP and set env var */
70 serial = otp_read_serialnum(dev);
71#endif
72
73 return serial;
Anup Patel9f2a0c02019-06-25 06:31:44 +000074}
75
76static void fu540_setup_macaddr(u32 serialnum)
77{
78 /* Default MAC address */
79 unsigned char mac[6] = { 0x70, 0xb3, 0xd5, 0x92, 0xf0, 0x00 };
80
81 /*
82 * We derive our board MAC address by ORing last three bytes
83 * of board serial number to above default MAC address.
84 *
85 * This logic of deriving board MAC address is taken from
86 * SiFive FSBL and is kept unchanged.
87 */
88 mac[5] |= (serialnum >> 0) & 0xff;
89 mac[4] |= (serialnum >> 8) & 0xff;
90 mac[3] |= (serialnum >> 16) & 0xff;
91
92 /* Update environment variable */
93 eth_env_set_enetaddr("ethaddr", mac);
94}
95
96int misc_init_r(void)
97{
Sagar Shrikant Kadamcba06352019-08-12 07:57:40 -070098 u32 serial_num;
99 char buf[9] = {0};
Anup Patel9f2a0c02019-06-25 06:31:44 +0000100
Sagar Shrikant Kadamcba06352019-08-12 07:57:40 -0700101 /* Set ethaddr environment variable from board serial number */
102 if (!env_get("serial#")) {
103 serial_num = fu540_read_serialnum();
104 if (!serial_num) {
105 WARN(true, "Board serial number should not be 0 !!\n");
106 return 0;
107 }
108 snprintf(buf, sizeof(buf), "%08x", serial_num);
109 env_set("serial#", buf);
110 fu540_setup_macaddr(serial_num);
111 }
Anup Patel9f2a0c02019-06-25 06:31:44 +0000112 return 0;
113}
114
115#endif
Anup Patel3fda0262019-02-25 08:15:19 +0000116
117int board_init(void)
118{
Pragnesh Patel5ce50202020-05-29 12:14:51 +0530119 int ret;
120
121 /* enable all cache ways */
122 ret = cache_enable_ways();
123 if (ret) {
124 debug("%s: could not enable cache ways\n", __func__);
125 return ret;
126 }
Anup Patel3fda0262019-02-25 08:15:19 +0000127
128 return 0;
129}
Pragnesh Patel01cdef22020-05-29 11:33:35 +0530130
131#ifdef CONFIG_SPL
Jagan Teki868e2952020-07-15 15:38:58 +0530132#define MODE_SELECT_REG 0x1000
133#define MODE_SELECT_QSPI 0x6
134#define MODE_SELECT_SD 0xb
135#define MODE_SELECT_MASK GENMASK(3, 0)
136
Pragnesh Patel01cdef22020-05-29 11:33:35 +0530137u32 spl_boot_device(void)
138{
Jagan Teki868e2952020-07-15 15:38:58 +0530139 u32 mode_select = readl((void *)MODE_SELECT_REG);
140 u32 boot_device = mode_select & MODE_SELECT_MASK;
141
142 switch (boot_device) {
143 case MODE_SELECT_QSPI:
144 return BOOT_DEVICE_SPI;
145 case MODE_SELECT_SD:
146 return BOOT_DEVICE_MMC1;
147 default:
148 debug("Unsupported boot device 0x%x but trying MMC1\n",
149 boot_device);
150 return BOOT_DEVICE_MMC1;
151 }
Pragnesh Patel01cdef22020-05-29 11:33:35 +0530152}
153#endif
154
155#ifdef CONFIG_SPL_LOAD_FIT
156int board_fit_config_name_match(const char *name)
157{
158 /* boot using first FIT config */
159 return 0;
160}
161#endif