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Prabhakar Kushwaha7d436072013-09-12 11:11:28 +05301/*
York Sunc60dee02014-03-27 17:54:48 -07002 * Copyright 2013-2014 Freescale Semiconductor, Inc.
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +05303 *
4 * See file CREDITS for list of people who contributed to this
5 * project.
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
20 * MA 02111-1307 USA
21 */
22
23#ifndef __CONFIG_H
24#define __CONFIG_H
25
26/*
27 * T1040 QDS board configuration file
28 */
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +053029
30#ifdef CONFIG_RAMBOOT_PBL
31#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
32#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
Masahiro Yamadae4536f82014-03-11 11:05:16 +090033#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t1040qds/t1040_pbi.cfg
34#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t1040qds/t1040_rcw.cfg
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +053035#endif
36
37/* High Level Configuration Options */
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +053038#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +053039#define CONFIG_MP /* support multiple processors */
40
Tang Yuantian48f6a9a2014-04-17 15:33:44 +080041/* support deep sleep */
42#define CONFIG_DEEP_SLEEP
Tang Yuantian48f6a9a2014-04-17 15:33:44 +080043
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +053044#ifndef CONFIG_SYS_TEXT_BASE
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +053045#define CONFIG_SYS_TEXT_BASE 0xeff40000
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +053046#endif
47
48#ifndef CONFIG_RESET_VECTOR_ADDRESS
49#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
50#endif
51
52#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
York Sun51370d52016-12-28 08:43:45 -080053#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +053054#define CONFIG_PCI_INDIRECT_BRIDGE
Robert P. J. Dayb38eaec2016-05-03 19:52:49 -040055#define CONFIG_PCIE1 /* PCIE controller 1 */
56#define CONFIG_PCIE2 /* PCIE controller 2 */
57#define CONFIG_PCIE3 /* PCIE controller 3 */
58#define CONFIG_PCIE4 /* PCIE controller 4 */
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +053059
60#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
61#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
62
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +053063#define CONFIG_ENV_OVERWRITE
64
Masahiro Yamadae856bdc2017-02-11 22:43:54 +090065#ifndef CONFIG_MTD_NOR_FLASH
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +053066#define CONFIG_ENV_IS_NOWHERE
67#else
68#define CONFIG_FLASH_CFI_DRIVER
69#define CONFIG_SYS_FLASH_CFI
70#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
71#endif
72
Masahiro Yamadae856bdc2017-02-11 22:43:54 +090073#ifdef CONFIG_MTD_NOR_FLASH
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +053074#if defined(CONFIG_SPIFLASH)
75#define CONFIG_SYS_EXTRA_ENV_RELOC
76#define CONFIG_ENV_IS_IN_SPI_FLASH
77#define CONFIG_ENV_SPI_BUS 0
78#define CONFIG_ENV_SPI_CS 0
79#define CONFIG_ENV_SPI_MAX_HZ 10000000
80#define CONFIG_ENV_SPI_MODE 0
81#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
82#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
83#define CONFIG_ENV_SECT_SIZE 0x10000
84#elif defined(CONFIG_SDCARD)
85#define CONFIG_SYS_EXTRA_ENV_RELOC
86#define CONFIG_ENV_IS_IN_MMC
87#define CONFIG_SYS_MMC_ENV_DEV 0
88#define CONFIG_ENV_SIZE 0x2000
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +053089#define CONFIG_ENV_OFFSET (512 * 1658)
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +053090#elif defined(CONFIG_NAND)
91#define CONFIG_SYS_EXTRA_ENV_RELOC
92#define CONFIG_ENV_IS_IN_NAND
93#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +053094#define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +053095#else
96#define CONFIG_ENV_IS_IN_FLASH
97#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
98#define CONFIG_ENV_SIZE 0x2000
99#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
100#endif
Masahiro Yamadae856bdc2017-02-11 22:43:54 +0900101#else /* CONFIG_MTD_NOR_FLASH */
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530102#define CONFIG_ENV_SIZE 0x2000
103#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
104#endif
105
106#ifndef __ASSEMBLY__
107unsigned long get_board_sys_clk(void);
108unsigned long get_board_ddr_clk(void);
109#endif
110
111#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
112#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
113
114/*
115 * These can be toggled for performance analysis, otherwise use default.
116 */
117#define CONFIG_SYS_CACHE_STASHING
118#define CONFIG_BACKSIDE_L2_CACHE
119#define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E
120#define CONFIG_BTB /* toggle branch predition */
121#define CONFIG_DDR_ECC
122#ifdef CONFIG_DDR_ECC
123#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
124#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
125#endif
126
127#define CONFIG_ENABLE_36BIT_PHYS
128
129#define CONFIG_ADDR_MAP
130#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
131
132#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
133#define CONFIG_SYS_MEMTEST_END 0x00400000
134#define CONFIG_SYS_ALT_MEMTEST
135#define CONFIG_PANIC_HANG /* do not reset board on panic */
136
137/*
138 * Config the L3 Cache as L3 SRAM
139 */
140#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
141
142#define CONFIG_SYS_DCSRBAR 0xf0000000
143#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
144
145/* EEPROM */
146#define CONFIG_ID_EEPROM
147#define CONFIG_SYS_I2C_EEPROM_NXID
148#define CONFIG_SYS_EEPROM_BUS_NUM 0
149#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
150#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
151#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
152#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
153
154/*
155 * DDR Setup
156 */
157#define CONFIG_VERY_BIG_RAM
158#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
159#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
160
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530161#define CONFIG_DIMM_SLOTS_PER_CTLR 1
Priyanka Jain2eb3ac72014-01-03 11:24:55 +0530162#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530163
164#define CONFIG_DDR_SPD
York Sun1b2af9b2014-10-27 11:45:11 -0700165#define CONFIG_FSL_DDR_INTERACTIVE
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530166
167#define CONFIG_SYS_SPD_BUS_NUM 0
168#define SPD_EEPROM_ADDRESS 0x51
169
170#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
171
172/*
173 * IFC Definitions
174 */
175#define CONFIG_SYS_FLASH_BASE 0xe0000000
176#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
177
178#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
179#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
180 + 0x8000000) | \
181 CSPR_PORT_SIZE_16 | \
182 CSPR_MSEL_NOR | \
183 CSPR_V)
184#define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
185#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
186 CSPR_PORT_SIZE_16 | \
187 CSPR_MSEL_NOR | \
188 CSPR_V)
189#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
Sandeep Singh377ffcf2014-06-05 18:49:57 +0530190
191/*
192 * TDM Definition
193 */
194#define T1040_TDM_QUIRK_CCSR_BASE 0xfe000000
195
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530196/* NOR Flash Timing Params */
197#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
198#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
199 FTIM0_NOR_TEADC(0x5) | \
200 FTIM0_NOR_TEAHC(0x5))
201#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
202 FTIM1_NOR_TRAD_NOR(0x1A) |\
203 FTIM1_NOR_TSEQRAD_NOR(0x13))
204#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
205 FTIM2_NOR_TCH(0x4) | \
206 FTIM2_NOR_TWPH(0x0E) | \
207 FTIM2_NOR_TWP(0x1c))
208#define CONFIG_SYS_NOR_FTIM3 0x0
209
210#define CONFIG_SYS_FLASH_QUIET_TEST
211#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
212
213#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
214#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
215#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
216#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
217
218#define CONFIG_SYS_FLASH_EMPTY_INFO
219#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
220 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
221#define CONFIG_FSL_QIXIS /* use common QIXIS code */
222#define QIXIS_BASE 0xffdf0000
223#define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)
224#define QIXIS_LBMAP_SWITCH 0x06
225#define QIXIS_LBMAP_MASK 0x0f
226#define QIXIS_LBMAP_SHIFT 0
227#define QIXIS_LBMAP_DFLTBANK 0x00
228#define QIXIS_LBMAP_ALTBANK 0x04
229#define QIXIS_RST_CTL_RESET 0x31
230#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
231#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
232#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
Prabhakar Kushwaha8c618dd2013-12-26 12:40:55 +0530233#define QIXIS_RST_FORCE_MEM 0x01
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530234
235#define CONFIG_SYS_CSPR3_EXT (0xf)
236#define CONFIG_SYS_CSPR3 (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
237 | CSPR_PORT_SIZE_8 \
238 | CSPR_MSEL_GPCM \
239 | CSPR_V)
240#define CONFIG_SYS_AMASK3 IFC_AMASK(4*1024)
241#define CONFIG_SYS_CSOR3 0x0
242/* QIXIS Timing parameters for IFC CS3 */
243#define CONFIG_SYS_CS3_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
244 FTIM0_GPCM_TEADC(0x0e) | \
245 FTIM0_GPCM_TEAHC(0x0e))
246#define CONFIG_SYS_CS3_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
247 FTIM1_GPCM_TRAD(0x3f))
248#define CONFIG_SYS_CS3_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
Prabhakar Kushwaha562de1d2013-12-12 12:09:01 +0530249 FTIM2_GPCM_TCH(0x8) | \
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530250 FTIM2_GPCM_TWP(0x1f))
251#define CONFIG_SYS_CS3_FTIM3 0x0
252
253#define CONFIG_NAND_FSL_IFC
254#define CONFIG_SYS_NAND_BASE 0xff800000
255#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
256
257#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
258#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
259 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
260 | CSPR_MSEL_NAND /* MSEL = NAND */ \
261 | CSPR_V)
262#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
263
264#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
265 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
266 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
267 | CSOR_NAND_RAL_3 /* RAL = 3Byes */ \
268 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
269 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
270 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
271
272#define CONFIG_SYS_NAND_ONFI_DETECTION
273
274/* ONFI NAND Flash mode0 Timing Params */
275#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
276 FTIM0_NAND_TWP(0x18) | \
277 FTIM0_NAND_TWCHT(0x07) | \
278 FTIM0_NAND_TWH(0x0a))
279#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
280 FTIM1_NAND_TWBE(0x39) | \
281 FTIM1_NAND_TRR(0x0e) | \
282 FTIM1_NAND_TRP(0x18))
283#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
284 FTIM2_NAND_TREH(0x0a) | \
285 FTIM2_NAND_TWHRE(0x1e))
286#define CONFIG_SYS_NAND_FTIM3 0x0
287
288#define CONFIG_SYS_NAND_DDR_LAW 11
289#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
290#define CONFIG_SYS_MAX_NAND_DEVICE 1
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530291#define CONFIG_CMD_NAND
292
293#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
294
295#if defined(CONFIG_NAND)
296#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
297#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
298#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
299#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
300#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
301#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
302#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
303#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
304#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
305#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
306#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
307#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
308#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
309#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
310#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
311#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
312#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
313#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
314#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
315#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
316#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
317#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
318#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
319#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
320#else
321#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
322#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
323#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
324#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
325#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
326#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
327#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
328#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
329#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
330#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
331#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
332#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
333#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
334#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
335#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
336#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
337#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
338#define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
339#define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
340#define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
341#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
342#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
343#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
344#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
345#endif
346
347#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
348
349#if defined(CONFIG_RAMBOOT_PBL)
350#define CONFIG_SYS_RAMBOOT
351#endif
352
353#define CONFIG_BOARD_EARLY_INIT_R
354#define CONFIG_MISC_INIT_R
355
356#define CONFIG_HWCONFIG
357
358/* define to use L1 as initial stack */
359#define CONFIG_L1_INIT_RAM
360#define CONFIG_SYS_INIT_RAM_LOCK
361#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
362#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
York Sunb3142e22015-08-17 13:31:51 -0700363#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530364/* The assembler doesn't like typecast */
365#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
366 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
367 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
368#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
369
370#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
371 GENERATED_GBL_DATA_SIZE)
372#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
373
Prabhakar Kushwaha9307cba2014-03-31 15:31:48 +0530374#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
Priyanka Jain337b0c52014-02-26 16:11:53 +0530375#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530376
377/* Serial Port - controlled on board with jumper J8
378 * open - index 2
379 * shorted - index 1
380 */
381#define CONFIG_CONS_INDEX 1
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530382#define CONFIG_SYS_NS16550_SERIAL
383#define CONFIG_SYS_NS16550_REG_SIZE 1
384#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
385
386#define CONFIG_SYS_BAUDRATE_TABLE \
387 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
388
389#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
390#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
391#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
392#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530393
Priyanka Jain337b0c52014-02-26 16:11:53 +0530394/* Video */
395#define CONFIG_FSL_DIU_FB
396#ifdef CONFIG_FSL_DIU_FB
Wang Dongshengc53711b2014-03-19 10:47:55 +0800397#define CONFIG_FSL_DIU_CH7301
Priyanka Jain337b0c52014-02-26 16:11:53 +0530398#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x180000)
Priyanka Jain337b0c52014-02-26 16:11:53 +0530399#define CONFIG_VIDEO_LOGO
400#define CONFIG_VIDEO_BMP_LOGO
401#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
402/*
403 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
404 * disable empty flash sector detection, which is I/O-intensive.
405 */
406#undef CONFIG_SYS_FLASH_EMPTY_INFO
407#endif
408
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530409/* I2C */
410#define CONFIG_SYS_I2C
411#define CONFIG_SYS_I2C_FSL /* Use FSL common I2C driver */
Priyanka Jain2eb3ac72014-01-03 11:24:55 +0530412#define CONFIG_SYS_FSL_I2C_SPEED 50000 /* I2C speed in Hz */
Shengzhou Liub0d97cd2014-07-07 12:17:47 +0800413#define CONFIG_SYS_FSL_I2C2_SPEED 50000
414#define CONFIG_SYS_FSL_I2C3_SPEED 50000
415#define CONFIG_SYS_FSL_I2C4_SPEED 50000
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530416#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530417#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
Shengzhou Liub0d97cd2014-07-07 12:17:47 +0800418#define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
419#define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530420#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
Shengzhou Liub0d97cd2014-07-07 12:17:47 +0800421#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
422#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
423#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530424
425#define I2C_MUX_PCA_ADDR 0x77
426#define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
427
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530428/* I2C bus multiplexer */
429#define I2C_MUX_CH_DEFAULT 0x8
Priyanka Jain337b0c52014-02-26 16:11:53 +0530430#define I2C_MUX_CH_DIU 0xC
431
432/* LDI/DVI Encoder for display */
433#define CONFIG_SYS_I2C_LDI_ADDR 0x38
434#define CONFIG_SYS_I2C_DVI_ADDR 0x75
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530435
436/*
437 * RTC configuration
438 */
439#define RTC
440#define CONFIG_RTC_DS3231 1
441#define CONFIG_SYS_I2C_RTC_ADDR 0x68
442
443/*
444 * eSPI - Enhanced SPI
445 */
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530446#define CONFIG_SF_DEFAULT_SPEED 10000000
447#define CONFIG_SF_DEFAULT_MODE 0
448
449/*
450 * General PCI
451 * Memory space is mapped 1-1, but I/O space must start from 0.
452 */
453
454#ifdef CONFIG_PCI
455/* controller 1, direct to uli, tgtid 3, Base address 20000 */
456#ifdef CONFIG_PCIE1
457#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
458#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
459#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
460#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */
461#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
462#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
463#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
464#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
465#endif
466
467/* controller 2, Slot 2, tgtid 2, Base address 201000 */
468#ifdef CONFIG_PCIE2
469#define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000
470#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
471#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull
472#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
473#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
474#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
475#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
476#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
477#endif
478
479/* controller 3, Slot 1, tgtid 1, Base address 202000 */
480#ifdef CONFIG_PCIE3
481#define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000
482#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
483#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull
484#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
485#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
486#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
487#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
488#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
489#endif
490
491/* controller 4, Base address 203000 */
492#ifdef CONFIG_PCIE4
493#define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000
494#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
495#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull
496#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
497#define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000
498#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
499#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
500#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
501#endif
502
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530503#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530504#endif /* CONFIG_PCI */
505
506/* SATA */
507#define CONFIG_FSL_SATA_V2
508#ifdef CONFIG_FSL_SATA_V2
509#define CONFIG_LIBATA
510#define CONFIG_FSL_SATA
511
512#define CONFIG_SYS_SATA_MAX_DEVICE 2
513#define CONFIG_SATA1
514#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
515#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
516#define CONFIG_SATA2
517#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
518#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
519
520#define CONFIG_LBA48
521#define CONFIG_CMD_SATA
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530522#endif
523
524/*
525* USB
526*/
527#define CONFIG_HAS_FSL_DR_USB
528
529#ifdef CONFIG_HAS_FSL_DR_USB
530#define CONFIG_USB_EHCI
531
532#ifdef CONFIG_USB_EHCI
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530533#define CONFIG_USB_EHCI_FSL
534#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530535#endif
536#endif
537
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530538#ifdef CONFIG_MMC
539#define CONFIG_FSL_ESDHC
Yangbo Lu12486f32015-09-17 10:27:38 +0800540#define CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530541#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
Yangbo Lufa1e0352015-09-17 10:27:27 +0800542#define CONFIG_FSL_ESDHC_ADAPTER_IDENT
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530543#endif
544
545/* Qman/Bman */
546#ifndef CONFIG_NOBQFMAN
547#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
Jeffrey Ladouceur2a8b3422014-12-03 18:08:43 -0500548#define CONFIG_SYS_BMAN_NUM_PORTALS 10
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530549#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
550#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
551#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
Jeffrey Ladouceur3fa66db2014-12-08 14:54:01 -0500552#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
553#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
554#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
555#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
556#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
557 CONFIG_SYS_BMAN_CENA_SIZE)
558#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
559#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
Jeffrey Ladouceur2a8b3422014-12-03 18:08:43 -0500560#define CONFIG_SYS_QMAN_NUM_PORTALS 10
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530561#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
562#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
563#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
Jeffrey Ladouceur3fa66db2014-12-08 14:54:01 -0500564#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
565#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
566#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
567#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
568#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
569 CONFIG_SYS_QMAN_CENA_SIZE)
570#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
571#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530572
573#define CONFIG_SYS_DPAA_FMAN
574#define CONFIG_SYS_DPAA_PME
575
Zhao Qiang6259e292014-03-21 16:21:46 +0800576#define CONFIG_QE
577#define CONFIG_U_QE
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530578/* Default address of microcode for the Linux Fman driver */
579#if defined(CONFIG_SPIFLASH)
580/*
581 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
582 * env, so we got 0x110000.
583 */
584#define CONFIG_SYS_QE_FW_IN_SPIFLASH
Zhao Qiangdcf1d772014-03-21 16:21:44 +0800585#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530586#elif defined(CONFIG_SDCARD)
587/*
588 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +0530589 * about 825KB (1650 blocks), Env is stored after the image, and the env size is
590 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530591 */
592#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
Zhao Qiangdcf1d772014-03-21 16:21:44 +0800593#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530594#elif defined(CONFIG_NAND)
595#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
Zhao Qiangdcf1d772014-03-21 16:21:44 +0800596#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530597#else
598#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
Zhao Qiangdcf1d772014-03-21 16:21:44 +0800599#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
Zhao Qiang6259e292014-03-21 16:21:46 +0800600#define CONFIG_SYS_QE_FW_ADDR 0xEFF10000
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530601#endif
602#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
603#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
604#endif /* CONFIG_NOBQFMAN */
605
606#ifdef CONFIG_SYS_DPAA_FMAN
607#define CONFIG_FMAN_ENET
608#define CONFIG_PHYLIB_10G
609#define CONFIG_PHY_VITESSE
610#define CONFIG_PHY_REALTEK
611#define CONFIG_PHY_TERANETICS
612#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
613#define SGMII_CARD_PORT2_PHY_ADDR 0x10
614#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
615#define SGMII_CARD_PORT4_PHY_ADDR 0x11
616#endif
617
618#ifdef CONFIG_FMAN_ENET
Prabhakar Kushwaha5b7672f2014-01-27 15:55:20 +0530619#define CONFIG_SYS_FM1_DTSEC4_PHY_ADDR 0x01
620#define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR 0x02
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530621
622#define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR 0x1c
623#define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR 0x1d
624#define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR 0x1e
625#define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR 0x1f
626
627#define CONFIG_MII /* MII PHY management */
628#define CONFIG_ETHPRIME "FM1@DTSEC1"
629#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
630#endif
631
Codrin Ciubotariua83fccc2015-01-21 11:54:11 +0200632/* Enable VSC9953 L2 Switch driver */
633#define CONFIG_VSC9953
Codrin Ciubotariu4c1ceb62016-03-14 13:46:51 +0200634#define CONFIG_CMD_ETHSW
Codrin Ciubotariua83fccc2015-01-21 11:54:11 +0200635#define CONFIG_SYS_FM1_QSGMII11_PHY_ADDR 0x14
636#define CONFIG_SYS_FM1_QSGMII21_PHY_ADDR 0x18
637
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530638/*
Prabhakar Kushwaha68b74732014-04-02 17:26:23 +0530639 * Dynamic MTD Partition support with mtdparts
640 */
Masahiro Yamadae856bdc2017-02-11 22:43:54 +0900641#ifdef CONFIG_MTD_NOR_FLASH
Prabhakar Kushwaha68b74732014-04-02 17:26:23 +0530642#define CONFIG_MTD_DEVICE
643#define CONFIG_MTD_PARTITIONS
644#define CONFIG_CMD_MTDPARTS
645#define CONFIG_FLASH_CFI_MTD
646#define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
647 "spi0=spife110000.0"
648#define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
649 "128k(dtb),96m(fs),-(user);"\
650 "fff800000.flash:2m(uboot),9m(kernel),"\
651 "128k(dtb),96m(fs),-(user);spife110000.0:" \
652 "2m(uboot),9m(kernel),128k(dtb),-(user)"
653#endif
654
655/*
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530656 * Environment
657 */
658#define CONFIG_LOADS_ECHO /* echo on for serial download */
659#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
660
661/*
662 * Command line configuration.
663 */
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530664#define CONFIG_CMD_EEPROM
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530665#define CONFIG_CMD_ERRATA
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530666#define CONFIG_CMD_IRQ
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530667#define CONFIG_CMD_REGINFO
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530668
669#ifdef CONFIG_PCI
670#define CONFIG_CMD_PCI
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530671#endif
672
Ruchika Gupta737537e2014-10-15 11:35:31 +0530673/* Hash command with SHA acceleration supported in hardware */
674#ifdef CONFIG_FSL_CAAM
675#define CONFIG_CMD_HASH
676#define CONFIG_SHA_HW_ACCEL
677#endif
678
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530679/*
680 * Miscellaneous configurable options
681 */
682#define CONFIG_SYS_LONGHELP /* undef to save memory */
683#define CONFIG_CMDLINE_EDITING /* Command-line editing */
684#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
685#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530686#ifdef CONFIG_CMD_KGDB
687#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
688#else
689#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
690#endif
691#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
692#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
693#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530694
695/*
696 * For booting Linux, the board info and command line data
697 * have to be in the first 64 MB of memory, since this is
698 * the maximum mapped by the Linux kernel during initialization.
699 */
700#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
701#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
702
703#ifdef CONFIG_CMD_KGDB
704#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530705#endif
706
707/*
708 * Environment Configuration
709 */
710#define CONFIG_ROOTPATH "/opt/nfsroot"
711#define CONFIG_BOOTFILE "uImage"
712#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
713
714/* default location for tftp and bootm */
715#define CONFIG_LOADADDR 1000000
716
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530717#define __USB_PHY_TYPE utmi
718
719#define CONFIG_EXTRA_ENV_SETTINGS \
York Sun1b2af9b2014-10-27 11:45:11 -0700720 "hwconfig=fsl_ddr:bank_intlv=auto;" \
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530721 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
722 "netdev=eth0\0" \
Priyanka Jain337b0c52014-02-26 16:11:53 +0530723 "video-mode=fslfb:1024x768-32@60,monitor=dvi\0" \
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530724 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
725 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
726 "tftpflash=tftpboot $loadaddr $uboot && " \
727 "protect off $ubootaddr +$filesize && " \
728 "erase $ubootaddr +$filesize && " \
729 "cp.b $loadaddr $ubootaddr $filesize && " \
730 "protect on $ubootaddr +$filesize && " \
731 "cmp.b $loadaddr $ubootaddr $filesize\0" \
732 "consoledev=ttyS0\0" \
733 "ramdiskaddr=2000000\0" \
734 "ramdiskfile=t1040qds/ramdisk.uboot\0" \
Scott Woodb24a4f62016-07-19 17:52:06 -0500735 "fdtaddr=1e00000\0" \
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530736 "fdtfile=t1040qds/t1040qds.dtb\0" \
Kim Phillips32465842014-05-14 19:33:45 -0500737 "bdev=sda3\0"
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530738
739#define CONFIG_LINUX \
740 "setenv bootargs root=/dev/ram rw " \
741 "console=$consoledev,$baudrate $othbootargs;" \
742 "setenv ramdiskaddr 0x02000000;" \
743 "setenv fdtaddr 0x00c00000;" \
744 "setenv loadaddr 0x1000000;" \
745 "bootm $loadaddr $ramdiskaddr $fdtaddr"
746
747#define CONFIG_HDBOOT \
748 "setenv bootargs root=/dev/$bdev rw " \
749 "console=$consoledev,$baudrate $othbootargs;" \
750 "tftp $loadaddr $bootfile;" \
751 "tftp $fdtaddr $fdtfile;" \
752 "bootm $loadaddr - $fdtaddr"
753
754#define CONFIG_NFSBOOTCOMMAND \
755 "setenv bootargs root=/dev/nfs rw " \
756 "nfsroot=$serverip:$rootpath " \
757 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
758 "console=$consoledev,$baudrate $othbootargs;" \
759 "tftp $loadaddr $bootfile;" \
760 "tftp $fdtaddr $fdtfile;" \
761 "bootm $loadaddr - $fdtaddr"
762
763#define CONFIG_RAMBOOTCOMMAND \
764 "setenv bootargs root=/dev/ram rw " \
765 "console=$consoledev,$baudrate $othbootargs;" \
766 "tftp $ramdiskaddr $ramdiskfile;" \
767 "tftp $loadaddr $bootfile;" \
768 "tftp $fdtaddr $fdtfile;" \
769 "bootm $loadaddr $ramdiskaddr $fdtaddr"
770
771#define CONFIG_BOOTCOMMAND CONFIG_LINUX
772
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530773#include <asm/fsl_secure_boot.h>
Aneesh Bansalef6c55a2016-01-22 16:37:22 +0530774
Prabhakar Kushwaha7d436072013-09-12 11:11:28 +0530775#endif /* __CONFIG_H */