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Stefan Roeseb765ffb2007-06-15 08:18:01 +02001/*
Stefan Roesef47b0482013-03-08 16:50:41 +01002 * (C) Copyright 2007-2013
Stefan Roeseb765ffb2007-06-15 08:18:01 +02003 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Stefan Roeseb765ffb2007-06-15 08:18:01 +02006 */
7
Sascha Lauef14ae412010-08-19 09:38:56 +02008/*
Stefan Roeseb765ffb2007-06-15 08:18:01 +02009 * lwmon5.h - configuration for lwmon5 board
Sascha Lauef14ae412010-08-19 09:38:56 +020010 */
Stefan Roeseb765ffb2007-06-15 08:18:01 +020011#ifndef __CONFIG_H
12#define __CONFIG_H
13
Sascha Lauef14ae412010-08-19 09:38:56 +020014/*
15 * Liebherr extra version info
16 */
17#define CONFIG_IDENT_STRING " - v2.0"
18
19/*
Stefan Roeseb765ffb2007-06-15 08:18:01 +020020 * High Level Configuration Options
Sascha Lauef14ae412010-08-19 09:38:56 +020021 */
Stefan Roeseb765ffb2007-06-15 08:18:01 +020022#define CONFIG_LWMON5 1 /* Board is lwmon5 */
23#define CONFIG_440EPX 1 /* Specific PPC440EPx */
Stefan Roesee73846b2007-06-15 11:33:41 +020024#define CONFIG_440 1 /* ... PPC440 family */
Wolfgang Denk2ae18242010-10-06 09:05:45 +020025
Stefan Roesef47b0482013-03-08 16:50:41 +010026#ifdef CONFIG_LCD4_LWMON5
27#define CONFIG_SYS_TEXT_BASE 0x01000000 /* SPL U-Boot TEXT_BASE */
28#define CONFIG_HOSTNAME lcd4_lwmon5
29#else
Wolfgang Denk2ae18242010-10-06 09:05:45 +020030#define CONFIG_SYS_TEXT_BASE 0xFFF80000
Stefan Roesef47b0482013-03-08 16:50:41 +010031#define CONFIG_HOSTNAME lwmon5
Wolfgang Denk2ae18242010-10-06 09:05:45 +020032#endif
33
Stefan Roeseb765ffb2007-06-15 08:18:01 +020034#define CONFIG_SYS_CLK_FREQ 33300000 /* external freq to pll */
35
Stefan Roesea3211482010-11-26 15:45:48 +010036#define CONFIG_4xx_DCACHE /* enable cache in SDRAM */
37
Sascha Lauef14ae412010-08-19 09:38:56 +020038#define CONFIG_BOARD_EARLY_INIT_F /* Call board_early_init_f */
39#define CONFIG_BOARD_EARLY_INIT_R /* Call board_early_init_r */
40#define CONFIG_BOARD_POSTCLK_INIT /* Call board_postclk_init */
41#define CONFIG_MISC_INIT_R /* Call misc_init_r */
42#define CONFIG_BOARD_RESET /* Call board_reset */
Stefan Roeseb765ffb2007-06-15 08:18:01 +020043
Sascha Lauef14ae412010-08-19 09:38:56 +020044/*
Stefan Roeseb765ffb2007-06-15 08:18:01 +020045 * Base addresses -- Note these are effective addresses where the
46 * actual resources get mapped (not physical addresses)
Sascha Lauef14ae412010-08-19 09:38:56 +020047 */
Wolfgang Denk14d0a022010-10-07 21:51:12 +020048#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* Start of U-Boot */
Stefan Roesef47b0482013-03-08 16:50:41 +010049#define CONFIG_SYS_MONITOR_LEN 0x80000
Sascha Lauef14ae412010-08-19 09:38:56 +020050#define CONFIG_SYS_MALLOC_LEN (1 << 20) /* Reserved for malloc */
Stefan Roeseb765ffb2007-06-15 08:18:01 +020051
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020052#define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000
53#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
54#define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH */
Sascha Lauef14ae412010-08-19 09:38:56 +020055#define CONFIG_SYS_LIME_BASE_0 0xc0000000
56#define CONFIG_SYS_LIME_BASE_1 0xc1000000
57#define CONFIG_SYS_LIME_BASE_2 0xc2000000
58#define CONFIG_SYS_LIME_BASE_3 0xc3000000
59#define CONFIG_SYS_FPGA_BASE_0 0xc4000000
60#define CONFIG_SYS_FPGA_BASE_1 0xc4200000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020061#define CONFIG_SYS_OCM_BASE 0xe0010000 /* ocm */
62#define CONFIG_SYS_PCI_BASE 0xe0000000 /* Internal PCI regs */
63#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
Sascha Lauef14ae412010-08-19 09:38:56 +020064#define CONFIG_SYS_PCI_MEMBASE1 (CONFIG_SYS_PCI_MEMBASE + 0x10000000)
65#define CONFIG_SYS_PCI_MEMBASE2 (CONFIG_SYS_PCI_MEMBASE1 + 0x10000000)
66#define CONFIG_SYS_PCI_MEMBASE3 (CONFIG_SYS_PCI_MEMBASE2 + 0x10000000)
Stefan Roeseb765ffb2007-06-15 08:18:01 +020067
Stefan Roesef47b0482013-03-08 16:50:41 +010068#ifndef CONFIG_LCD4_LWMON5
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020069#define CONFIG_SYS_USB2D0_BASE 0xe0000100
70#define CONFIG_SYS_USB_DEVICE 0xe0000000
71#define CONFIG_SYS_USB_HOST 0xe0000400
Stefan Roesef47b0482013-03-08 16:50:41 +010072#endif
Stefan Roeseb765ffb2007-06-15 08:18:01 +020073
Stefan Roese8f24e062008-01-09 10:28:20 +010074/*
Sascha Lauef14ae412010-08-19 09:38:56 +020075 * Initial RAM & stack pointer
76 *
Stefan Roese8f24e062008-01-09 10:28:20 +010077 * On LWMON5 we use D-cache as init-ram and stack pointer. We also move
78 * the POST_WORD from OCM to a 440EPx register that preserves it's
Yuri Tikhonoveb0615b2008-04-24 10:30:53 +020079 * content during reset (GPT0_COMP6). This way we reserve the OCM (16k)
80 * for logbuffer only. (GPT0_COMP1-COMP5 are reserved for logbuffer header.)
Stefan Roese8f24e062008-01-09 10:28:20 +010081 */
Stefan Roesef47b0482013-03-08 16:50:41 +010082#ifndef CONFIG_LCD4_LWMON5
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020083#define CONFIG_SYS_INIT_RAM_DCACHE 1 /* d-cache as init ram */
84#define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* DCache */
Wolfgang Denk553f0982010-10-26 13:32:32 +020085#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
Wolfgang Denk553f0982010-10-26 13:32:32 +020086#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +020087 GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020088#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Stefan Roesef47b0482013-03-08 16:50:41 +010089#else
90#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE
91#define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
92#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
93 GENERATED_GBL_DATA_SIZE)
94#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
95#endif
Sascha Lauef14ae412010-08-19 09:38:56 +020096/* unused GPT0 COMP reg */
Michael Zaidman800eb092010-09-20 08:51:53 +020097#define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP6)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020098#define CONFIG_SYS_OCM_SIZE (16 << 10)
Sascha Lauef14ae412010-08-19 09:38:56 +020099/* 440EPx errata CHIP 11: don't use last 4kbytes */
100#define CONFIG_SYS_MEM_TOP_HIDE (4 << 10)
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200101
Yuri Tikhonov8f15d4a2008-02-04 14:10:42 +0100102/* Additional registers for watchdog timer post test */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200103#define CONFIG_SYS_WATCHDOG_TIME_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_MASK2)
104#define CONFIG_SYS_WATCHDOG_FLAGS_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_MASK1)
105#define CONFIG_SYS_DSPIC_TEST_ADDR CONFIG_SYS_WATCHDOG_FLAGS_ADDR
106#define CONFIG_SYS_OCM_STATUS_ADDR CONFIG_SYS_WATCHDOG_FLAGS_ADDR
107#define CONFIG_SYS_WATCHDOG_MAGIC 0x12480000
108#define CONFIG_SYS_WATCHDOG_MAGIC_MASK 0xFFFF0000
109#define CONFIG_SYS_DSPIC_TEST_MASK 0x00000001
110#define CONFIG_SYS_OCM_STATUS_OK 0x00009A00
111#define CONFIG_SYS_OCM_STATUS_FAIL 0x0000A300
112#define CONFIG_SYS_OCM_STATUS_MASK 0x0000FF00
Yuri Tikhonov8f15d4a2008-02-04 14:10:42 +0100113
Sascha Lauef14ae412010-08-19 09:38:56 +0200114/*
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200115 * Serial Port
Sascha Lauef14ae412010-08-19 09:38:56 +0200116 */
Stefan Roese550650d2010-09-20 16:05:31 +0200117#define CONFIG_CONS_INDEX 2 /* Use UART1 */
118#define CONFIG_SYS_NS16550
119#define CONFIG_SYS_NS16550_SERIAL
120#define CONFIG_SYS_NS16550_REG_SIZE 1
121#define CONFIG_SYS_NS16550_CLK get_serial_clock()
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200122#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external clock provided */
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200123#define CONFIG_BAUDRATE 115200
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200124
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200125#define CONFIG_SYS_BAUDRATE_TABLE \
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200126 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
127
Sascha Lauef14ae412010-08-19 09:38:56 +0200128/*
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200129 * Environment
Sascha Lauef14ae412010-08-19 09:38:56 +0200130 */
131#define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200132
Sascha Lauef14ae412010-08-19 09:38:56 +0200133/*
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200134 * FLASH related
Sascha Lauef14ae412010-08-19 09:38:56 +0200135 */
136#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200137#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200138
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200139#define CONFIG_SYS_FLASH0 0xFC000000
140#define CONFIG_SYS_FLASH1 0xF8000000
141#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 }
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200142
Sascha Lauef14ae412010-08-19 09:38:56 +0200143#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2 /* max number of memory banks */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200145
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200146#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
147#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200148
Sascha Lauef14ae412010-08-19 09:38:56 +0200149#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes (20x faster) */
150#define CONFIG_SYS_FLASH_PROTECTION /* use hardware flash protection */
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200151
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200152#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
Sascha Lauef14ae412010-08-19 09:38:56 +0200153#define CONFIG_SYS_FLASH_QUIET_TEST /* don't warn upon unknown flash */
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200154
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200155#define CONFIG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */
Sascha Lauef14ae412010-08-19 09:38:56 +0200156#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN) - CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200157#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200158
159/* Address and size of Redundant Environment Sector */
Sascha Lauef14ae412010-08-19 09:38:56 +0200160#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200161#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200162
Sascha Lauef14ae412010-08-19 09:38:56 +0200163/*
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200164 * DDR SDRAM
Sascha Lauef14ae412010-08-19 09:38:56 +0200165 */
166#define CONFIG_SYS_MBYTES_SDRAM 256
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200167#define CONFIG_SYS_DDR_CACHED_ADDR 0x40000000 /* setup 2nd TLB cached here */
Sascha Lauef14ae412010-08-19 09:38:56 +0200168#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
Stefan Roesef47b0482013-03-08 16:50:41 +0100169#ifndef CONFIG_LCD4_LWMON5
Sascha Lauef14ae412010-08-19 09:38:56 +0200170#define CONFIG_DDR_ECC /* enable ECC */
Stefan Roesef47b0482013-03-08 16:50:41 +0100171#endif
Pavel Kolesnikov531e3e82007-07-20 15:03:03 +0200172
Stefan Roesef47b0482013-03-08 16:50:41 +0100173#ifndef CONFIG_LCD4_LWMON5
Pavel Kolesnikov531e3e82007-07-20 15:03:03 +0200174/* POST support */
Sascha Lauef14ae412010-08-19 09:38:56 +0200175#define CONFIG_POST (CONFIG_SYS_POST_CACHE | \
176 CONFIG_SYS_POST_CPU | \
177 CONFIG_SYS_POST_ECC | \
178 CONFIG_SYS_POST_ETHER | \
179 CONFIG_SYS_POST_FPU | \
180 CONFIG_SYS_POST_I2C | \
181 CONFIG_SYS_POST_MEMORY | \
182 CONFIG_SYS_POST_OCM | \
183 CONFIG_SYS_POST_RTC | \
184 CONFIG_SYS_POST_SPR | \
185 CONFIG_SYS_POST_UART | \
186 CONFIG_SYS_POST_SYSMON | \
187 CONFIG_SYS_POST_WATCHDOG | \
188 CONFIG_SYS_POST_DSP | \
189 CONFIG_SYS_POST_BSPEC1 | \
190 CONFIG_SYS_POST_BSPEC2 | \
191 CONFIG_SYS_POST_BSPEC3 | \
192 CONFIG_SYS_POST_BSPEC4 | \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200193 CONFIG_SYS_POST_BSPEC5)
Yuri Tikhonov8f15d4a2008-02-04 14:10:42 +0100194
Sascha Lauef14ae412010-08-19 09:38:56 +0200195/* Define here the base-addresses of the UARTs to test in POST */
Stefan Roese5d7c73e2010-09-29 16:58:38 +0200196#define CONFIG_SYS_POST_UART_TABLE { CONFIG_SYS_NS16550_COM1, \
197 CONFIG_SYS_NS16550_COM2 }
Sascha Lauef14ae412010-08-19 09:38:56 +0200198
Stefan Roese834a45d2010-10-07 14:16:25 +0200199#define CONFIG_POST_UART { \
200 "UART test", \
201 "uart", \
202 "This test verifies the UART operation.", \
203 POST_RAM | POST_SLOWTEST | POST_ALWAYS | POST_MANUAL, \
204 &uart_post_test, \
205 NULL, \
206 NULL, \
207 CONFIG_SYS_POST_UART \
208 }
209
Sascha Lauef14ae412010-08-19 09:38:56 +0200210#define CONFIG_POST_WATCHDOG { \
Yuri Tikhonov8f15d4a2008-02-04 14:10:42 +0100211 "Watchdog timer test", \
212 "watchdog", \
213 "This test checks the watchdog timer.", \
214 POST_RAM | POST_POWERON | POST_SLOWTEST | POST_MANUAL | POST_REBOOT, \
215 &lwmon5_watchdog_post_test, \
216 NULL, \
217 NULL, \
Sascha Lauef14ae412010-08-19 09:38:56 +0200218 CONFIG_SYS_POST_WATCHDOG \
Yuri Tikhonov8f15d4a2008-02-04 14:10:42 +0100219 }
220
Sascha Lauef14ae412010-08-19 09:38:56 +0200221#define CONFIG_POST_BSPEC1 { \
Yuri Tikhonov8f15d4a2008-02-04 14:10:42 +0100222 "dsPIC init test", \
223 "dspic_init", \
224 "This test returns result of dsPIC READY test run earlier.", \
225 POST_RAM | POST_ALWAYS, \
226 &dspic_init_post_test, \
227 NULL, \
228 NULL, \
Sascha Lauef14ae412010-08-19 09:38:56 +0200229 CONFIG_SYS_POST_BSPEC1 \
Yuri Tikhonov8f15d4a2008-02-04 14:10:42 +0100230 }
231
Sascha Lauef14ae412010-08-19 09:38:56 +0200232#define CONFIG_POST_BSPEC2 { \
Yuri Tikhonov8f15d4a2008-02-04 14:10:42 +0100233 "dsPIC test", \
234 "dspic", \
235 "This test gets result of dsPIC POST and dsPIC version.", \
236 POST_RAM | POST_ALWAYS, \
237 &dspic_post_test, \
238 NULL, \
239 NULL, \
Sascha Lauef14ae412010-08-19 09:38:56 +0200240 CONFIG_SYS_POST_BSPEC2 \
Yuri Tikhonov8f15d4a2008-02-04 14:10:42 +0100241 }
242
Sascha Lauef14ae412010-08-19 09:38:56 +0200243#define CONFIG_POST_BSPEC3 { \
Yuri Tikhonov8f15d4a2008-02-04 14:10:42 +0100244 "FPGA test", \
245 "fpga", \
246 "This test checks FPGA registers and memory.", \
Sascha Lauef14ae412010-08-19 09:38:56 +0200247 POST_RAM | POST_ALWAYS | POST_MANUAL, \
Yuri Tikhonov8f15d4a2008-02-04 14:10:42 +0100248 &fpga_post_test, \
249 NULL, \
250 NULL, \
Sascha Lauef14ae412010-08-19 09:38:56 +0200251 CONFIG_SYS_POST_BSPEC3 \
Yuri Tikhonov8f15d4a2008-02-04 14:10:42 +0100252 }
253
Sascha Lauef14ae412010-08-19 09:38:56 +0200254#define CONFIG_POST_BSPEC4 { \
Yuri Tikhonov8f15d4a2008-02-04 14:10:42 +0100255 "GDC test", \
256 "gdc", \
257 "This test checks GDC registers and memory.", \
Sascha Lauef14ae412010-08-19 09:38:56 +0200258 POST_RAM | POST_ALWAYS | POST_MANUAL,\
Yuri Tikhonov8f15d4a2008-02-04 14:10:42 +0100259 &gdc_post_test, \
260 NULL, \
261 NULL, \
Sascha Lauef14ae412010-08-19 09:38:56 +0200262 CONFIG_SYS_POST_BSPEC4 \
Yuri Tikhonov8f15d4a2008-02-04 14:10:42 +0100263 }
264
Sascha Lauef14ae412010-08-19 09:38:56 +0200265#define CONFIG_POST_BSPEC5 { \
Yuri Tikhonov8f15d4a2008-02-04 14:10:42 +0100266 "SYSMON1 test", \
267 "sysmon1", \
268 "This test checks GPIO_62_EPX pin indicating power failure.", \
269 POST_RAM | POST_MANUAL | POST_NORMAL | POST_SLOWTEST, \
270 &sysmon1_post_test, \
271 NULL, \
272 NULL, \
Sascha Lauef14ae412010-08-19 09:38:56 +0200273 CONFIG_SYS_POST_BSPEC5 \
Yuri Tikhonov8f15d4a2008-02-04 14:10:42 +0100274 }
Stefan Roese3e4c90c2007-08-10 08:42:55 +0200275
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200276#define CONFIG_SYS_POST_CACHE_ADDR 0x7fff0000 /* free virtual address */
Stefan Roese3e4c90c2007-08-10 08:42:55 +0200277#define CONFIG_LOGBUFFER
Yuri Tikhonoveb0615b2008-04-24 10:30:53 +0200278/* Reserve GPT0_COMP1-COMP5 for logbuffer header */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200279#define CONFIG_ALT_LH_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP1)
280#define CONFIG_ALT_LB_ADDR (CONFIG_SYS_OCM_BASE)
281#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
Stefan Roesef47b0482013-03-08 16:50:41 +0100282#endif
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200283
Sascha Lauef14ae412010-08-19 09:38:56 +0200284/*
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200285 * I2C
Sascha Lauef14ae412010-08-19 09:38:56 +0200286 */
Dirk Eibach880540d2013-04-25 02:40:01 +0000287#define CONFIG_SYS_I2C
288#define CONFIG_SYS_I2C_PPC4XX
289#define CONFIG_SYS_I2C_PPC4XX_CH0
290#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
291#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200292
Sascha Lauef14ae412010-08-19 09:38:56 +0200293#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* RTC */
294#define CONFIG_SYS_I2C_EEPROM_CPU_ADDR 0x52 /* EEPROM (CPU Modul) */
295#define CONFIG_SYS_I2C_EEPROM_MB_ADDR 0x53 /* EEPROM AT24C128 (MainBoard) */
296#define CONFIG_SYS_I2C_DSPIC_ADDR 0x54 /* dsPIC */
297#define CONFIG_SYS_I2C_DSPIC_2_ADDR 0x55 /* dsPIC */
298#define CONFIG_SYS_I2C_DSPIC_KEYB_ADDR 0x56 /* dsPIC */
299#define CONFIG_SYS_I2C_DSPIC_IO_ADDR 0x57 /* dsPIC */
300
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200301#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
302#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* The Atmel AT24C128 has */
Stefan Roesec25dd8f2007-08-23 11:02:37 +0200303 /* 64 byte page write mode using*/
304 /* last 6 bits of the address */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200305#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
Sascha Lauef14ae412010-08-19 09:38:56 +0200306#define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200307
Sascha Lauef14ae412010-08-19 09:38:56 +0200308#define CONFIG_RTC_PCF8563 /* enable Philips PCF8563 RTC */
309#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Philips PCF8563 RTC address */
310#define CONFIG_SYS_I2C_KEYBD_ADDR 0x56 /* PIC LWE keyboard */
311#define CONFIG_SYS_I2C_DSPIC_IO_ADDR 0x57 /* PIC I/O addr */
312
Peter Tyser60aaaa02010-10-22 00:20:30 -0500313#define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_RTC_ADDR, \
314 CONFIG_SYS_I2C_EEPROM_CPU_ADDR,\
315 CONFIG_SYS_I2C_EEPROM_MB_ADDR, \
316 CONFIG_SYS_I2C_DSPIC_ADDR, \
317 CONFIG_SYS_I2C_DSPIC_2_ADDR, \
318 CONFIG_SYS_I2C_DSPIC_KEYB_ADDR,\
319 CONFIG_SYS_I2C_DSPIC_IO_ADDR }
Sascha Lauef14ae412010-08-19 09:38:56 +0200320
321/*
322 * Pass open firmware flat tree
323 */
324#define CONFIG_OF_LIBFDT
325#define CONFIG_OF_BOARD_SETUP
326/* Update size in "reg" property of NOR FLASH device tree nodes */
327#define CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200328
Stefan Roesea3211482010-11-26 15:45:48 +0100329#define CONFIG_FIT /* enable FIT image support */
330
Stefan Roese3ad63872007-08-21 16:27:57 +0200331#define CONFIG_POST_KEY_MAGIC "3C+3E" /* press F3 + F5 keys to force POST */
Stefan Roese3ad63872007-08-21 16:27:57 +0200332
333#define CONFIG_PREBOOT "setenv bootdelay 15"
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200334
335#undef CONFIG_BOOTARGS
336
337#define CONFIG_EXTRA_ENV_SETTINGS \
338 "hostname=lwmon5\0" \
339 "netdev=eth0\0" \
Stefan Roese5d187432007-07-06 11:48:24 +0200340 "unlock=yes\0" \
Stefan Roese3e4c90c2007-08-10 08:42:55 +0200341 "logversion=2\0" \
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200342 "nfsargs=setenv bootargs root=/dev/nfs rw " \
343 "nfsroot=${serverip}:${rootpath}\0" \
344 "ramargs=setenv bootargs root=/dev/ram rw\0" \
345 "addip=setenv bootargs ${bootargs} " \
346 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
347 ":${hostname}:${netdev}:off panic=1\0" \
348 "addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0"\
Stefan Roese04625762007-08-29 16:31:18 +0200349 "addmisc=setenv bootargs ${bootargs} rtc-pcf8563.probe=0,0x51\0"\
350 "flash_nfs=run nfsargs addip addtty addmisc;" \
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200351 "bootm ${kernel_addr}\0" \
Stefan Roese04625762007-08-29 16:31:18 +0200352 "flash_self=run ramargs addip addtty addmisc;" \
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200353 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
Stefan Roese04625762007-08-29 16:31:18 +0200354 "net_nfs=tftp 200000 ${bootfile};" \
355 "run nfsargs addip addtty addmisc;bootm\0" \
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200356 "rootpath=/opt/eldk/ppc_4xxFP\0" \
357 "bootfile=/tftpboot/lwmon5/uImage\0" \
358 "kernel_addr=FC000000\0" \
359 "ramdisk_addr=FC180000\0" \
360 "load=tftp 200000 /tftpboot/${hostname}/u-boot.bin\0" \
361 "update=protect off FFF80000 FFFFFFFF;era FFF80000 FFFFFFFF;" \
362 "cp.b 200000 FFF80000 80000\0" \
Detlev Zundeld8ab58b2008-03-06 16:45:53 +0100363 "upd=run load update\0" \
Stefan Roese334043f2007-07-06 12:26:51 +0200364 "lwe_env=tftp 200000 /tftpboot.dev/lwmon5/env_uboot.bin;" \
Sascha Lauef14ae412010-08-19 09:38:56 +0200365 "autoscr 200000\0" \
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200366 ""
367#define CONFIG_BOOTCOMMAND "run flash_self"
368
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200369#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200370
371#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200372#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200373
Ben Warren96e21f82008-10-27 23:50:15 -0700374#define CONFIG_PPC4xx_EMAC
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200375#define CONFIG_IBM_EMAC4_V4 1
376#define CONFIG_MII 1 /* MII PHY management */
377#define CONFIG_PHY_ADDR 3 /* PHY address, See schematics */
378
379#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
Stefan Roese3ad63872007-08-21 16:27:57 +0200380#define CONFIG_PHY_RESET_DELAY 300
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200381
382#define CONFIG_HAS_ETH0
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200383#define CONFIG_SYS_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200384
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200385#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
386#define CONFIG_PHY1_ADDR 1
387
Anatolij Gustschind610a602008-01-11 15:31:09 +0100388/* Video console */
389#define CONFIG_VIDEO
390#define CONFIG_VIDEO_MB862xx
Anatolij Gustschin5d16ca82009-10-23 12:03:14 +0200391#define CONFIG_VIDEO_MB862xx_ACCEL
Anatolij Gustschind610a602008-01-11 15:31:09 +0100392#define CONFIG_CFB_CONSOLE
393#define CONFIG_VIDEO_LOGO
394#define CONFIG_CONSOLE_EXTRA_INFO
395#define VIDEO_FB_16BPP_PIXEL_SWAP
Wolfgang Grandegger229b6dc2009-10-23 12:03:15 +0200396#define VIDEO_FB_16BPP_WORD_SWAP
Anatolij Gustschind610a602008-01-11 15:31:09 +0100397
398#define CONFIG_VGA_AS_SINGLE_DEVICE
399#define CONFIG_VIDEO_SW_CURSOR
400#define CONFIG_SPLASH_SCREEN
401
Stefan Roesef47b0482013-03-08 16:50:41 +0100402#ifndef CONFIG_LCD4_LWMON5
Stefan Roesea3211482010-11-26 15:45:48 +0100403/*
404 * USB/EHCI
405 */
406#define CONFIG_USB_EHCI /* Enable EHCI USB support */
407#define CONFIG_USB_EHCI_PPC4XX /* on PPC4xx platform */
408#define CONFIG_SYS_PPC4XX_USB_ADDR 0xe0000300
Stefan Roesea3211482010-11-26 15:45:48 +0100409#define CONFIG_EHCI_MMIO_BIG_ENDIAN
410#define CONFIG_EHCI_DESC_BIG_ENDIAN
411#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* re-init HCD after CMD_RESET */
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200412#define CONFIG_USB_STORAGE
413
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200414/* Partitions */
415#define CONFIG_MAC_PARTITION
416#define CONFIG_DOS_PARTITION
417#define CONFIG_ISO_PARTITION
Stefan Roesef47b0482013-03-08 16:50:41 +0100418#endif
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200419
Jon Loeligera22d4da2007-07-08 15:42:59 -0500420/*
Jon Loeliger079a1362007-07-10 10:12:10 -0500421 * BOOTP options
422 */
423#define CONFIG_BOOTP_BOOTFILESIZE
424#define CONFIG_BOOTP_BOOTPATH
425#define CONFIG_BOOTP_GATEWAY
426#define CONFIG_BOOTP_HOSTNAME
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200427
Jon Loeliger079a1362007-07-10 10:12:10 -0500428/*
Jon Loeligera22d4da2007-07-08 15:42:59 -0500429 * Command line configuration.
430 */
Jon Loeligera22d4da2007-07-08 15:42:59 -0500431#define CONFIG_CMD_ASKENV
432#define CONFIG_CMD_DATE
433#define CONFIG_CMD_DHCP
434#define CONFIG_CMD_DIAG
435#define CONFIG_CMD_EEPROM
436#define CONFIG_CMD_ELF
437#define CONFIG_CMD_FAT
438#define CONFIG_CMD_I2C
439#define CONFIG_CMD_IRQ
440#define CONFIG_CMD_MII
Jon Loeligera22d4da2007-07-08 15:42:59 -0500441#define CONFIG_CMD_PING
442#define CONFIG_CMD_REGINFO
443#define CONFIG_CMD_SDRAM
444
Anatolij Gustschind610a602008-01-11 15:31:09 +0100445#ifdef CONFIG_VIDEO
446#define CONFIG_CMD_BMP
447#endif
448
Stefan Roesef47b0482013-03-08 16:50:41 +0100449#ifndef CONFIG_LCD4_LWMON5
Jon Loeligera22d4da2007-07-08 15:42:59 -0500450#ifdef CONFIG_440EPX
451#define CONFIG_CMD_USB
452#endif
Stefan Roesef47b0482013-03-08 16:50:41 +0100453#endif
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200454
Sascha Lauef14ae412010-08-19 09:38:56 +0200455/*
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200456 * Miscellaneous configurable options
Sascha Lauef14ae412010-08-19 09:38:56 +0200457 */
Jon Loeligera22d4da2007-07-08 15:42:59 -0500458#define CONFIG_SUPPORT_VFAT
459
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200460#define CONFIG_SYS_LONGHELP /* undef to save memory */
Wolfgang Denk58d20422008-01-16 00:01:01 +0100461
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200462#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
Wolfgang Denk58d20422008-01-16 00:01:01 +0100463
Jon Loeligera22d4da2007-07-08 15:42:59 -0500464#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200465#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200466#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200467#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200468#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200469#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
470#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
471#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200472
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200473#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
474#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200475
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200476#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
477#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200478
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200479#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
480#define CONFIG_LOOPW 1 /* enable loopw command */
481#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200482#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
483
Stefan Roesef47b0482013-03-08 16:50:41 +0100484#define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup*/
485
486#ifndef CONFIG_LCD4_LWMON5
Sascha Lauef14ae412010-08-19 09:38:56 +0200487#ifndef DEBUG
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200488#define CONFIG_HW_WATCHDOG 1 /* Use external HW-Watchdog */
Sascha Lauef14ae412010-08-19 09:38:56 +0200489#endif
Yuri Tikhonov2e721092008-02-21 14:23:42 +0100490#define CONFIG_WD_PERIOD 40000 /* in usec */
Yuri Tikhonovd32a8742008-04-06 19:19:14 +0200491#define CONFIG_WD_MAX_RATE 66600 /* in ticks */
Stefan Roesef47b0482013-03-08 16:50:41 +0100492#endif
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200493
494/*
495 * For booting Linux, the board info and command line data
Sascha Lauef14ae412010-08-19 09:38:56 +0200496 * have to be in the first 16 MB of memory, since this is
497 * the maximum mapped by the 40x Linux kernel during initialization.
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200498 */
Sascha Lauef14ae412010-08-19 09:38:56 +0200499#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux */
500#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200501
Sascha Lauef14ae412010-08-19 09:38:56 +0200502/*
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200503 * External Bus Controller (EBC) Setup
Sascha Lauef14ae412010-08-19 09:38:56 +0200504 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200505#define CONFIG_SYS_FLASH CONFIG_SYS_FLASH_BASE
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200506
507/* Memory Bank 0 (NOR-FLASH) initialization */
Sascha Lauef14ae412010-08-19 09:38:56 +0200508#define CONFIG_SYS_EBC_PB0AP 0x03000280
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200509#define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH | 0xfc000)
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200510
511/* Memory Bank 1 (Lime) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200512#define CONFIG_SYS_EBC_PB1AP 0x01004380
Sascha Lauef14ae412010-08-19 09:38:56 +0200513#define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_LIME_BASE_0 | 0xbc000)
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200514
515/* Memory Bank 2 (FPGA) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200516#define CONFIG_SYS_EBC_PB2AP 0x01004400
517#define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_FPGA_BASE_0 | 0x1c000)
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200518
519/* Memory Bank 3 (FPGA2) initialization */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200520#define CONFIG_SYS_EBC_PB3AP 0x01004400
521#define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_FPGA_BASE_1 | 0x1c000)
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200522
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200523#define CONFIG_SYS_EBC_CFG 0xb8400000
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200524
Sascha Lauef14ae412010-08-19 09:38:56 +0200525/*
Stefan Roese04e6c382007-07-04 10:06:30 +0200526 * Graphics (Fujitsu Lime)
Sascha Lauef14ae412010-08-19 09:38:56 +0200527 */
528/* SDRAM Clock frequency adjustment register */
529#define CONFIG_SYS_LIME_SDRAM_CLOCK 0xC1FC0038
530#if 1 /* 133MHz is not tested enough, use 100MHz for now */
Anatolij Gustschinb66091d2007-07-26 15:08:01 +0200531/* Lime Clock frequency is to set 100MHz */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200532#define CONFIG_SYS_LIME_CLOCK_100MHZ 0x00000
Sascha Lauef14ae412010-08-19 09:38:56 +0200533#else
Anatolij Gustschinb66091d2007-07-26 15:08:01 +0200534/* Lime Clock frequency for 133MHz */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200535#define CONFIG_SYS_LIME_CLOCK_133MHZ 0x10000
Anatolij Gustschinb66091d2007-07-26 15:08:01 +0200536#endif
Stefan Roese04e6c382007-07-04 10:06:30 +0200537
Sascha Lauef14ae412010-08-19 09:38:56 +0200538/* SDRAM Parameter register */
539#define CONFIG_SYS_LIME_MMR 0xC1FCFFFC
540/*
541 * SDRAM parameter value; was 0x414FB7F2, caused several vertical bars
542 * and pixel flare on display when 133MHz was configured. According to
543 * SDRAM chip datasheet CAS Latency is 3 for 133MHz and -75 Speed
544 * Grade
545 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200546#ifdef CONFIG_SYS_LIME_CLOCK_133MHZ
Wolfgang Grandeggerc28d3bb2009-10-23 12:03:13 +0200547#define CONFIG_SYS_MB862xx_MMR 0x414FB7F3
548#define CONFIG_SYS_MB862xx_CCF CONFIG_SYS_LIME_CLOCK_133MHZ
Anatolij Gustschinb66091d2007-07-26 15:08:01 +0200549#else
Wolfgang Grandeggerc28d3bb2009-10-23 12:03:13 +0200550#define CONFIG_SYS_MB862xx_MMR 0x414FB7F2
551#define CONFIG_SYS_MB862xx_CCF CONFIG_SYS_LIME_CLOCK_100MHZ
Anatolij Gustschinb66091d2007-07-26 15:08:01 +0200552#endif
Stefan Roese04e6c382007-07-04 10:06:30 +0200553
Sascha Lauef14ae412010-08-19 09:38:56 +0200554/*
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200555 * GPIO Setup
Sascha Lauef14ae412010-08-19 09:38:56 +0200556 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200557#define CONFIG_SYS_GPIO_PHY1_RST 12
558#define CONFIG_SYS_GPIO_FLASH_WP 14
559#define CONFIG_SYS_GPIO_PHY0_RST 22
Stefan Roese9055f662013-08-26 12:08:48 +0200560#define CONFIG_SYS_GPIO_PERM_VOLT_FEED 49
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200561#define CONFIG_SYS_GPIO_DSPIC_READY 51
Sascha Lauef14ae412010-08-19 09:38:56 +0200562#define CONFIG_SYS_GPIO_CAN_ENABLE 53
563#define CONFIG_SYS_GPIO_LSB_ENABLE 54
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200564#define CONFIG_SYS_GPIO_EEPROM_EXT_WP 55
565#define CONFIG_SYS_GPIO_HIGHSIDE 56
566#define CONFIG_SYS_GPIO_EEPROM_INT_WP 57
567#define CONFIG_SYS_GPIO_BOARD_RESET 58
568#define CONFIG_SYS_GPIO_LIME_S 59
569#define CONFIG_SYS_GPIO_LIME_RST 60
570#define CONFIG_SYS_GPIO_SYSMON_STATUS 62
571#define CONFIG_SYS_GPIO_WATCHDOG 63
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200572
Stefan Roese9055f662013-08-26 12:08:48 +0200573/* On LCD4, GPIO49 has to be configured to 0 instead of 1 */
574#ifdef CONFIG_LCD4_LWMON5
575#define GPIO49_VAL 0
576#else
577#define GPIO49_VAL 1
578#endif
579
Sascha Lauef14ae412010-08-19 09:38:56 +0200580/*
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200581 * PPC440 GPIO Configuration
582 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200583#define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200584{ \
585/* GPIO Core 0 */ \
586{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \
587{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 EBC_ADDR(6) DMA_ACK(2) */ \
588{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 EBC_ADDR(5) DMA_EOT/TC(2) */ \
589{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 EBC_ADDR(4) DMA_REQ(3) */ \
590{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 EBC_ADDR(3) DMA_ACK(3) */ \
591{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 EBC_ADDR(2) DMA_EOT/TC(3) */ \
592{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 EBC_CS_N(1) */ \
593{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 EBC_CS_N(2) */ \
594{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 EBC_CS_N(3) */ \
595{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 EBC_CS_N(4) */ \
596{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5) */ \
597{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR */ \
598{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO12 */ \
599{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO13 */ \
600{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO14 */ \
Stefan Roese20d500d2007-10-23 10:17:42 +0200601{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO15 */ \
Wolfgang Denk1636d1c2007-06-22 23:59:00 +0200602{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMCTxD(4) */ \
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200603{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMCTxD(5) */ \
604{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMCTxD(6) */ \
605{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 GMCTxD(7) */ \
606{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 RejectPkt0 */ \
607{GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 RejectPkt1 */ \
608{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO22 */ \
609{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 SCPD0 */ \
610{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 GMCTxD(2) */ \
611{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 GMCTxD(3) */ \
612{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO26 */ \
613{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO27 EXT_EBC_REQ USB2D_RXERROR */ \
614{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO28 USB2D_TXVALID */ \
615{GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO29 EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ \
616{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO30 EBC_EXT_ACK USB2D_XCVRSELECT*/ \
617{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/ \
618}, \
619{ \
620/* GPIO Core 1 */ \
621{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO32 USB2D_OPMODE0 EBC_DATA(2) */ \
622{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO33 USB2D_OPMODE1 EBC_DATA(3) */ \
623{GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_0}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
624{GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
625{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N EBC_DATA(0) UART3_SIN*/ \
626{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N EBC_DATA(1) UART3_SOUT*/ \
627{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \
628{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N UART1_SIN */ \
629{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 UIC_IRQ(0) */ \
630{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 UIC_IRQ(1) */ \
631{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 UIC_IRQ(2) */ \
632{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 UIC_IRQ(3) */ \
633{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO44 UIC_IRQ(4) DMA_ACK(1) */ \
634{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO45 UIC_IRQ(6) DMA_EOT/TC(1) */ \
635{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7) DMA_REQ(0) */ \
636{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \
637{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \
Stefan Roese9055f662013-08-26 12:08:48 +0200638{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO49_VAL}, /* GPIO49 Unselect via TraceSelect Bit */ \
Stefan Roese04e6c382007-07-04 10:06:30 +0200639{GPIO1_BASE, GPIO_IN, GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200640{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \
641{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \
Stefan Roese20d500d2007-10-23 10:17:42 +0200642{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO53 Unselect via TraceSelect Bit */ \
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200643{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \
644{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO55 Unselect via TraceSelect Bit */ \
645{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \
646{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO57 Unselect via TraceSelect Bit */ \
Stefan Roese3e954be2007-09-11 14:12:55 +0200647{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200648{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \
649{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \
650{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \
651{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \
652{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \
653} \
654}
655
Jon Loeligera22d4da2007-07-08 15:42:59 -0500656#if defined(CONFIG_CMD_KGDB)
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200657#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200658#endif
Stefan Roesef47b0482013-03-08 16:50:41 +0100659
660/*
661 * SPL related defines
662 */
663#ifdef CONFIG_LCD4_LWMON5
Stefan Roesef47b0482013-03-08 16:50:41 +0100664#define CONFIG_SPL_FRAMEWORK
665#define CONFIG_SPL_BOARD_INIT
666#define CONFIG_SPL_NOR_SUPPORT
667#define CONFIG_SPL_TEXT_BASE 0xffff0000 /* last 64 KiB for SPL */
668#define CONFIG_SYS_SPL_MAX_LEN (64 << 10)
669#define CONFIG_UBOOT_PAD_TO 458752 /* decimal for 'dd' */
Stefan Roesef47b0482013-03-08 16:50:41 +0100670#define CONFIG_SPL_LIBCOMMON_SUPPORT /* image.c */
671#define CONFIG_SPL_LIBGENERIC_SUPPORT /* string.c */
672#define CONFIG_SPL_SERIAL_SUPPORT
673
674/* Place BSS for SPL near end of SDRAM */
675#define CONFIG_SPL_BSS_START_ADDR ((256 - 1) << 20)
676#define CONFIG_SPL_BSS_MAX_SIZE (64 << 10)
677
678#define CONFIG_SPL_OS_BOOT
679/* Place patched DT blob (fdt) at this address */
680#define CONFIG_SYS_SPL_ARGS_ADDR 0x01800000
681
682#define CONFIG_SPL_TARGET "u-boot-img-spl-at-end.bin"
683
684/* Settings for real U-Boot to be loaded from NOR flash */
685#define CONFIG_SYS_UBOOT_BASE (-CONFIG_SYS_MONITOR_LEN)
686#define CONFIG_SYS_UBOOT_START 0x01002100
687
688#define CONFIG_SYS_OS_BASE 0xf8000000
689#define CONFIG_SYS_FDT_BASE 0xf87c0000
690#endif
691
Stefan Roeseb765ffb2007-06-15 08:18:01 +0200692#endif /* __CONFIG_H */