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Tom Warren74652cf2011-04-14 12:18:06 +00001/*
2* (C) Copyright 2010-2011
3* NVIDIA Corporation <www.nvidia.com>
4*
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Tom Warren74652cf2011-04-14 12:18:06 +00006*/
Tom Warrenb2871032012-12-11 13:34:15 +00007
8/* Tegra AP (Application Processor) code */
9
Tom Warren74652cf2011-04-14 12:18:06 +000010#include <common.h>
Tom Warren150c2492012-09-19 15:50:56 -070011#include <asm/io.h>
12#include <asm/arch/gp_padctrl.h>
13#include <asm/arch-tegra/ap.h>
Tom Warrenb2871032012-12-11 13:34:15 +000014#include <asm/arch-tegra/clock.h>
Tom Warren150c2492012-09-19 15:50:56 -070015#include <asm/arch-tegra/fuse.h>
16#include <asm/arch-tegra/pmc.h>
17#include <asm/arch-tegra/scu.h>
Tom Warrene23bb6a2013-01-28 13:32:10 +000018#include <asm/arch-tegra/tegra.h>
Tom Warren150c2492012-09-19 15:50:56 -070019#include <asm/arch-tegra/warmboot.h>
Tom Warren74652cf2011-04-14 12:18:06 +000020
Tom Warren49493cb2013-04-10 10:32:32 -070021int tegra_get_chip(void)
Simon Glassd5153622012-04-02 13:18:50 +000022{
Tom Warren49493cb2013-04-10 10:32:32 -070023 int rev;
24 struct apb_misc_gp_ctlr *gp =
25 (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
Simon Glassd5153622012-04-02 13:18:50 +000026
27 /*
28 * This is undocumented, Chip ID is bits 15:8 of the register
29 * APB_MISC + 0x804, and has value 0x20 for Tegra20, 0x30 for
Tom Warrene23bb6a2013-01-28 13:32:10 +000030 * Tegra30, and 0x35 for T114.
Simon Glassd5153622012-04-02 13:18:50 +000031 */
Simon Glassd5153622012-04-02 13:18:50 +000032 rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT;
Tom Warren49493cb2013-04-10 10:32:32 -070033 debug("%s: CHIPID is 0x%02X\n", __func__, rev);
Simon Glassd5153622012-04-02 13:18:50 +000034
Tom Warren49493cb2013-04-10 10:32:32 -070035 return rev;
36}
Simon Glassd5153622012-04-02 13:18:50 +000037
Tom Warren49493cb2013-04-10 10:32:32 -070038int tegra_get_sku_info(void)
39{
40 int sku_id;
41 struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE;
42
43 sku_id = readl(&fuse->sku_info) & 0xff;
44 debug("%s: SKU info byte is 0x%02X\n", __func__, sku_id);
45
46 return sku_id;
47}
48
49int tegra_get_chip_sku(void)
50{
51 uint sku_id, chip_id;
52
53 chip_id = tegra_get_chip();
54 sku_id = tegra_get_sku_info();
55
56 switch (chip_id) {
Allen Martin00a27492012-08-31 08:30:00 +000057 case CHIPID_TEGRA20:
Tom Warren49493cb2013-04-10 10:32:32 -070058 switch (sku_id) {
Stephen Warren20583d02013-05-17 14:10:15 +000059 case SKU_ID_T20_7:
Simon Glassd5153622012-04-02 13:18:50 +000060 case SKU_ID_T20:
61 return TEGRA_SOC_T20;
62 case SKU_ID_T25SE:
63 case SKU_ID_AP25:
64 case SKU_ID_T25:
65 case SKU_ID_AP25E:
66 case SKU_ID_T25E:
67 return TEGRA_SOC_T25;
68 }
69 break;
Tom Warrenb2871032012-12-11 13:34:15 +000070 case CHIPID_TEGRA30:
Tom Warren49493cb2013-04-10 10:32:32 -070071 switch (sku_id) {
Stephen Warreneb222d12013-03-27 09:37:02 +000072 case SKU_ID_T33:
Tom Warrenb2871032012-12-11 13:34:15 +000073 case SKU_ID_T30:
Alban Bedel3346cbb2013-11-13 17:27:18 +010074 case SKU_ID_TM30MQS_P_A3:
Tom Warrenb2871032012-12-11 13:34:15 +000075 return TEGRA_SOC_T30;
76 }
77 break;
Tom Warrene23bb6a2013-01-28 13:32:10 +000078 case CHIPID_TEGRA114:
Tom Warren49493cb2013-04-10 10:32:32 -070079 switch (sku_id) {
Tom Warrene23bb6a2013-01-28 13:32:10 +000080 case SKU_ID_T114_ENG:
Stephen Warren840167c2013-05-17 14:10:14 +000081 case SKU_ID_T114_1:
Tom Warrene23bb6a2013-01-28 13:32:10 +000082 return TEGRA_SOC_T114;
83 }
84 break;
Simon Glassd5153622012-04-02 13:18:50 +000085 }
Tom Warren49493cb2013-04-10 10:32:32 -070086 /* unknown chip/sku id */
87 printf("%s: ERROR: UNKNOWN CHIP/SKU ID COMBO (0x%02X/0x%02X)\n",
88 __func__, chip_id, sku_id);
Simon Glassd5153622012-04-02 13:18:50 +000089 return TEGRA_SOC_UNKNOWN;
90}
91
Allen Martin12b7b702012-08-31 08:30:12 +000092static void enable_scu(void)
Tom Warren74652cf2011-04-14 12:18:06 +000093{
94 struct scu_ctlr *scu = (struct scu_ctlr *)NV_PA_ARM_PERIPHBASE;
95 u32 reg;
96
Tom Warrendbc000b2013-05-23 12:26:18 +000097 /* Only enable the SCU on T20/T25 */
98 if (tegra_get_chip() != CHIPID_TEGRA20)
99 return;
100
Tom Warren74652cf2011-04-14 12:18:06 +0000101 /* If SCU already setup/enabled, return */
102 if (readl(&scu->scu_ctrl) & SCU_CTRL_ENABLE)
103 return;
104
105 /* Invalidate all ways for all processors */
106 writel(0xFFFF, &scu->scu_inv_all);
107
108 /* Enable SCU - bit 0 */
109 reg = readl(&scu->scu_ctrl);
110 reg |= SCU_CTRL_ENABLE;
111 writel(reg, &scu->scu_ctrl);
112}
113
Tom Warren76e350b2012-05-30 14:06:09 -0700114static u32 get_odmdata(void)
115{
116 /*
117 * ODMDATA is stored in the BCT in IRAM by the BootROM.
118 * The BCT start and size are stored in the BIT in IRAM.
119 * Read the data @ bct_start + (bct_size - 12). This works
120 * on T20 and T30 BCTs, which are locked down. If this changes
121 * in new chips (T114, etc.), we can revisit this algorithm.
122 */
123
124 u32 bct_start, odmdata;
125
Tom Warrenb2871032012-12-11 13:34:15 +0000126 bct_start = readl(NV_PA_BASE_SRAM + NVBOOTINFOTABLE_BCTPTR);
Tom Warren76e350b2012-05-30 14:06:09 -0700127 odmdata = readl(bct_start + BCT_ODMDATA_OFFSET);
128
129 return odmdata;
130}
131
Allen Martin12b7b702012-08-31 08:30:12 +0000132static void init_pmc_scratch(void)
Tom Warren74652cf2011-04-14 12:18:06 +0000133{
Tom Warren29f3e3f2012-09-04 17:00:24 -0700134 struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
Tom Warren76e350b2012-05-30 14:06:09 -0700135 u32 odmdata;
Tom Warren74652cf2011-04-14 12:18:06 +0000136 int i;
137
138 /* SCRATCH0 is initialized by the boot ROM and shouldn't be cleared */
139 for (i = 0; i < 23; i++)
140 writel(0, &pmc->pmc_scratch1+i);
141
142 /* ODMDATA is for kernel use to determine RAM size, LP config, etc. */
Tom Warren76e350b2012-05-30 14:06:09 -0700143 odmdata = get_odmdata();
144 writel(odmdata, &pmc->pmc_scratch20);
Tom Warren74652cf2011-04-14 12:18:06 +0000145}
146
Allen Martin12b7b702012-08-31 08:30:12 +0000147void s_init(void)
Tom Warren74652cf2011-04-14 12:18:06 +0000148{
Simon Glass210576f2011-11-05 03:56:50 +0000149 /* Init PMC scratch memory */
150 init_pmc_scratch();
Tom Warren74652cf2011-04-14 12:18:06 +0000151
Simon Glass210576f2011-11-05 03:56:50 +0000152 enable_scu();
153
Tom Warrend0edce42013-03-25 16:22:26 -0700154 /* init the cache */
155 config_cache();
Tom Warren74652cf2011-04-14 12:18:06 +0000156}