Tom Warren | 74652cf | 2011-04-14 12:18:06 +0000 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2010-2011 |
| 3 | * NVIDIA Corporation <www.nvidia.com> |
| 4 | * |
Wolfgang Denk | 1a45966 | 2013-07-08 09:37:19 +0200 | [diff] [blame] | 5 | * SPDX-License-Identifier: GPL-2.0+ |
Tom Warren | 74652cf | 2011-04-14 12:18:06 +0000 | [diff] [blame] | 6 | */ |
Tom Warren | b287103 | 2012-12-11 13:34:15 +0000 | [diff] [blame] | 7 | |
| 8 | /* Tegra AP (Application Processor) code */ |
| 9 | |
Tom Warren | 74652cf | 2011-04-14 12:18:06 +0000 | [diff] [blame] | 10 | #include <common.h> |
Tom Warren | 150c249 | 2012-09-19 15:50:56 -0700 | [diff] [blame] | 11 | #include <asm/io.h> |
| 12 | #include <asm/arch/gp_padctrl.h> |
| 13 | #include <asm/arch-tegra/ap.h> |
Tom Warren | b287103 | 2012-12-11 13:34:15 +0000 | [diff] [blame] | 14 | #include <asm/arch-tegra/clock.h> |
Tom Warren | 150c249 | 2012-09-19 15:50:56 -0700 | [diff] [blame] | 15 | #include <asm/arch-tegra/fuse.h> |
| 16 | #include <asm/arch-tegra/pmc.h> |
| 17 | #include <asm/arch-tegra/scu.h> |
Tom Warren | e23bb6a | 2013-01-28 13:32:10 +0000 | [diff] [blame] | 18 | #include <asm/arch-tegra/tegra.h> |
Tom Warren | 150c249 | 2012-09-19 15:50:56 -0700 | [diff] [blame] | 19 | #include <asm/arch-tegra/warmboot.h> |
Tom Warren | 74652cf | 2011-04-14 12:18:06 +0000 | [diff] [blame] | 20 | |
Tom Warren | 49493cb | 2013-04-10 10:32:32 -0700 | [diff] [blame] | 21 | int tegra_get_chip(void) |
Simon Glass | d515362 | 2012-04-02 13:18:50 +0000 | [diff] [blame] | 22 | { |
Tom Warren | 49493cb | 2013-04-10 10:32:32 -0700 | [diff] [blame] | 23 | int rev; |
| 24 | struct apb_misc_gp_ctlr *gp = |
| 25 | (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE; |
Simon Glass | d515362 | 2012-04-02 13:18:50 +0000 | [diff] [blame] | 26 | |
| 27 | /* |
| 28 | * This is undocumented, Chip ID is bits 15:8 of the register |
| 29 | * APB_MISC + 0x804, and has value 0x20 for Tegra20, 0x30 for |
Tom Warren | e23bb6a | 2013-01-28 13:32:10 +0000 | [diff] [blame] | 30 | * Tegra30, and 0x35 for T114. |
Simon Glass | d515362 | 2012-04-02 13:18:50 +0000 | [diff] [blame] | 31 | */ |
Simon Glass | d515362 | 2012-04-02 13:18:50 +0000 | [diff] [blame] | 32 | rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT; |
Tom Warren | 49493cb | 2013-04-10 10:32:32 -0700 | [diff] [blame] | 33 | debug("%s: CHIPID is 0x%02X\n", __func__, rev); |
Simon Glass | d515362 | 2012-04-02 13:18:50 +0000 | [diff] [blame] | 34 | |
Tom Warren | 49493cb | 2013-04-10 10:32:32 -0700 | [diff] [blame] | 35 | return rev; |
| 36 | } |
Simon Glass | d515362 | 2012-04-02 13:18:50 +0000 | [diff] [blame] | 37 | |
Tom Warren | 49493cb | 2013-04-10 10:32:32 -0700 | [diff] [blame] | 38 | int tegra_get_sku_info(void) |
| 39 | { |
| 40 | int sku_id; |
| 41 | struct fuse_regs *fuse = (struct fuse_regs *)NV_PA_FUSE_BASE; |
| 42 | |
| 43 | sku_id = readl(&fuse->sku_info) & 0xff; |
| 44 | debug("%s: SKU info byte is 0x%02X\n", __func__, sku_id); |
| 45 | |
| 46 | return sku_id; |
| 47 | } |
| 48 | |
| 49 | int tegra_get_chip_sku(void) |
| 50 | { |
| 51 | uint sku_id, chip_id; |
| 52 | |
| 53 | chip_id = tegra_get_chip(); |
| 54 | sku_id = tegra_get_sku_info(); |
| 55 | |
| 56 | switch (chip_id) { |
Allen Martin | 00a2749 | 2012-08-31 08:30:00 +0000 | [diff] [blame] | 57 | case CHIPID_TEGRA20: |
Tom Warren | 49493cb | 2013-04-10 10:32:32 -0700 | [diff] [blame] | 58 | switch (sku_id) { |
Stephen Warren | 20583d0 | 2013-05-17 14:10:15 +0000 | [diff] [blame] | 59 | case SKU_ID_T20_7: |
Simon Glass | d515362 | 2012-04-02 13:18:50 +0000 | [diff] [blame] | 60 | case SKU_ID_T20: |
| 61 | return TEGRA_SOC_T20; |
| 62 | case SKU_ID_T25SE: |
| 63 | case SKU_ID_AP25: |
| 64 | case SKU_ID_T25: |
| 65 | case SKU_ID_AP25E: |
| 66 | case SKU_ID_T25E: |
| 67 | return TEGRA_SOC_T25; |
| 68 | } |
| 69 | break; |
Tom Warren | b287103 | 2012-12-11 13:34:15 +0000 | [diff] [blame] | 70 | case CHIPID_TEGRA30: |
Tom Warren | 49493cb | 2013-04-10 10:32:32 -0700 | [diff] [blame] | 71 | switch (sku_id) { |
Stephen Warren | eb222d1 | 2013-03-27 09:37:02 +0000 | [diff] [blame] | 72 | case SKU_ID_T33: |
Tom Warren | b287103 | 2012-12-11 13:34:15 +0000 | [diff] [blame] | 73 | case SKU_ID_T30: |
Alban Bedel | 3346cbb | 2013-11-13 17:27:18 +0100 | [diff] [blame] | 74 | case SKU_ID_TM30MQS_P_A3: |
Tom Warren | b287103 | 2012-12-11 13:34:15 +0000 | [diff] [blame] | 75 | return TEGRA_SOC_T30; |
| 76 | } |
| 77 | break; |
Tom Warren | e23bb6a | 2013-01-28 13:32:10 +0000 | [diff] [blame] | 78 | case CHIPID_TEGRA114: |
Tom Warren | 49493cb | 2013-04-10 10:32:32 -0700 | [diff] [blame] | 79 | switch (sku_id) { |
Tom Warren | e23bb6a | 2013-01-28 13:32:10 +0000 | [diff] [blame] | 80 | case SKU_ID_T114_ENG: |
Stephen Warren | 840167c | 2013-05-17 14:10:14 +0000 | [diff] [blame] | 81 | case SKU_ID_T114_1: |
Tom Warren | e23bb6a | 2013-01-28 13:32:10 +0000 | [diff] [blame] | 82 | return TEGRA_SOC_T114; |
| 83 | } |
| 84 | break; |
Simon Glass | d515362 | 2012-04-02 13:18:50 +0000 | [diff] [blame] | 85 | } |
Tom Warren | 49493cb | 2013-04-10 10:32:32 -0700 | [diff] [blame] | 86 | /* unknown chip/sku id */ |
| 87 | printf("%s: ERROR: UNKNOWN CHIP/SKU ID COMBO (0x%02X/0x%02X)\n", |
| 88 | __func__, chip_id, sku_id); |
Simon Glass | d515362 | 2012-04-02 13:18:50 +0000 | [diff] [blame] | 89 | return TEGRA_SOC_UNKNOWN; |
| 90 | } |
| 91 | |
Allen Martin | 12b7b70 | 2012-08-31 08:30:12 +0000 | [diff] [blame] | 92 | static void enable_scu(void) |
Tom Warren | 74652cf | 2011-04-14 12:18:06 +0000 | [diff] [blame] | 93 | { |
| 94 | struct scu_ctlr *scu = (struct scu_ctlr *)NV_PA_ARM_PERIPHBASE; |
| 95 | u32 reg; |
| 96 | |
Tom Warren | dbc000b | 2013-05-23 12:26:18 +0000 | [diff] [blame] | 97 | /* Only enable the SCU on T20/T25 */ |
| 98 | if (tegra_get_chip() != CHIPID_TEGRA20) |
| 99 | return; |
| 100 | |
Tom Warren | 74652cf | 2011-04-14 12:18:06 +0000 | [diff] [blame] | 101 | /* If SCU already setup/enabled, return */ |
| 102 | if (readl(&scu->scu_ctrl) & SCU_CTRL_ENABLE) |
| 103 | return; |
| 104 | |
| 105 | /* Invalidate all ways for all processors */ |
| 106 | writel(0xFFFF, &scu->scu_inv_all); |
| 107 | |
| 108 | /* Enable SCU - bit 0 */ |
| 109 | reg = readl(&scu->scu_ctrl); |
| 110 | reg |= SCU_CTRL_ENABLE; |
| 111 | writel(reg, &scu->scu_ctrl); |
| 112 | } |
| 113 | |
Tom Warren | 76e350b | 2012-05-30 14:06:09 -0700 | [diff] [blame] | 114 | static u32 get_odmdata(void) |
| 115 | { |
| 116 | /* |
| 117 | * ODMDATA is stored in the BCT in IRAM by the BootROM. |
| 118 | * The BCT start and size are stored in the BIT in IRAM. |
| 119 | * Read the data @ bct_start + (bct_size - 12). This works |
| 120 | * on T20 and T30 BCTs, which are locked down. If this changes |
| 121 | * in new chips (T114, etc.), we can revisit this algorithm. |
| 122 | */ |
| 123 | |
| 124 | u32 bct_start, odmdata; |
| 125 | |
Tom Warren | b287103 | 2012-12-11 13:34:15 +0000 | [diff] [blame] | 126 | bct_start = readl(NV_PA_BASE_SRAM + NVBOOTINFOTABLE_BCTPTR); |
Tom Warren | 76e350b | 2012-05-30 14:06:09 -0700 | [diff] [blame] | 127 | odmdata = readl(bct_start + BCT_ODMDATA_OFFSET); |
| 128 | |
| 129 | return odmdata; |
| 130 | } |
| 131 | |
Allen Martin | 12b7b70 | 2012-08-31 08:30:12 +0000 | [diff] [blame] | 132 | static void init_pmc_scratch(void) |
Tom Warren | 74652cf | 2011-04-14 12:18:06 +0000 | [diff] [blame] | 133 | { |
Tom Warren | 29f3e3f | 2012-09-04 17:00:24 -0700 | [diff] [blame] | 134 | struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE; |
Tom Warren | 76e350b | 2012-05-30 14:06:09 -0700 | [diff] [blame] | 135 | u32 odmdata; |
Tom Warren | 74652cf | 2011-04-14 12:18:06 +0000 | [diff] [blame] | 136 | int i; |
| 137 | |
| 138 | /* SCRATCH0 is initialized by the boot ROM and shouldn't be cleared */ |
| 139 | for (i = 0; i < 23; i++) |
| 140 | writel(0, &pmc->pmc_scratch1+i); |
| 141 | |
| 142 | /* ODMDATA is for kernel use to determine RAM size, LP config, etc. */ |
Tom Warren | 76e350b | 2012-05-30 14:06:09 -0700 | [diff] [blame] | 143 | odmdata = get_odmdata(); |
| 144 | writel(odmdata, &pmc->pmc_scratch20); |
Tom Warren | 74652cf | 2011-04-14 12:18:06 +0000 | [diff] [blame] | 145 | } |
| 146 | |
Allen Martin | 12b7b70 | 2012-08-31 08:30:12 +0000 | [diff] [blame] | 147 | void s_init(void) |
Tom Warren | 74652cf | 2011-04-14 12:18:06 +0000 | [diff] [blame] | 148 | { |
Simon Glass | 210576f | 2011-11-05 03:56:50 +0000 | [diff] [blame] | 149 | /* Init PMC scratch memory */ |
| 150 | init_pmc_scratch(); |
Tom Warren | 74652cf | 2011-04-14 12:18:06 +0000 | [diff] [blame] | 151 | |
Simon Glass | 210576f | 2011-11-05 03:56:50 +0000 | [diff] [blame] | 152 | enable_scu(); |
| 153 | |
Tom Warren | d0edce4 | 2013-03-25 16:22:26 -0700 | [diff] [blame] | 154 | /* init the cache */ |
| 155 | config_cache(); |
Tom Warren | 74652cf | 2011-04-14 12:18:06 +0000 | [diff] [blame] | 156 | } |