Adam Ford | f36f8bc | 2020-05-03 08:11:33 -0500 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ |
| 2 | /* |
| 3 | * Copyright 2020 Compass Electronics Group, LLC |
| 4 | */ |
| 5 | |
| 6 | / { |
| 7 | wdt-reboot { |
| 8 | compatible = "wdt-reboot"; |
| 9 | wdt = <&wdog1>; |
| 10 | u-boot,dm-spl; |
| 11 | }; |
| 12 | }; |
| 13 | |
| 14 | &{/soc@0} { |
| 15 | u-boot,dm-pre-reloc; |
| 16 | u-boot,dm-spl; |
| 17 | }; |
| 18 | |
| 19 | &aips1 { |
| 20 | u-boot,dm-spl; |
| 21 | u-boot,dm-pre-reloc; |
| 22 | }; |
| 23 | |
| 24 | &aips2 { |
| 25 | u-boot,dm-spl; |
| 26 | }; |
| 27 | |
| 28 | &aips3 { |
| 29 | u-boot,dm-spl; |
| 30 | }; |
| 31 | |
| 32 | &clk { |
| 33 | u-boot,dm-spl; |
| 34 | u-boot,dm-pre-reloc; |
| 35 | /delete-property/ assigned-clocks; |
| 36 | /delete-property/ assigned-clock-parents; |
| 37 | /delete-property/ assigned-clock-rates; |
| 38 | }; |
| 39 | |
| 40 | &fec1 { |
| 41 | phy-reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; |
| 42 | }; |
| 43 | |
| 44 | &gpio1 { |
| 45 | u-boot,dm-spl; |
| 46 | }; |
| 47 | |
| 48 | &gpio2 { |
| 49 | u-boot,dm-spl; |
| 50 | }; |
| 51 | |
| 52 | &gpio3 { |
| 53 | u-boot,dm-spl; |
| 54 | }; |
| 55 | |
| 56 | &gpio4 { |
| 57 | u-boot,dm-spl; |
| 58 | }; |
| 59 | |
| 60 | &gpio5 { |
| 61 | u-boot,dm-spl; |
| 62 | }; |
| 63 | |
| 64 | &iomuxc { |
| 65 | u-boot,dm-spl; |
| 66 | }; |
| 67 | |
| 68 | &osc_24m { |
| 69 | u-boot,dm-spl; |
| 70 | u-boot,dm-pre-reloc; |
| 71 | }; |
| 72 | |
| 73 | &pca6416_0 { |
| 74 | compatible = "ti,tca6416"; |
| 75 | }; |
| 76 | |
| 77 | &pca6416_1 { |
| 78 | compatible = "ti,tca6416"; |
| 79 | }; |
| 80 | |
| 81 | &pinctrl_i2c1 { |
| 82 | u-boot,dm-spl; |
| 83 | }; |
| 84 | |
| 85 | &pinctrl_pmic { |
| 86 | u-boot,dm-spl; |
| 87 | }; |
| 88 | |
| 89 | &pinctrl_uart2 { |
| 90 | u-boot,dm-spl; |
| 91 | }; |
| 92 | |
| 93 | &pinctrl_usdhc2_gpio { |
| 94 | u-boot,dm-spl; |
| 95 | }; |
| 96 | |
| 97 | &pinctrl_usdhc2 { |
| 98 | u-boot,dm-spl; |
| 99 | }; |
| 100 | |
| 101 | &pinctrl_usdhc3 { |
| 102 | u-boot,dm-spl; |
| 103 | }; |
| 104 | |
| 105 | &uart2 { |
| 106 | u-boot,dm-spl; |
| 107 | }; |
| 108 | |
| 109 | &usdhc2 { |
| 110 | u-boot,dm-spl; |
| 111 | }; |
| 112 | |
| 113 | &usdhc3 { |
| 114 | u-boot,dm-spl; |
| 115 | }; |
| 116 | |
| 117 | &i2c1 { |
| 118 | u-boot,dm-spl; |
| 119 | }; |
| 120 | |
| 121 | &{/soc@0/bus@30800000/i2c@30a20000/pmic@4b} { |
| 122 | u-boot,dm-spl; |
| 123 | }; |
| 124 | |
| 125 | &{/soc@0/bus@30800000/i2c@30a20000/pmic@4b/regulators} { |
| 126 | u-boot,dm-spl; |
| 127 | }; |
| 128 | |
| 129 | &wdog1 { |
| 130 | u-boot,dm-spl; |
| 131 | }; |