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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Stefano Babic8be4f402016-06-06 11:19:42 +02002/*
3 * Copyright (C) Stefano Babic <sbabic@denx.de>
4 *
5 * Configuration settings for the E+L i.MX6Q DO82 board.
Stefano Babic8be4f402016-06-06 11:19:42 +02006 */
7
8#ifndef __EL6Q_COMMON_CONFIG_H
9#define __EL6Q_COMMON_CONFIG_H
10
11#define CONFIG_BOARD_NAME EL6Q
12
Stefano Babic8be4f402016-06-06 11:19:42 +020013#include "mx6_common.h"
14
15#define CONFIG_IMX_THERMAL
16
17/* Size of malloc() pool */
18#define CONFIG_SYS_MALLOC_LEN (10 * SZ_1M)
19
Stefano Babic8be4f402016-06-06 11:19:42 +020020#define CONFIG_MXC_UART
21
22#ifdef CONFIG_SPL
Stefano Babic8be4f402016-06-06 11:19:42 +020023#define CONFIG_SYS_SPI_U_BOOT_OFFS (64 * 1024)
Stefano Babic8be4f402016-06-06 11:19:42 +020024#include "imx6_spl.h"
25#endif
26
27/* MMC Configs */
28#define CONFIG_SYS_FSL_ESDHC_ADDR 0
29#define CONFIG_SYS_FSL_USDHC_NUM 2
30
31/* I2C config */
32#define CONFIG_SYS_I2C
33#define CONFIG_SYS_I2C_MXC
34#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
35#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
36#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
37#define CONFIG_SYS_I2C_SPEED 100000
38
39/* PMIC */
40#define CONFIG_POWER
41#define CONFIG_POWER_I2C
42#define CONFIG_POWER_PFUZE100
43#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
44
45/* Commands */
Stefano Babic8be4f402016-06-06 11:19:42 +020046#define CONFIG_SF_DEFAULT_BUS 3
47#define CONFIG_SF_DEFAULT_CS 0
48#define CONFIG_SF_DEFAULT_SPEED 20000000
49#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
50
51/* allow to overwrite serial and ethaddr */
52#define CONFIG_ENV_OVERWRITE
53#define CONFIG_MXC_UART_BASE UART2_BASE
Stefano Babic8be4f402016-06-06 11:19:42 +020054
Stefano Babic8be4f402016-06-06 11:19:42 +020055#define CONFIG_BOARD_NAME EL6Q
56
Stefano Babic8be4f402016-06-06 11:19:42 +020057#define CONFIG_EXTRA_ENV_SETTINGS \
58 "board="__stringify(CONFIG_BOARD_NAME)"\0" \
59 "cma_size="__stringify(EL6Q_CMA_SIZE)"\0" \
60 "chp_size="__stringify(EL6Q_COHERENT_POOL_SIZE)"\0" \
Simon Glass12ca05a2016-10-17 20:12:39 -060061 "console=" CONSOLE_DEV "\0" \
Stefano Babic8be4f402016-06-06 11:19:42 +020062 "fdtfile=undefined\0" \
63 "fdt_high=0xffffffff\0" \
64 "fdt_addr_r=0x18000000\0" \
65 "fdt_addr=0x18000000\0" \
66 "findfdt=setenv fdtfile " CONFIG_DEFAULT_FDT_FILE "\0" \
67 "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
68 "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \
69 "pxefile_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \
70 BOOTENV
71
72#define BOOT_TARGET_DEVICES(func) \
73 func(MMC, mmc, 0) \
74 func(MMC, mmc, 1) \
75 func(PXE, PXE, na) \
76 func(DHCP, dhcp, na)
77
Stefano Babic8be4f402016-06-06 11:19:42 +020078#include <config_distro_bootcmd.h>
79
80#define CONFIG_ARP_TIMEOUT 200UL
81
Stefano Babic8be4f402016-06-06 11:19:42 +020082#define CONFIG_SYS_MEMTEST_START 0x10000000
83#define CONFIG_SYS_MEMTEST_END 0x10800000
84#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000
85
Stefano Babic8be4f402016-06-06 11:19:42 +020086/* Physical Memory Map */
Stefano Babic8be4f402016-06-06 11:19:42 +020087#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
88
89#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
90#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
91#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
92
93#define CONFIG_SYS_INIT_SP_OFFSET \
94 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
95#define CONFIG_SYS_INIT_SP_ADDR \
96 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
97
Masahiro Yamadae856bdc2017-02-11 22:43:54 +090098/* environment organization */
Stefano Babic8be4f402016-06-06 11:19:42 +020099
100#define CONFIG_ENV_SIZE (8 * 1024)
101
Stefano Babic8be4f402016-06-06 11:19:42 +0200102#if defined(CONFIG_ENV_IS_IN_MMC)
103#define CONFIG_SYS_MMC_ENV_DEV 1
104#define CONFIG_SYS_MMC_ENV_PART 2
105#define CONFIG_ENV_OFFSET 0x0
106#endif
107
108#endif /* __EL6Q_COMMON_CONFIG_H */