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wdenk855a4962004-03-14 18:23:55 +00001/*
2 * (C) Copyright 2002
3 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
4 * Marius Groeger <mgroeger@sysgo.de>
5 *
6 * 2003-2004 (c) MontaVista Software, Inc.
7 *
8 * Configuation settings for the ADS GraphicsClient+ board.
9 *
10 * See file CREDITS for list of people who contributed to this
11 * project.
12 *
13 * This program is free software; you can redistribute it and/or
14 * modify it under the terms of the GNU General Public License as
15 * published by the Free Software Foundation; either version 2 of
16 * the License, or (at your option) any later version.
17 *
18 * This program is distributed in the hope that it will be useful,
19 * but WITHOUT ANY WARRANTY; without even the implied warranty of
20 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 * GNU General Public License for more details.
22 *
23 * You should have received a copy of the GNU General Public License
24 * along with this program; if not, write to the Free Software
25 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 * MA 02111-1307 USA
27 */
28
29#ifndef __CONFIG_H
30#define __CONFIG_H
31
32#undef DEBUG
33
34/*
35 * The ADS GCPlus Linux boot ROM loads U-Boot into RAM at 0xc0200000.
36 * We don't actually init RAM in this case since we're using U-Boot as
37 * an secondary boot loader during Linux kernel development and testing,
38 * e.g. bootp/tftp download of the kernel is a far more convenient
39 * when testing new kernels on this target. However the ADS GCPlus Linux
40 * boot ROM leaves the MMU enabled when it passes control to U-Boot. So
wdenk400558b2005-04-02 23:52:25 +000041 * we use lowlevel_init (CONFIG_INIT_CRITICAL) to remedy that problem.
wdenk855a4962004-03-14 18:23:55 +000042 */
wdenk8aa1a2d2005-04-04 12:44:11 +000043#undef CONFIG_SKIP_LOWLEVEL_INIT
44#define CONFIG_SKIP_RELOCATE_UBOOT 1
wdenk855a4962004-03-14 18:23:55 +000045
46/*
47 * High Level Configuration Options
48 * (easy to change)
49 */
50#define CONFIG_SA1110 1 /* This is an SA1100 CPU */
51#define CONFIG_GCPLUS 1 /* on an ADS GCPlus Board */
52
53#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
54
55#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
56#define CONFIG_SETUP_MEMORY_TAGS 1
57#define CONFIG_INITRD_TAG 1
58
59/*
60 * Size of malloc() pool
61 */
62#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024)
63#define CFG_GBL_DATA_SIZE 128 /* size rsrvd for initial data */
64
65
66/*
67 * Hardware drivers
68 */
69#define CONFIG_DRIVER_LAN91C96 /* we have an SMC9194 on-board */
70#define CONFIG_LAN91C96_BASE 0x100e0000
71
72/*
73 * select serial console configuration
74 */
75#define CONFIG_SERIAL3 1 /* we use SERIAL 3 on ADS GCPlus */
76
77/* allow to overwrite serial and ethaddr */
78#define CONFIG_ENV_OVERWRITE
79
80#define CONFIG_BAUDRATE 38400
81
wdenk855a4962004-03-14 18:23:55 +000082
Jon Loeliger72eb0ef2007-07-04 22:32:19 -050083/*
84 * Command line configuration.
85 */
86#include <config_cmd_default.h>
87
88#define CONFIG_CMD_DHCP
89
90
Jon Loeliger2fd90ce2007-07-09 21:48:26 -050091/*
92 * BOOTP options
93 */
94#define CONFIG_BOOTP_SUBNETMASK
95#define CONFIG_BOOTP_GATEWAY
96#define CONFIG_BOOTP_HOSTNAME
97#define CONFIG_BOOTP_BOOTPATH
98
wdenk855a4962004-03-14 18:23:55 +000099
100#define CONFIG_BOOTDELAY 3
101#define CONFIG_BOOTARGS "console=ttySA0,38400n8 mtdparts=sa1100-flash:1m@0(zImage),3m@1m(ramdisk.gz),12m@4m(userfs) root=/dev/nfs ip=bootp"
102#define CONFIG_BOOTCOMMAND "bootp;tftp;bootm"
103#define CFG_AUTOLOAD "n" /* No autoload */
104
Jon Loeliger72eb0ef2007-07-04 22:32:19 -0500105#if defined(CONFIG_CMD_KGDB)
wdenk855a4962004-03-14 18:23:55 +0000106#define CONFIG_KGDB_BAUDRATE 38400 /* speed to run kgdb serial port */
107#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
108#endif
109
110/*
111 * Miscellaneous configurable options
112 */
113#define CFG_LONGHELP /* undef to save memory */
114#define CFG_PROMPT "ADS GCPlus # " /* Monitor Command Prompt */
115#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
116#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
117#define CFG_MAXARGS 16 /* max number of command args */
118#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
119
120#define CFG_MEMTEST_START 0xc0400000 /* memtest works on */
121#define CFG_MEMTEST_END 0xc0800000 /* 4 ... 8 MB in DRAM */
122
123#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */
124
125#define CFG_LOAD_ADDR 0xc0000000 /* default load address */
126
127#define CFG_HZ 3686400 /* incrementer freq: 3.6864 MHz */
128#define CFG_CPUSPEED 0x0a /* set core clock to 206MHz */
129
130 /* valid baudrates */
131#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
132
133/*-----------------------------------------------------------------------
134 * Stack sizes
135 *
136 * The stack sizes are set up in start.S using the settings below
137 */
138#define CONFIG_STACKSIZE (128*1024) /* regular stack */
139#ifdef CONFIG_USE_IRQ
140#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
141#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
142#endif
143
144/*-----------------------------------------------------------------------
145 * Physical Memory Map
146 */
147#define CONFIG_NR_DRAM_BANKS 2 /* we have 2 banks of DRAM */
148#define PHYS_SDRAM_1 0xc0000000 /* SDRAM Bank #1 */
149#define PHYS_SDRAM_1_SIZE 0x01000000 /* 16 MB */
150#define PHYS_SDRAM_2 0xc8000000 /* SDRAM Bank #2 */
151#define PHYS_SDRAM_2_SIZE 0x01000000 /* 16 MB */
152
153
154#define PHYS_FLASH_1 0x08000000 /* Flash Bank #1 */
155#define PHYS_FLASH_SIZE 0x00800000 /* 8 MB */
156#define PHYS_FLASH_BANK_SIZE 0x01000000 /* 16 MB Banks */
157#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */
158
159#define CFG_FLASH_BASE PHYS_FLASH_1
160
161/*-----------------------------------------------------------------------
162 * FLASH and environment organization
163 */
164#if 1
165#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
166#define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
167
168/* timeout values are in ticks */
169#define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */
170#define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */
171#else
wdenk42dfe7a2004-03-14 22:25:36 +0000172/* REVISIT: This doesn't work on ADS GCPlus just yet: */
wdenk855a4962004-03-14 18:23:55 +0000173#define CFG_FLASH_CFI 1 /* flash is CFI conformant */
174#define CFG_FLASH_CFI_DRIVER 1 /* use common cfi driver */
175#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
176#define CFG_MAX_FLASH_BANKS 1 /* max # of memory banks */
177#define CFG_FLASH_INCREMENT 0 /* there is only one bank */
178#define CFG_MAX_FLASH_SECT 128 /* max # of sectors on one chip */
wdenk42dfe7a2004-03-14 22:25:36 +0000179/*#define CFG_FLASH_PROTECTION 1 /--* hardware flash protection */
wdenk855a4962004-03-14 18:23:55 +0000180#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
181#endif
182
183#define CFG_ENV_IS_IN_FLASH 1
184#define CFG_ENV_ADDR (PHYS_FLASH_1 + PHYS_FLASH_SECT_SIZE) /* Addr of Environment Sector */
185#define CFG_ENV_SIZE PHYS_FLASH_SECT_SIZE
186
187#endif /* __CONFIG_H */