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Bartlomiej Sieka4707fb52006-10-13 21:09:09 +02001/*
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +01002 * (C) Copyright 2003-2006 Wolfgang Denk, DENX Software Engineering,
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +02003 * wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this project.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the Free
9 * Software Foundation; either version 2 of the License, or (at your option)
10 * any later version.
11 *
12 * This program is distributed in the hope that it will be useful, but WITHOUT
13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +010014 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +020015 * for more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc., 59
19 * Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#ifndef __CONFIG_H
23#define __CONFIG_H
24
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +020025/*
26 * High Level Configuration Options
27 * (easy to change)
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +010028 */
29#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
30#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */
31#define CONFIG_V38B 1 /* ...on V38B board */
32#define CFG_MPC5XXX_CLKIN 33000000 /* ...running at 33.000000MHz */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +020033
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +010034#define CONFIG_RTC_PCF8563 1 /* has PCF8563 RTC */
35#define CONFIG_MPC5200_DDR 1 /* has DDR SDRAM */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +020036
Bartlomiej Siekace3f1a42006-11-11 22:48:22 +010037#undef CONFIG_HW_WATCHDOG /* don't use watchdog */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +020038
39#define CONFIG_NETCONSOLE 1
40
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +010041#define CONFIG_BOARD_EARLY_INIT_R 1 /* do board-specific init */
Bartlomiej Siekacce4acb2006-12-28 19:08:21 +010042#define CONFIG_BOARD_EARLY_INIT_F 1 /* do board-specific init */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +020043
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +010044#define CFG_XLB_PIPELINING 1 /* gives better performance */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +020045
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +010046#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
47#define BOOTFLAG_WARM 0x02 /* Software reboot */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +020048
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +020049/*
50 * Serial console configuration
51 */
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +010052#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
53#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +020054#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
55
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +020056/*
57 * DDR
58 */
59#define SDRAM_DDR 1 /* is DDR */
60/* Settings for XLB = 132 MHz */
61#define SDRAM_MODE 0x018D0000
62#define SDRAM_EMODE 0x40090000
63#define SDRAM_CONTROL 0x704f0f00
64#define SDRAM_CONFIG1 0x73722930
65#define SDRAM_CONFIG2 0x47770000
66#define SDRAM_TAPDELAY 0x10000000
67
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +020068/*
69 * PCI - no suport
70 */
71#undef CONFIG_PCI
72
73/*
74 * Partitions
75 */
76#define CONFIG_MAC_PARTITION 1
77#define CONFIG_DOS_PARTITION 1
78
79/*
80 * USB
81 */
82#define CONFIG_USB_OHCI
83#define CONFIG_USB_STORAGE
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +010084#define CONFIG_USB_CLOCK 0x0001BBBB
85#define CONFIG_USB_CONFIG 0x00001000
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +020086
Jon Loeligerdca3b3d2007-07-04 22:33:46 -050087
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +020088/*
Jon Loeliger079a1362007-07-10 10:12:10 -050089 * BOOTP options
90 */
91#define CONFIG_BOOTP_BOOTFILESIZE
92#define CONFIG_BOOTP_BOOTPATH
93#define CONFIG_BOOTP_GATEWAY
94#define CONFIG_BOOTP_HOSTNAME
95
96
97/*
Jon Loeligerdca3b3d2007-07-04 22:33:46 -050098 * Command line configuration.
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +020099 */
Jon Loeligerdca3b3d2007-07-04 22:33:46 -0500100#include <config_cmd_default.h>
101
102#define CONFIG_CMD_FAT
103#define CONFIG_CMD_I2C
104#define CONFIG_CMD_IDE
105#define CONFIG_CMD_PING
106#define CONFIG_CMD_DHCP
107#define CONFIG_CMD_DIAG
108#define CONFIG_CMD_IRQ
109#define CONFIG_CMD_JFFS2
110#define CONFIG_CMD_MII
111#define CONFIG_CMD_SDRAM
112#define CONFIG_CMD_DATE
113#define CONFIG_CMD_USB
114#define CONFIG_CMD_FAT
115
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200116
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +0100117#define CONFIG_TIMESTAMP /* Print image info with timestamp */
118
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200119/*
120 * Boot low with 16 MB Flash
121 */
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +0100122#define CFG_LOWBOOT 1
123#define CFG_LOWBOOT16 1
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200124
125/*
126 * Autobooting
127 */
128#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
129
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +0100130#define CONFIG_PREBOOT "echo;" \
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200131 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
132 "echo"
133
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +0100134#undef CONFIG_BOOTARGS
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200135
Wolfgang Denkfcfed4f2006-10-18 22:44:38 +0200136#define CONFIG_EXTRA_ENV_SETTINGS \
Wolfgang Denkfcfed4f2006-10-18 22:44:38 +0200137 "bootcmd=run net_nfs\0" \
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +0100138 "bootdelay=3\0" \
139 "baudrate=115200\0" \
140 "preboot=echo;echo Type \"run flash_nfs\" to mount root " \
141 "filesystem over NFS; echo\0" \
142 "netdev=eth0\0" \
Bartlomiej Siekacce4acb2006-12-28 19:08:21 +0100143 "ramargs=setenv bootargs root=/dev/ram rw wdt=off \0" \
Wolfgang Denkfcfed4f2006-10-18 22:44:38 +0200144 "addip=setenv bootargs $(bootargs) " \
145 "ip=$(ipaddr):$(serverip):$(gatewayip):" \
146 "$(netmask):$(hostname):$(netdev):off panic=1\0" \
147 "flash_nfs=run nfsargs addip;bootm $(kernel_addr)\0" \
148 "flash_self=run ramargs addip;bootm $(kernel_addr) " \
149 "$(ramdisk_addr)\0" \
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +0100150 "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \
Wolfgang Denkfcfed4f2006-10-18 22:44:38 +0200151 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Bartlomiej Siekacce4acb2006-12-28 19:08:21 +0100152 "nfsroot=$(serverip):$(rootpath) wdt=off\0" \
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +0100153 "hostname=v38b\0" \
154 "ethact=FEC ETHERNET\0" \
155 "rootpath=/opt/eldk-3.1.1/ppc_6xx\0" \
156 "update=prot off ff000000 ff03ffff; era ff000000 ff03ffff; " \
157 "cp.b 200000 ff000000 $(filesize);" \
158 "prot on ff000000 ff03ffff\0" \
159 "load=tftp 200000 $(u-boot)\0" \
160 "netmask=255.255.0.0\0" \
161 "ipaddr=192.168.160.18\0" \
162 "serverip=192.168.1.1\0" \
163 "ethaddr=00:e0:ee:00:05:2e\0" \
164 "bootfile=/tftpboot/v38b/uImage\0" \
165 "u-boot=/tftpboot/v38b/u-boot.bin\0" \
Wolfgang Denkfcfed4f2006-10-18 22:44:38 +0200166 ""
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200167
168#define CONFIG_BOOTCOMMAND "run net_nfs"
169
170#if defined(CONFIG_MPC5200)
171/*
172 * IPB Bus clocking configuration.
173 */
Bartlomiej Siekac99512d2007-05-27 16:53:43 +0200174#undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200175#endif
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +0100176
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200177/*
178 * I2C configuration
179 */
180#define CONFIG_HARD_I2C 1 /* I2C with hardware support */
181#define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +0100182#define CFG_I2C_SPEED 100000 /* 100 kHz */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200183#define CFG_I2C_SLAVE 0x7F
184
185/*
186 * EEPROM configuration
187 */
188#define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */
189#define CFG_I2C_EEPROM_ADDR_LEN 1
190#define CFG_EEPROM_PAGE_WRITE_BITS 3
191#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 70
192
193/*
194 * RTC configuration
195 */
196#define CFG_I2C_RTC_ADDR 0x51
197
198/*
199 * Flash configuration - use CFI driver
200 */
201#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */
202#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +0100203#define CFG_FLASH_CFI_AMD_RESET 1
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200204#define CFG_FLASH_BASE 0xFF000000
205#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */
206#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
207#define CFG_FLASH_SIZE 0x01000000 /* 16 MiB */
208#define CFG_MAX_FLASH_SECT 256 /* max num of sects on one chip */
Wolfgang Denkfcfed4f2006-10-18 22:44:38 +0200209#define CFG_FLASH_USE_BUFFER_WRITE 1 /* flash write speed-up */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200210
211/*
212 * Environment settings
213 */
214#define CFG_ENV_IS_IN_FLASH 1
215#define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00040000)
216#define CFG_ENV_SIZE 0x10000
217#define CFG_ENV_SECT_SIZE 0x10000
218#define CONFIG_ENV_OVERWRITE 1
219
220/*
221 * Memory map
222 */
223#define CFG_MBAR 0xF0000000
224#define CFG_SDRAM_BASE 0x00000000
225#define CFG_DEFAULT_MBAR 0x80000000
226
227/* Use SRAM until RAM will be available */
228#define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
229#define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */
230
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200231#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
232#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
233#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
234
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +0100235#define CFG_MONITOR_BASE TEXT_BASE
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200236#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
237# define CFG_RAMBOOT 1
238#endif
239
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +0100240#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256kB for Monitor */
241#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128kB for malloc() */
242#define CFG_BOOTMAPSZ (8 << 20) /* Linux initial memory map */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200243
244/*
245 * Ethernet configuration
246 */
247#define CONFIG_MPC5xxx_FEC 1
248#define CONFIG_PHY_ADDR 0x00
Wolfgang Denkfcfed4f2006-10-18 22:44:38 +0200249#define CONFIG_MII 1
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200250
251/*
252 * GPIO configuration
253 */
Bartlomiej Sieka44a47e62006-11-11 22:43:00 +0100254#define CFG_GPS_PORT_CONFIG 0x90001404
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200255
256/*
257 * Miscellaneous configurable options
258 */
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +0100259#define CFG_LONGHELP /* undef to save memory */
260#define CFG_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeligerdca3b3d2007-07-04 22:33:46 -0500261#if defined(CONFIG_CMD_KGDB)
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +0100262#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200263#else
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +0100264#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200265#endif
266#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +0100267#define CFG_MAXARGS 16 /* max number of command args */
268#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200269
270#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +0100271#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200272
273#define CFG_LOAD_ADDR 0x100000 /* default load address */
274
275#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
276
Jon Loeligerdca3b3d2007-07-04 22:33:46 -0500277#define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
278#if defined(CONFIG_CMD_KGDB)
279# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
280#endif
281
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200282/*
283 * Various low-level settings
284 */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200285#define CFG_HID0_INIT HID0_ICE | HID0_ICFI
286#define CFG_HID0_FINAL HID0_ICE
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200287
288#define CFG_BOOTCS_START CFG_FLASH_BASE
289#define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
290#define CFG_BOOTCS_CFG 0x00047801
291#define CFG_CS0_START CFG_FLASH_BASE
292#define CFG_CS0_SIZE CFG_FLASH_SIZE
293
294#define CFG_CS_BURST 0x00000000
295#define CFG_CS_DEADCYCLE 0x33333333
296
297#define CFG_RESET_ADDRESS 0xff000000
298
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +0100299/*
300 * IDE/ATA (supports IDE harddisk)
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200301 */
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +0100302#undef CONFIG_IDE_8xx_PCCARD /* Don't use IDE with PC Card Adapter */
303#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
304#undef CONFIG_IDE_LED /* LED for ide not supported */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200305
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +0100306#define CONFIG_IDE_RESET /* reset for ide supported */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200307#define CONFIG_IDE_PREINIT
308
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +0100309#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
310#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200311
312#define CFG_ATA_IDE0_OFFSET 0x0000
313
314#define CFG_ATA_BASE_ADDR MPC5XXX_ATA
315
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +0100316#define CFG_ATA_DATA_OFFSET (0x0060) /* data I/O offset */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200317
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +0100318#define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET) /* normal register accesses offset */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200319
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +0100320#define CFG_ATA_ALT_OFFSET (0x005C) /* alternate registers offset */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200321
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +0100322#define CFG_ATA_STRIDE 4 /* Interval between registers */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200323
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +0100324/*
325 * Status LED
326 */
327#define CONFIG_STATUS_LED /* Status LED enabled */
328#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200329
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +0100330#define CFG_LED_BASE MPC5XXX_GPT7_ENABLE /* Timer 7 GPIO */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200331#ifndef __ASSEMBLY__
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200332typedef unsigned int led_id_t;
333
334#define __led_toggle(_msk) \
335 do { \
336 *((volatile long *) (CFG_LED_BASE)) ^= (_msk); \
337 } while(0)
338
339#define __led_set(_msk, _st) \
340 do { \
341 if ((_st)) \
342 *((volatile long *) (CFG_LED_BASE)) &= ~(_msk); \
343 else \
344 *((volatile long *) (CFG_LED_BASE)) |= (_msk); \
345 } while(0)
346
347#define __led_init(_msk, st) \
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +0100348 do { \
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200349 *((volatile long *) (CFG_LED_BASE)) |= 0x34; \
Bartlomiej Sieka82d9c9e2006-11-01 01:34:29 +0100350 } while(0)
351#endif /* __ASSEMBLY__ */
Bartlomiej Sieka4707fb52006-10-13 21:09:09 +0200352
353#endif /* __CONFIG_H */