blob: 0304f94c107d40b289877a74231a061faa029c73 [file] [log] [blame]
wdenkc7de8292002-11-19 11:04:11 +00001#include <common.h>
2#include <asm/processor.h>
3#include <memio.h>
4#include <linux/ctype.h>
5
6static __inline__ unsigned long
7get_msr(void)
8{
9 unsigned long msr;
10
11 asm volatile("mfmsr %0" : "=r" (msr) :);
12 return msr;
13}
14
15static __inline__ void
16set_msr(unsigned long msr)
17{
wdenk8bde7f72003-06-27 21:31:46 +000018 asm volatile("mtmsr %0" : : "r" (msr));
wdenkc7de8292002-11-19 11:04:11 +000019}
20
21static __inline__ unsigned long
22get_dec(void)
23{
24 unsigned long val;
25
26 asm volatile("mfdec %0" : "=r" (val) :);
27 return val;
28}
29
30
31static __inline__ void
32set_dec(unsigned long val)
33{
wdenk8bde7f72003-06-27 21:31:46 +000034 asm volatile("mtdec %0" : : "r" (val));
wdenkc7de8292002-11-19 11:04:11 +000035}
36
37
38void
39enable_interrupts(void)
40{
41 set_msr (get_msr() | MSR_EE);
42}
43
44/* returns flag if MSR_EE was set before */
45int
46disable_interrupts(void)
47{
48 ulong msr;
49
50 msr = get_msr();
51 set_msr (msr & ~MSR_EE);
52 return ((msr & MSR_EE) != 0);
53}
54
55u8 in8(u32 port)
56{
57 return in_byte(port);
58}
59
60void out8(u32 port, u8 val)
61{
62 out_byte(port, val);
63}
64
65unsigned long in32(u32 port)
66{
67 return in_long(port);
68}
69
70unsigned long simple_strtoul(const char *cp,char **endp,unsigned int base)
71{
wdenk8bde7f72003-06-27 21:31:46 +000072 unsigned long result = 0,value;
wdenkc7de8292002-11-19 11:04:11 +000073
wdenk8bde7f72003-06-27 21:31:46 +000074 if (*cp == '0') {
75 cp++;
76 if ((*cp == 'x') && isxdigit(cp[1])) {
77 base = 16;
78 cp++;
79 }
80 if (!base) {
81 base = 8;
82 }
83 }
84 if (!base) {
85 base = 10;
86 }
87 while (isxdigit(*cp) && (value = isdigit(*cp) ? *cp-'0' : (islower(*cp)
88 ? toupper(*cp) : *cp)-'A'+10) < base) {
89 result = result*base + value;
90 cp++;
91 }
92 if (endp)
93 *endp = (char *)cp;
94 return result;
wdenkc7de8292002-11-19 11:04:11 +000095}
96
97long simple_strtol(const char *cp,char **endp,unsigned int base)
98{
wdenk8bde7f72003-06-27 21:31:46 +000099 if(*cp=='-')
100 return -simple_strtoul(cp+1,endp,base);
101 return simple_strtoul(cp,endp,base);
wdenkc7de8292002-11-19 11:04:11 +0000102}
103
104static inline void
105soft_restart(unsigned long addr)
106{
wdenk8bde7f72003-06-27 21:31:46 +0000107 /* SRR0 has system reset vector, SRR1 has default MSR value */
108 /* rfi restores MSR from SRR1 and sets the PC to the SRR0 value */
wdenkc7de8292002-11-19 11:04:11 +0000109
wdenk8bde7f72003-06-27 21:31:46 +0000110 __asm__ __volatile__ ("mtspr 26, %0" :: "r" (addr));
111 __asm__ __volatile__ ("li 4, (1 << 6)" ::: "r4");
112 __asm__ __volatile__ ("mtspr 27, 4");
113 __asm__ __volatile__ ("rfi");
wdenkc7de8292002-11-19 11:04:11 +0000114
wdenk8bde7f72003-06-27 21:31:46 +0000115 while(1); /* not reached */
wdenkc7de8292002-11-19 11:04:11 +0000116}
117
118void
119do_reset (void)
120{
wdenk8bde7f72003-06-27 21:31:46 +0000121 ulong addr;
122 /* flush and disable I/D cache */
123 __asm__ __volatile__ ("mfspr 3, 1008" ::: "r3");
124 __asm__ __volatile__ ("ori 5, 5, 0xcc00" ::: "r5");
125 __asm__ __volatile__ ("ori 4, 3, 0xc00" ::: "r4");
126 __asm__ __volatile__ ("andc 5, 3, 5" ::: "r5");
127 __asm__ __volatile__ ("sync");
128 __asm__ __volatile__ ("mtspr 1008, 4");
129 __asm__ __volatile__ ("isync");
130 __asm__ __volatile__ ("sync");
131 __asm__ __volatile__ ("mtspr 1008, 5");
132 __asm__ __volatile__ ("isync");
133 __asm__ __volatile__ ("sync");
wdenkc7de8292002-11-19 11:04:11 +0000134
135#ifdef CFG_RESET_ADDRESS
wdenk8bde7f72003-06-27 21:31:46 +0000136 addr = CFG_RESET_ADDRESS;
wdenkc7de8292002-11-19 11:04:11 +0000137#else
wdenk8bde7f72003-06-27 21:31:46 +0000138 /*
139 * note: when CFG_MONITOR_BASE points to a RAM address,
140 * CFG_MONITOR_BASE - sizeof (ulong) is usually a valid
141 * address. Better pick an address known to be invalid on your
142 * system and assign it to CFG_RESET_ADDRESS.
143 */
144 addr = CFG_MONITOR_BASE - sizeof (ulong);
wdenkc7de8292002-11-19 11:04:11 +0000145#endif
wdenk8bde7f72003-06-27 21:31:46 +0000146 soft_restart(addr);
147 while(1); /* not reached */
wdenkc7de8292002-11-19 11:04:11 +0000148}