| TsiChungLiew | eaf9e44 | 2007-08-05 04:11:20 -0500 | [diff] [blame] | 1 | /* |
| 2 | * Freescale I2C Controller |
| 3 | * |
| 4 | * Copyright 2006 Freescale Semiconductor, Inc. |
| 5 | * |
| 6 | * Based on earlier versions by Gleb Natapov <gnatapov@mrv.com>, |
| 7 | * Xianghua Xiao <x.xiao@motorola.com>, Eran Liberty (liberty@freescale.com), |
| 8 | * and Jeff Brown. |
| 9 | * Some bits are taken from linux driver writen by adrian@humboldt.co.uk. |
| 10 | * |
| 11 | * This software may be used and distributed according to the |
| 12 | * terms of the GNU Public License, Version 2, incorporated |
| 13 | * herein by reference. |
| 14 | * |
| 15 | * This program is free software; you can redistribute it and/or |
| 16 | * modify it under the terms of the GNU General Public License |
| 17 | * Version 2 as published by the Free Software Foundation. |
| 18 | * |
| 19 | * This program is distributed in the hope that it will be useful, |
| 20 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 21 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 22 | * GNU General Public License for more details. |
| 23 | * |
| 24 | * You should have received a copy of the GNU General Public License |
| 25 | * along with this program; if not, write to the Free Software |
| 26 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 27 | * MA 02111-1307 USA |
| 28 | */ |
| 29 | |
| 30 | #ifndef _ASM_FSL_I2C_H_ |
| 31 | #define _ASM_FSL_I2C_H_ |
| 32 | |
| 33 | #include <asm/types.h> |
| 34 | |
| 35 | typedef struct fsl_i2c { |
| 36 | |
| 37 | u8 adr; /* I2C slave address */ |
| 38 | u8 res0[3]; |
| 39 | #define I2C_ADR 0xFE |
| 40 | #define I2C_ADR_SHIFT 1 |
| 41 | #define I2C_ADR_RES ~(I2C_ADR) |
| 42 | |
| 43 | u8 fdr; /* I2C frequency divider register */ |
| 44 | u8 res1[3]; |
| 45 | #define IC2_FDR 0x3F |
| 46 | #define IC2_FDR_SHIFT 0 |
| 47 | #define IC2_FDR_RES ~(IC2_FDR) |
| 48 | |
| 49 | u8 cr; /* I2C control redister */ |
| 50 | u8 res2[3]; |
| 51 | #define I2C_CR_MEN 0x80 |
| 52 | #define I2C_CR_MIEN 0x40 |
| 53 | #define I2C_CR_MSTA 0x20 |
| 54 | #define I2C_CR_MTX 0x10 |
| 55 | #define I2C_CR_TXAK 0x08 |
| 56 | #define I2C_CR_RSTA 0x04 |
| 57 | #define I2C_CR_BCST 0x01 |
| 58 | |
| 59 | u8 sr; /* I2C status register */ |
| 60 | u8 res3[3]; |
| 61 | #define I2C_SR_MCF 0x80 |
| 62 | #define I2C_SR_MAAS 0x40 |
| 63 | #define I2C_SR_MBB 0x20 |
| 64 | #define I2C_SR_MAL 0x10 |
| 65 | #define I2C_SR_BCSTM 0x08 |
| 66 | #define I2C_SR_SRW 0x04 |
| 67 | #define I2C_SR_MIF 0x02 |
| 68 | #define I2C_SR_RXAK 0x01 |
| 69 | |
| 70 | u8 dr; /* I2C data register */ |
| 71 | u8 res4[3]; |
| 72 | #define I2C_DR 0xFF |
| 73 | #define I2C_DR_SHIFT 0 |
| 74 | #define I2C_DR_RES ~(I2C_DR) |
| 75 | |
| 76 | u8 dfsrr; /* I2C digital filter sampling rate register */ |
| 77 | u8 res5[3]; |
| 78 | #define I2C_DFSRR 0x3F |
| 79 | #define I2C_DFSRR_SHIFT 0 |
| 80 | #define I2C_DFSRR_RES ~(I2C_DR) |
| 81 | |
| 82 | /* Fill out the reserved block */ |
| 83 | u8 res6[0xE8]; |
| 84 | } fsl_i2c_t; |
| 85 | |
| 86 | #endif /* _ASM_I2C_H_ */ |