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Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +00001/*
2 * (C) Copyright 2012 SAMSUNG Electronics
3 * Padmavathi Venna <padma.v@samsung.com>
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +00006 */
7
8#include <common.h>
9#include <malloc.h>
10#include <spi.h>
Rajeshwari Shinde4d3acb92012-12-26 20:03:23 +000011#include <fdtdec.h>
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +000012#include <asm/arch/clk.h>
13#include <asm/arch/clock.h>
14#include <asm/arch/cpu.h>
15#include <asm/arch/gpio.h>
16#include <asm/arch/pinmux.h>
17#include <asm/arch-exynos/spi.h>
18#include <asm/io.h>
19
Rajeshwari Shinde4d3acb92012-12-26 20:03:23 +000020DECLARE_GLOBAL_DATA_PTR;
21
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +000022/* Information about each SPI controller */
23struct spi_bus {
24 enum periph_id periph_id;
25 s32 frequency; /* Default clock frequency, -1 for none */
26 struct exynos_spi *regs;
27 int inited; /* 1 if this bus is ready for use */
Rajeshwari Shinde4d3acb92012-12-26 20:03:23 +000028 int node;
Rajeshwari Shinde8d203af2013-10-08 16:20:04 +053029 uint deactivate_delay_us; /* Delay to wait after deactivate */
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +000030};
31
32/* A list of spi buses that we know about */
33static struct spi_bus spi_bus[EXYNOS5_SPI_NUM_CONTROLLERS];
Rajeshwari Shinde4d3acb92012-12-26 20:03:23 +000034static unsigned int bus_count;
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +000035
36struct exynos_spi_slave {
37 struct spi_slave slave;
38 struct exynos_spi *regs;
39 unsigned int freq; /* Default frequency */
40 unsigned int mode;
41 enum periph_id periph_id; /* Peripheral ID for this device */
42 unsigned int fifo_size;
Rajeshwari Shindee4eaef82013-05-28 20:10:38 +000043 int skip_preamble;
Rajeshwari Shinde8d203af2013-10-08 16:20:04 +053044 struct spi_bus *bus; /* Pointer to our SPI bus info */
45 ulong last_transaction_us; /* Time of last transaction end */
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +000046};
47
48static struct spi_bus *spi_get_bus(unsigned dev_index)
49{
Rajeshwari Shinde4d3acb92012-12-26 20:03:23 +000050 if (dev_index < bus_count)
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +000051 return &spi_bus[dev_index];
52 debug("%s: invalid bus %d", __func__, dev_index);
53
54 return NULL;
55}
56
57static inline struct exynos_spi_slave *to_exynos_spi(struct spi_slave *slave)
58{
59 return container_of(slave, struct exynos_spi_slave, slave);
60}
61
62/**
63 * Setup the driver private data
64 *
65 * @param bus ID of the bus that the slave is attached to
66 * @param cs ID of the chip select connected to the slave
67 * @param max_hz Required spi frequency
68 * @param mode Required spi mode (clk polarity, clk phase and
69 * master or slave)
70 * @return new device or NULL
71 */
72struct spi_slave *spi_setup_slave(unsigned int busnum, unsigned int cs,
73 unsigned int max_hz, unsigned int mode)
74{
75 struct exynos_spi_slave *spi_slave;
76 struct spi_bus *bus;
77
78 if (!spi_cs_is_valid(busnum, cs)) {
79 debug("%s: Invalid bus/chip select %d, %d\n", __func__,
80 busnum, cs);
81 return NULL;
82 }
83
Simon Glassd3504fe2013-03-18 19:23:40 +000084 spi_slave = spi_alloc_slave(struct exynos_spi_slave, busnum, cs);
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +000085 if (!spi_slave) {
86 debug("%s: Could not allocate spi_slave\n", __func__);
87 return NULL;
88 }
89
90 bus = &spi_bus[busnum];
Rajeshwari Shinde8d203af2013-10-08 16:20:04 +053091 spi_slave->bus = bus;
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +000092 spi_slave->regs = bus->regs;
93 spi_slave->mode = mode;
94 spi_slave->periph_id = bus->periph_id;
95 if (bus->periph_id == PERIPH_ID_SPI1 ||
96 bus->periph_id == PERIPH_ID_SPI2)
97 spi_slave->fifo_size = 64;
98 else
99 spi_slave->fifo_size = 256;
100
Rajeshwari Shindee4eaef82013-05-28 20:10:38 +0000101 spi_slave->skip_preamble = 0;
Rajeshwari Shinde8d203af2013-10-08 16:20:04 +0530102 spi_slave->last_transaction_us = timer_get_us();
Rajeshwari Shindee4eaef82013-05-28 20:10:38 +0000103
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +0000104 spi_slave->freq = bus->frequency;
105 if (max_hz)
106 spi_slave->freq = min(max_hz, spi_slave->freq);
107
108 return &spi_slave->slave;
109}
110
111/**
112 * Free spi controller
113 *
114 * @param slave Pointer to spi_slave to which controller has to
115 * communicate with
116 */
117void spi_free_slave(struct spi_slave *slave)
118{
119 struct exynos_spi_slave *spi_slave = to_exynos_spi(slave);
120
121 free(spi_slave);
122}
123
124/**
125 * Flush spi tx, rx fifos and reset the SPI controller
126 *
127 * @param slave Pointer to spi_slave to which controller has to
128 * communicate with
129 */
130static void spi_flush_fifo(struct spi_slave *slave)
131{
132 struct exynos_spi_slave *spi_slave = to_exynos_spi(slave);
133 struct exynos_spi *regs = spi_slave->regs;
134
135 clrsetbits_le32(&regs->ch_cfg, SPI_CH_HS_EN, SPI_CH_RST);
136 clrbits_le32(&regs->ch_cfg, SPI_CH_RST);
137 setbits_le32(&regs->ch_cfg, SPI_TX_CH_ON | SPI_RX_CH_ON);
138}
139
140/**
141 * Initialize the spi base registers, set the required clock frequency and
142 * initialize the gpios
143 *
144 * @param slave Pointer to spi_slave to which controller has to
145 * communicate with
146 * @return zero on success else a negative value
147 */
148int spi_claim_bus(struct spi_slave *slave)
149{
150 struct exynos_spi_slave *spi_slave = to_exynos_spi(slave);
151 struct exynos_spi *regs = spi_slave->regs;
152 u32 reg = 0;
153 int ret;
154
155 ret = set_spi_clk(spi_slave->periph_id,
156 spi_slave->freq);
157 if (ret < 0) {
158 debug("%s: Failed to setup spi clock\n", __func__);
159 return ret;
160 }
161
162 exynos_pinmux_config(spi_slave->periph_id, PINMUX_FLAG_NONE);
163
164 spi_flush_fifo(slave);
165
166 reg = readl(&regs->ch_cfg);
167 reg &= ~(SPI_CH_CPHA_B | SPI_CH_CPOL_L);
168
169 if (spi_slave->mode & SPI_CPHA)
170 reg |= SPI_CH_CPHA_B;
171
172 if (spi_slave->mode & SPI_CPOL)
173 reg |= SPI_CH_CPOL_L;
174
175 writel(reg, &regs->ch_cfg);
176 writel(SPI_FB_DELAY_180, &regs->fb_clk);
177
178 return 0;
179}
180
181/**
182 * Reset the spi H/W and flush the tx and rx fifos
183 *
184 * @param slave Pointer to spi_slave to which controller has to
185 * communicate with
186 */
187void spi_release_bus(struct spi_slave *slave)
188{
189 spi_flush_fifo(slave);
190}
191
192static void spi_get_fifo_levels(struct exynos_spi *regs,
193 int *rx_lvl, int *tx_lvl)
194{
195 uint32_t spi_sts = readl(&regs->spi_sts);
196
197 *rx_lvl = (spi_sts >> SPI_RX_LVL_OFFSET) & SPI_FIFO_LVL_MASK;
198 *tx_lvl = (spi_sts >> SPI_TX_LVL_OFFSET) & SPI_FIFO_LVL_MASK;
199}
200
201/**
202 * If there's something to transfer, do a software reset and set a
203 * transaction size.
204 *
205 * @param regs SPI peripheral registers
206 * @param count Number of bytes to transfer
Rajeshwari Shindec4a79632013-10-08 16:20:06 +0530207 * @param step Number of bytes to transfer in each packet (1 or 4)
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +0000208 */
Rajeshwari Shindec4a79632013-10-08 16:20:06 +0530209static void spi_request_bytes(struct exynos_spi *regs, int count, int step)
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +0000210{
Rajeshwari Shindec4a79632013-10-08 16:20:06 +0530211 /* For word address we need to swap bytes */
212 if (step == 4) {
213 setbits_le32(&regs->mode_cfg,
214 SPI_MODE_CH_WIDTH_WORD | SPI_MODE_BUS_WIDTH_WORD);
215 count /= 4;
216 setbits_le32(&regs->swap_cfg, SPI_TX_SWAP_EN | SPI_RX_SWAP_EN |
217 SPI_TX_BYTE_SWAP | SPI_RX_BYTE_SWAP |
218 SPI_TX_HWORD_SWAP | SPI_RX_HWORD_SWAP);
219 } else {
220 /* Select byte access and clear the swap configuration */
221 clrbits_le32(&regs->mode_cfg,
222 SPI_MODE_CH_WIDTH_WORD | SPI_MODE_BUS_WIDTH_WORD);
223 writel(0, &regs->swap_cfg);
224 }
225
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +0000226 assert(count && count < (1 << 16));
227 setbits_le32(&regs->ch_cfg, SPI_CH_RST);
228 clrbits_le32(&regs->ch_cfg, SPI_CH_RST);
Rajeshwari Shindec4a79632013-10-08 16:20:06 +0530229
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +0000230 writel(count | SPI_PACKET_CNT_EN, &regs->pkt_cnt);
231}
232
Rajeshwari Shindee4eaef82013-05-28 20:10:38 +0000233static int spi_rx_tx(struct exynos_spi_slave *spi_slave, int todo,
234 void **dinp, void const **doutp, unsigned long flags)
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +0000235{
236 struct exynos_spi *regs = spi_slave->regs;
237 uchar *rxp = *dinp;
238 const uchar *txp = *doutp;
239 int rx_lvl, tx_lvl;
240 uint out_bytes, in_bytes;
Rajeshwari Shindee4eaef82013-05-28 20:10:38 +0000241 int toread;
242 unsigned start = get_timer(0);
243 int stopping;
Rajeshwari Shindec4a79632013-10-08 16:20:06 +0530244 int step;
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +0000245
246 out_bytes = in_bytes = todo;
247
Rajeshwari Shindee4eaef82013-05-28 20:10:38 +0000248 stopping = spi_slave->skip_preamble && (flags & SPI_XFER_END) &&
249 !(spi_slave->mode & SPI_SLAVE);
250
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +0000251 /*
Rajeshwari Shindec4a79632013-10-08 16:20:06 +0530252 * Try to transfer words if we can. This helps read performance at
253 * SPI clock speeds above about 20MHz.
254 */
255 step = 1;
256 if (!((todo | (uintptr_t)rxp | (uintptr_t)txp) & 3) &&
257 !spi_slave->skip_preamble)
258 step = 4;
259
260 /*
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +0000261 * If there's something to send, do a software reset and set a
262 * transaction size.
263 */
Rajeshwari Shindec4a79632013-10-08 16:20:06 +0530264 spi_request_bytes(regs, todo, step);
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +0000265
266 /*
267 * Bytes are transmitted/received in pairs. Wait to receive all the
268 * data because then transmission will be done as well.
269 */
Rajeshwari Shindee4eaef82013-05-28 20:10:38 +0000270 toread = in_bytes;
271
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +0000272 while (in_bytes) {
273 int temp;
274
275 /* Keep the fifos full/empty. */
276 spi_get_fifo_levels(regs, &rx_lvl, &tx_lvl);
Rajeshwari Shindec4a79632013-10-08 16:20:06 +0530277
278 /*
279 * Don't completely fill the txfifo, since we don't want our
280 * rxfifo to overflow, and it may already contain data.
281 */
Rajeshwari Shinde120af152013-10-08 16:20:05 +0530282 while (tx_lvl < spi_slave->fifo_size/2 && out_bytes) {
Rajeshwari Shindec4a79632013-10-08 16:20:06 +0530283 if (!txp)
284 temp = -1;
285 else if (step == 4)
286 temp = *(uint32_t *)txp;
287 else
288 temp = *txp;
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +0000289 writel(temp, &regs->tx_data);
Rajeshwari Shindec4a79632013-10-08 16:20:06 +0530290 out_bytes -= step;
291 if (txp)
292 txp += step;
293 tx_lvl += step;
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +0000294 }
Rajeshwari Shindec4a79632013-10-08 16:20:06 +0530295 if (rx_lvl >= step) {
296 while (rx_lvl >= step) {
Rajeshwari Shinde120af152013-10-08 16:20:05 +0530297 temp = readl(&regs->rx_data);
298 if (spi_slave->skip_preamble) {
299 if (temp == SPI_PREAMBLE_END_BYTE) {
300 spi_slave->skip_preamble = 0;
301 stopping = 0;
302 }
303 } else {
Rajeshwari Shindec4a79632013-10-08 16:20:06 +0530304 if (rxp || stopping) {
305 *rxp = temp;
306 rxp += step;
307 }
308 in_bytes -= step;
Rajeshwari Shindee4eaef82013-05-28 20:10:38 +0000309 }
Rajeshwari Shindec4a79632013-10-08 16:20:06 +0530310 toread -= step;
311 rx_lvl -= step;
312 }
Rajeshwari Shindee4eaef82013-05-28 20:10:38 +0000313 } else if (!toread) {
314 /*
315 * We have run out of input data, but haven't read
316 * enough bytes after the preamble yet. Read some more,
317 * and make sure that we transmit dummy bytes too, to
318 * keep things going.
319 */
320 assert(!out_bytes);
321 out_bytes = in_bytes;
322 toread = in_bytes;
323 txp = NULL;
Rajeshwari Shindec4a79632013-10-08 16:20:06 +0530324 spi_request_bytes(regs, toread, step);
Rajeshwari Shindee4eaef82013-05-28 20:10:38 +0000325 }
326 if (spi_slave->skip_preamble && get_timer(start) > 100) {
327 printf("SPI timeout: in_bytes=%d, out_bytes=%d, ",
328 in_bytes, out_bytes);
329 return -1;
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +0000330 }
331 }
Rajeshwari Shindee4eaef82013-05-28 20:10:38 +0000332
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +0000333 *dinp = rxp;
334 *doutp = txp;
Rajeshwari Shindee4eaef82013-05-28 20:10:38 +0000335
336 return 0;
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +0000337}
338
339/**
340 * Transfer and receive data
341 *
342 * @param slave Pointer to spi_slave to which controller has to
343 * communicate with
344 * @param bitlen No of bits to tranfer or receive
345 * @param dout Pointer to transfer buffer
346 * @param din Pointer to receive buffer
347 * @param flags Flags for transfer begin and end
348 * @return zero on success else a negative value
349 */
350int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
351 void *din, unsigned long flags)
352{
353 struct exynos_spi_slave *spi_slave = to_exynos_spi(slave);
354 int upto, todo;
355 int bytelen;
Rajeshwari Shindee4eaef82013-05-28 20:10:38 +0000356 int ret = 0;
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +0000357
358 /* spi core configured to do 8 bit transfers */
359 if (bitlen % 8) {
360 debug("Non byte aligned SPI transfer.\n");
361 return -1;
362 }
363
364 /* Start the transaction, if necessary. */
365 if ((flags & SPI_XFER_BEGIN))
366 spi_cs_activate(slave);
367
Rajeshwari Shindec4a79632013-10-08 16:20:06 +0530368 /*
369 * Exynos SPI limits each transfer to 65535 transfers. To keep
370 * things simple, allow a maximum of 65532 bytes. We could allow
371 * more in word mode, but the performance difference is small.
372 */
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +0000373 bytelen = bitlen / 8;
Rajeshwari Shindee4eaef82013-05-28 20:10:38 +0000374 for (upto = 0; !ret && upto < bytelen; upto += todo) {
Rajeshwari Shindec4a79632013-10-08 16:20:06 +0530375 todo = min(bytelen - upto, (1 << 16) - 4);
Rajeshwari Shindee4eaef82013-05-28 20:10:38 +0000376 ret = spi_rx_tx(spi_slave, todo, &din, &dout, flags);
377 if (ret)
378 break;
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +0000379 }
380
381 /* Stop the transaction, if necessary. */
Rajeshwari Shindee4eaef82013-05-28 20:10:38 +0000382 if ((flags & SPI_XFER_END) && !(spi_slave->mode & SPI_SLAVE)) {
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +0000383 spi_cs_deactivate(slave);
Rajeshwari Shindee4eaef82013-05-28 20:10:38 +0000384 if (spi_slave->skip_preamble) {
385 assert(!spi_slave->skip_preamble);
386 debug("Failed to complete premable transaction\n");
387 ret = -1;
388 }
389 }
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +0000390
Rajeshwari Shindee4eaef82013-05-28 20:10:38 +0000391 return ret;
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +0000392}
393
394/**
395 * Validates the bus and chip select numbers
396 *
397 * @param bus ID of the bus that the slave is attached to
398 * @param cs ID of the chip select connected to the slave
399 * @return one on success else zero
400 */
401int spi_cs_is_valid(unsigned int bus, unsigned int cs)
402{
403 return spi_get_bus(bus) && cs == 0;
404}
405
406/**
407 * Activate the CS by driving it LOW
408 *
409 * @param slave Pointer to spi_slave to which controller has to
410 * communicate with
411 */
412void spi_cs_activate(struct spi_slave *slave)
413{
414 struct exynos_spi_slave *spi_slave = to_exynos_spi(slave);
415
Rajeshwari Shinde8d203af2013-10-08 16:20:04 +0530416 /* If it's too soon to do another transaction, wait */
417 if (spi_slave->bus->deactivate_delay_us &&
418 spi_slave->last_transaction_us) {
419 ulong delay_us; /* The delay completed so far */
420 delay_us = timer_get_us() - spi_slave->last_transaction_us;
421 if (delay_us < spi_slave->bus->deactivate_delay_us)
422 udelay(spi_slave->bus->deactivate_delay_us - delay_us);
423 }
424
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +0000425 clrbits_le32(&spi_slave->regs->cs_reg, SPI_SLAVE_SIG_INACT);
426 debug("Activate CS, bus %d\n", spi_slave->slave.bus);
Rajeshwari Shindee4eaef82013-05-28 20:10:38 +0000427 spi_slave->skip_preamble = spi_slave->mode & SPI_PREAMBLE;
Rajeshwari Shinde8d203af2013-10-08 16:20:04 +0530428
429 /* Remember time of this transaction so we can honour the bus delay */
430 if (spi_slave->bus->deactivate_delay_us)
431 spi_slave->last_transaction_us = timer_get_us();
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +0000432}
433
434/**
435 * Deactivate the CS by driving it HIGH
436 *
437 * @param slave Pointer to spi_slave to which controller has to
438 * communicate with
439 */
440void spi_cs_deactivate(struct spi_slave *slave)
441{
442 struct exynos_spi_slave *spi_slave = to_exynos_spi(slave);
443
444 setbits_le32(&spi_slave->regs->cs_reg, SPI_SLAVE_SIG_INACT);
445 debug("Deactivate CS, bus %d\n", spi_slave->slave.bus);
446}
447
448static inline struct exynos_spi *get_spi_base(int dev_index)
449{
450 if (dev_index < 3)
451 return (struct exynos_spi *)samsung_get_base_spi() + dev_index;
452 else
453 return (struct exynos_spi *)samsung_get_base_spi_isp() +
454 (dev_index - 3);
455}
456
Rajeshwari Shinde4d3acb92012-12-26 20:03:23 +0000457/*
458 * Read the SPI config from the device tree node.
459 *
460 * @param blob FDT blob to read from
461 * @param node Node offset to read from
462 * @param bus SPI bus structure to fill with information
463 * @return 0 if ok, or -FDT_ERR_NOTFOUND if something was missing
464 */
Vivek Gautam7d179582013-03-05 03:49:57 +0000465#ifdef CONFIG_OF_CONTROL
Rajeshwari Shinde4d3acb92012-12-26 20:03:23 +0000466static int spi_get_config(const void *blob, int node, struct spi_bus *bus)
467{
468 bus->node = node;
469 bus->regs = (struct exynos_spi *)fdtdec_get_addr(blob, node, "reg");
470 bus->periph_id = pinmux_decode_periph_id(blob, node);
471
472 if (bus->periph_id == PERIPH_ID_NONE) {
473 debug("%s: Invalid peripheral ID %d\n", __func__,
474 bus->periph_id);
475 return -FDT_ERR_NOTFOUND;
476 }
477
478 /* Use 500KHz as a suitable default */
479 bus->frequency = fdtdec_get_int(blob, node, "spi-max-frequency",
480 500000);
Rajeshwari Shinde8d203af2013-10-08 16:20:04 +0530481 bus->deactivate_delay_us = fdtdec_get_int(blob, node,
482 "spi-deactivate-delay", 0);
Rajeshwari Shinde4d3acb92012-12-26 20:03:23 +0000483
484 return 0;
485}
486
487/*
488 * Process a list of nodes, adding them to our list of SPI ports.
489 *
490 * @param blob fdt blob
491 * @param node_list list of nodes to process (any <=0 are ignored)
492 * @param count number of nodes to process
493 * @param is_dvc 1 if these are DVC ports, 0 if standard I2C
494 * @return 0 if ok, -1 on error
495 */
496static int process_nodes(const void *blob, int node_list[], int count)
497{
498 int i;
499
500 /* build the i2c_controllers[] for each controller */
501 for (i = 0; i < count; i++) {
502 int node = node_list[i];
503 struct spi_bus *bus;
504
505 if (node <= 0)
506 continue;
507
508 bus = &spi_bus[i];
509 if (spi_get_config(blob, node, bus)) {
510 printf("exynos spi_init: failed to decode bus %d\n",
511 i);
512 return -1;
513 }
514
515 debug("spi: controller bus %d at %p, periph_id %d\n",
516 i, bus->regs, bus->periph_id);
517 bus->inited = 1;
518 bus_count++;
519 }
520
521 return 0;
522}
Vivek Gautam7d179582013-03-05 03:49:57 +0000523#endif
Rajeshwari Shinde4d3acb92012-12-26 20:03:23 +0000524
Hung-ying Tyanf3424c52013-05-15 18:27:30 +0800525/**
526 * Set up a new SPI slave for an fdt node
527 *
528 * @param blob Device tree blob
529 * @param node SPI peripheral node to use
530 * @return 0 if ok, -1 on error
531 */
Simon Glass0efc0242013-12-03 16:43:24 -0700532struct spi_slave *spi_setup_slave_fdt(const void *blob, int slave_node,
533 int spi_node)
Hung-ying Tyanf3424c52013-05-15 18:27:30 +0800534{
535 struct spi_bus *bus;
536 unsigned int i;
537
538 for (i = 0, bus = spi_bus; i < bus_count; i++, bus++) {
Simon Glass0efc0242013-12-03 16:43:24 -0700539 if (bus->node == spi_node)
540 return spi_base_setup_slave_fdt(blob, i, slave_node);
Hung-ying Tyanf3424c52013-05-15 18:27:30 +0800541 }
542
Simon Glass0efc0242013-12-03 16:43:24 -0700543 debug("%s: Failed to find bus node %d\n", __func__, spi_node);
Hung-ying Tyanf3424c52013-05-15 18:27:30 +0800544 return NULL;
545}
546
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +0000547/* Sadly there is no error return from this function */
548void spi_init(void)
549{
Rajeshwari Shinde4d3acb92012-12-26 20:03:23 +0000550 int count;
551
552#ifdef CONFIG_OF_CONTROL
553 int node_list[EXYNOS5_SPI_NUM_CONTROLLERS];
554 const void *blob = gd->fdt_blob;
555
556 count = fdtdec_find_aliases_for_id(blob, "spi",
557 COMPAT_SAMSUNG_EXYNOS_SPI, node_list,
558 EXYNOS5_SPI_NUM_CONTROLLERS);
559 if (process_nodes(blob, node_list, count))
560 return;
561
562#else
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +0000563 struct spi_bus *bus;
564
Rajeshwari Shinde4d3acb92012-12-26 20:03:23 +0000565 for (count = 0; count < EXYNOS5_SPI_NUM_CONTROLLERS; count++) {
566 bus = &spi_bus[count];
567 bus->regs = get_spi_base(count);
568 bus->periph_id = PERIPH_ID_SPI0 + count;
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +0000569
570 /* Although Exynos5 supports upto 50Mhz speed,
571 * we are setting it to 10Mhz for safe side
572 */
573 bus->frequency = 10000000;
574 bus->inited = 1;
Rajeshwari Shinde4d3acb92012-12-26 20:03:23 +0000575 bus->node = 0;
576 bus_count = EXYNOS5_SPI_NUM_CONTROLLERS;
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +0000577 }
Rajeshwari Shinde4d3acb92012-12-26 20:03:23 +0000578#endif
Rajeshwari Shinde1bf43b82012-11-02 01:15:36 +0000579}