Bartlomiej Sieka | 53d4a49 | 2007-02-09 10:45:42 +0100 | [diff] [blame] | 1 | /* |
| 2 | * (C) Copyright 2003-2007 |
| 3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. |
| 4 | * |
| 5 | * modified for Promess PRO - by Andy Joseph, andy@promessdev.com |
| 6 | * modified for Promess PRO-Motion - by Robert McCullough, rob@promessdev.com |
| 7 | * modified by Chris M. Tumas 6/20/06 Change CAS latency to 2 from 3 |
| 8 | * Also changed the refresh for 100Mhz operation |
| 9 | * |
| 10 | * See file CREDITS for list of people who contributed to this |
| 11 | * project. |
| 12 | * |
| 13 | * This program is free software; you can redistribute it and/or |
| 14 | * modify it under the terms of the GNU General Public License as |
| 15 | * published by the Free Software Foundation; either version 2 of |
| 16 | * the License, or (at your option) any later version. |
| 17 | * |
| 18 | * This program is distributed in the hope that it will be useful, |
| 19 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 20 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 21 | * GNU General Public License for more details. |
| 22 | * |
| 23 | * You should have received a copy of the GNU General Public License |
| 24 | * along with this program; if not, write to the Free Software |
| 25 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 26 | * MA 02111-1307 USA |
| 27 | */ |
| 28 | |
| 29 | #include <common.h> |
| 30 | #include <mpc5xxx.h> |
| 31 | |
| 32 | |
| 33 | /* Kollmorgen DPR initialization data */ |
| 34 | struct init_elem { |
| 35 | unsigned long addr; |
| 36 | unsigned len; |
| 37 | char *data; |
| 38 | } init_seq[] = { |
| 39 | {0x500003F2, 2, "\x86\x00"}, /* HW parameter */ |
| 40 | {0x500003F0, 2, "\x00\x00"}, |
| 41 | {0x500003EC, 4, "\x00\x80\xc1\x52"}, /* Magic word */ |
| 42 | }; |
| 43 | |
| 44 | /* |
| 45 | * Initialize Kollmorgen DPR |
| 46 | */ |
| 47 | static void kollmorgen_init(void) |
| 48 | { |
| 49 | unsigned i, j; |
| 50 | vu_char *p; |
| 51 | |
| 52 | for (i = 0; i < sizeof(init_seq) / sizeof(struct init_elem); ++i) { |
| 53 | p = (vu_char *)init_seq[i].addr; |
| 54 | for (j = 0; j < init_seq[i].len; ++j) |
| 55 | *(p + j) = *(init_seq[i].data + j); |
| 56 | } |
| 57 | |
| 58 | printf("DPR: Kollmorgen DPR initialized\n"); |
| 59 | } |
| 60 | |
| 61 | |
| 62 | /* |
| 63 | * Early board initalization. |
| 64 | */ |
| 65 | int board_early_init_r(void) |
| 66 | { |
| 67 | /* Now, when we are in RAM, disable Boot Chipselect and enable CS0 */ |
| 68 | *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); |
| 69 | *(vu_long *)MPC5XXX_ADDECR |= (1 << 16); |
| 70 | |
| 71 | /* Initialize Kollmorgen DPR */ |
| 72 | kollmorgen_init(); |
| 73 | |
| 74 | return 0; |
| 75 | } |
| 76 | |
| 77 | |
| 78 | #ifndef CFG_RAMBOOT |
| 79 | /* |
| 80 | * Helper function to initialize SDRAM controller. |
| 81 | */ |
| 82 | static void sdram_start (int hi_addr) |
| 83 | { |
| 84 | long hi_addr_bit = hi_addr ? 0x01000000 : 0; |
| 85 | |
| 86 | /* unlock mode register */ |
| 87 | *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 | |
| 88 | hi_addr_bit; |
| 89 | |
| 90 | /* precharge all banks */ |
| 91 | *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 | |
| 92 | hi_addr_bit; |
| 93 | |
| 94 | /* auto refresh */ |
| 95 | *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | |
| 96 | hi_addr_bit; |
| 97 | |
| 98 | /* auto refresh, second time */ |
| 99 | *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 | |
| 100 | hi_addr_bit; |
| 101 | |
| 102 | /* set mode register */ |
| 103 | *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE; |
| 104 | |
| 105 | /* normal operation */ |
| 106 | *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit; |
| 107 | } |
| 108 | #endif /* !CFG_RAMBOOT */ |
| 109 | |
| 110 | |
| 111 | /* |
| 112 | * Initalize SDRAM - configure SDRAM controller, detect memory size. |
| 113 | */ |
| 114 | long int initdram (int board_type) |
| 115 | { |
| 116 | ulong dramsize = 0; |
| 117 | #ifndef CFG_RAMBOOT |
| 118 | ulong test1, test2; |
| 119 | |
| 120 | /* configure SDRAM start/end for detection */ |
| 121 | *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001e; /* 2G at 0x0 */ |
| 122 | *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000; /* disabled */ |
| 123 | |
| 124 | /* setup config registers */ |
| 125 | *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1; |
| 126 | *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2; |
| 127 | |
| 128 | sdram_start(0); |
| 129 | test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000); |
| 130 | sdram_start(1); |
| 131 | test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000); |
| 132 | if (test1 > test2) { |
| 133 | sdram_start(0); |
| 134 | dramsize = test1; |
| 135 | } else { |
| 136 | dramsize = test2; |
| 137 | } |
| 138 | |
| 139 | /* memory smaller than 1MB is impossible */ |
| 140 | if (dramsize < (1 << 20)) |
| 141 | dramsize = 0; |
| 142 | |
| 143 | /* set SDRAM CS0 size according to the amount of RAM found */ |
| 144 | if (dramsize > 0) |
| 145 | *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 + |
| 146 | __builtin_ffs(dramsize >> 20) - 1; |
| 147 | else |
| 148 | *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */ |
| 149 | |
| 150 | /* let SDRAM CS1 start right after CS0 and disable it */ |
| 151 | *(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize; |
| 152 | |
| 153 | #else /* !CFG_RAMBOOT */ |
| 154 | /* retrieve size of memory connected to SDRAM CS0 */ |
| 155 | dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF; |
| 156 | if (dramsize >= 0x13) |
| 157 | dramsize = (1 << (dramsize - 0x13)) << 20; |
| 158 | else |
| 159 | dramsize = 0; |
| 160 | #endif /* CFG_RAMBOOT */ |
| 161 | |
| 162 | /* return total ram size */ |
| 163 | return dramsize; |
| 164 | } |
| 165 | |
| 166 | |
| 167 | int checkboard (void) |
| 168 | { |
| 169 | puts("Board: Promess Motion-PRO board\n"); |
| 170 | return 0; |
| 171 | } |