blob: 3bd011518b3ad013e0cba9da740f18b9593a136f [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001// SPDX-License-Identifier: GPL-2.0+
Simon Glass81afac12016-01-18 20:19:19 -07002/*
3 * Copyright (C) 2014 Google, Inc
Simon Glass81afac12016-01-18 20:19:19 -07004 */
5
6#include <common.h>
7#include <dm.h>
Simon Glassf7ae49f2020-05-10 11:40:05 -06008#include <log.h>
Simon Glass81afac12016-01-18 20:19:19 -07009#include <pch.h>
10
Bin Mengec2af6f2016-02-01 01:40:44 -080011#define GPIO_BASE 0x48
Bin Meng4f106bc2016-02-01 01:40:46 -080012#define IO_BASE 0x4c
Simon Glass81afac12016-01-18 20:19:19 -070013#define SBASE_ADDR 0x54
14
Bin Meng3e389d82016-02-01 01:40:42 -080015static int pch9_get_spi_base(struct udevice *dev, ulong *sbasep)
Simon Glass81afac12016-01-18 20:19:19 -070016{
17 uint32_t sbase_addr;
18
19 dm_pci_read_config32(dev, SBASE_ADDR, &sbase_addr);
20 *sbasep = sbase_addr & 0xfffffe00;
21
22 return 0;
23}
24
Bin Mengec2af6f2016-02-01 01:40:44 -080025static int pch9_get_gpio_base(struct udevice *dev, u32 *gbasep)
26{
27 u32 base;
28
29 /*
30 * GPIO_BASE moved to its current offset with ICH6, but prior to
31 * that it was unused (or undocumented). Check that it looks
32 * okay: not all ones or zeros.
33 *
34 * Note we don't need check bit0 here, because the Tunnel Creek
35 * GPIO base address register bit0 is reserved (read returns 0),
36 * while on the Ivybridge the bit0 is used to indicate it is an
37 * I/O space.
38 */
39 dm_pci_read_config32(dev, GPIO_BASE, &base);
40 if (base == 0x00000000 || base == 0xffffffff) {
41 debug("%s: unexpected BASE value\n", __func__);
42 return -ENODEV;
43 }
44
45 /*
46 * Okay, I guess we're looking at the right device. The actual
47 * GPIO registers are in the PCI device's I/O space, starting
48 * at the offset that we just read. Bit 0 indicates that it's
49 * an I/O address, not a memory address, so mask that off.
50 */
51 *gbasep = base & 1 ? base & ~3 : base & ~15;
52
53 return 0;
54}
55
Bin Meng4f106bc2016-02-01 01:40:46 -080056static int pch9_get_io_base(struct udevice *dev, u32 *iobasep)
57{
58 u32 base;
59
60 dm_pci_read_config32(dev, IO_BASE, &base);
61 if (base == 0x00000000 || base == 0xffffffff) {
62 debug("%s: unexpected BASE value\n", __func__);
63 return -ENODEV;
64 }
65
66 *iobasep = base & 1 ? base & ~3 : base & ~15;
67
68 return 0;
69}
70
Simon Glass81afac12016-01-18 20:19:19 -070071static const struct pch_ops pch9_ops = {
Bin Meng3e389d82016-02-01 01:40:42 -080072 .get_spi_base = pch9_get_spi_base,
Bin Mengec2af6f2016-02-01 01:40:44 -080073 .get_gpio_base = pch9_get_gpio_base,
Bin Meng4f106bc2016-02-01 01:40:46 -080074 .get_io_base = pch9_get_io_base,
Simon Glass81afac12016-01-18 20:19:19 -070075};
76
77static const struct udevice_id pch9_ids[] = {
78 { .compatible = "intel,pch9" },
79 { }
80};
81
82U_BOOT_DRIVER(pch9_drv) = {
83 .name = "intel-pch9",
84 .id = UCLASS_PCH,
85 .of_match = pch9_ids,
86 .ops = &pch9_ops,
87};