blob: ffe89cb78fc990f3be96dfe3592974d5be7325f6 [file] [log] [blame]
wdenk10767cc2004-05-13 13:23:58 +00001/*
wdenk1d6f9722004-09-09 17:44:35 +00002 * ueberarbeitet durch Christoph Seyfert
3 *
wdenk414eec32005-04-02 22:37:54 +00004 * (C) Copyright 2004-2005 DENX Software Engineering,
wdenk10767cc2004-05-13 13:23:58 +00005 * Wolfgang Grandegger <wg@denx.de>
6 * (C) Copyright 2003
7 * DAVE Srl
8 *
9 * http://www.dave-tech.it
10 * http://www.wawnet.biz
11 * mailto:info@wawnet.biz
12 *
13 * Credits: Stefan Roese, Wolfgang Denk
14 *
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License as
17 * published by the Free Software Foundation; either version 2 of
18 * the License, or (at your option) any later version.
19 *
20 * This program is distributed in the hope that it will be useful,
21 * but WITHOUT ANY WARRANTY; without even the implied warranty of
22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
23 * GNU General Public License for more details.
24 *
25 * You should have received a copy of the GNU General Public License
26 * along with this program; if not, write to the Free Software
27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 * MA 02111-1307 USA
29 */
30
31/*
32 * board/config.h - configuration options, board specific
33 */
34
35#ifndef __CONFIG_H
36#define __CONFIG_H
37
38#define CONFIG_PPCHAMELEON_MODULE_BA 0 /* Basic Model */
39#define CONFIG_PPCHAMELEON_MODULE_ME 1 /* Medium Model */
40#define CONFIG_PPCHAMELEON_MODULE_HI 2 /* High-End Model */
41#ifndef CONFIG_PPCHAMELEON_MODULE_MODEL
42#define CONFIG_PPCHAMELEON_MODULE_MODEL CONFIG_PPCHAMELEON_MODULE_BA
43#endif
44
wdenk1d6f9722004-09-09 17:44:35 +000045/* Only one of the following two symbols must be defined (default is 25 MHz)
46 * CONFIG_PPCHAMELEON_CLK_25
47 * CONFIG_PPCHAMELEON_CLK_33
48 */
49#if (!defined(CONFIG_PPCHAMELEON_CLK_25) && !defined(CONFIG_PPCHAMELEON_CLK_33))
50#define CONFIG_PPCHAMELEON_CLK_25
51#endif
52
53#if (defined(CONFIG_PPCHAMELEON_CLK_25) && defined(CONFIG_PPCHAMELEON_CLK_33))
54#error "* Two external frequencies (SysClk) are defined! *"
55#endif
56
57#undef CONFIG_PPCHAMELEON_SMI712
58
wdenk10767cc2004-05-13 13:23:58 +000059/*
60 * Debug stuff
61 */
62#undef __DEBUG_START_FROM_SRAM__
63#define __DISABLE_MACHINE_EXCEPTION__
64
65#ifdef __DEBUG_START_FROM_SRAM__
66#define CFG_DUMMY_FLASH_SIZE 1024*1024*4
67#endif
68
69/*
70 * High Level Configuration Options
71 * (easy to change)
72 */
73
74#define CONFIG_405EP 1 /* This is a PPC405 CPU */
75#define CONFIG_4xx 1 /* ...member of PPC4xx family */
76#define CONFIG_PPCHAMELEONEVB 1 /* ...on a PPChameleonEVB board */
77
78#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
79#define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */
80
wdenk1d6f9722004-09-09 17:44:35 +000081#ifdef CONFIG_PPCHAMELEON_CLK_25
82# define CONFIG_SYS_CLK_FREQ 25000000 /* external frequency to pll */
83#elif (defined (CONFIG_PPCHAMELEON_CLK_33))
wdenk10767cc2004-05-13 13:23:58 +000084#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
wdenk1d6f9722004-09-09 17:44:35 +000085#else
86# error "* External frequency (SysClk) not defined! *"
87#endif
wdenk10767cc2004-05-13 13:23:58 +000088
wdenk1d6f9722004-09-09 17:44:35 +000089#define CONFIG_UART1_CONSOLE 1 /* Use second UART */
wdenk10767cc2004-05-13 13:23:58 +000090#define CONFIG_BAUDRATE 115200
91#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
92
wdenk1d6f9722004-09-09 17:44:35 +000093#define CONFIG_VERSION_VARIABLE 1 /* add version variable */
94#define CONFIG_IDENT_STRING "1"
95
wdenk10767cc2004-05-13 13:23:58 +000096#undef CONFIG_BOOTARGS
97
98/* Ethernet stuff */
99#define CONFIG_ENV_OVERWRITE /* Let the user to change the Ethernet MAC addresses */
wdenk1d6f9722004-09-09 17:44:35 +0000100#define CONFIG_ETHADDR 00:50:C2:1E:AF:FE
wdenke2ffd592004-12-31 09:32:47 +0000101#define CONFIG_HAS_ETH1
wdenk1d6f9722004-09-09 17:44:35 +0000102#define CONFIG_ETH1ADDR 00:50:C2:1E:AF:FD
wdenk10767cc2004-05-13 13:23:58 +0000103
104#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
105#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
106
107
108#undef CONFIG_EXT_PHY
wdenk1d6f9722004-09-09 17:44:35 +0000109#define CONFIG_NET_MULTI 1
wdenk10767cc2004-05-13 13:23:58 +0000110
111#define CONFIG_MII 1 /* MII PHY management */
112#ifndef CONFIG_EXT_PHY
stroesebf418862005-06-30 13:06:07 +0000113#define CONFIG_PHY_ADDR 1 /* EMAC0 PHY address */
stroese3c71f3e2005-07-01 15:53:57 +0000114#define CONFIG_PHY1_ADDR 16 /* EMAC1 PHY address */
wdenk10767cc2004-05-13 13:23:58 +0000115#else
116#define CONFIG_PHY_ADDR 2 /* PHY address */
117#endif
118#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ
119
wdenk414eec32005-04-02 22:37:54 +0000120#define CONFIG_TIMESTAMP /* Print image info with timestamp */
121
wdenk10767cc2004-05-13 13:23:58 +0000122#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
wdenk414eec32005-04-02 22:37:54 +0000123 CFG_CMD_DHCP | \
wdenk10767cc2004-05-13 13:23:58 +0000124 CFG_CMD_ELF | \
125 CFG_CMD_EEPROM | \
126 CFG_CMD_I2C | \
127 CFG_CMD_IRQ | \
wdenk1d6f9722004-09-09 17:44:35 +0000128 CFG_CMD_JFFS2 | \
wdenk10767cc2004-05-13 13:23:58 +0000129 CFG_CMD_MII | \
wdenk414eec32005-04-02 22:37:54 +0000130 CFG_CMD_NAND | \
131 CFG_CMD_NFS | \
132 CFG_CMD_SNTP )
wdenk10767cc2004-05-13 13:23:58 +0000133
134#define CONFIG_MAC_PARTITION
135#define CONFIG_DOS_PARTITION
136
137/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
138#include <cmd_confdefs.h>
139
140#undef CONFIG_WATCHDOG /* watchdog disabled */
141
142#define CONFIG_RTC_MC146818 /* DS1685 is MC146818 compatible*/
143#define CFG_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */
144
145#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
146
147/*
148 * Miscellaneous configurable options
149 */
150#define CFG_LONGHELP /* undef to save memory */
151#define CFG_PROMPT "=> " /* Monitor Command Prompt */
152
wdenk1d6f9722004-09-09 17:44:35 +0000153#define CFG_HUSH_PARSER /* use "hush" command parser */
wdenk10767cc2004-05-13 13:23:58 +0000154#ifdef CFG_HUSH_PARSER
155#define CFG_PROMPT_HUSH_PS2 "> "
156#endif
157
158#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
159#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
160#else
161#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
162#endif
163#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
164#define CFG_MAXARGS 16 /* max number of command args */
165#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
166
167#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */
168
169#define CFG_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
170
171#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
172#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
173
174#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */
175#define CFG_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */
176#define CFG_BASE_BAUD 691200
177
178/* The following table includes the supported baudrates */
179#define CFG_BAUDRATE_TABLE \
180 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
181 57600, 115200, 230400, 460800, 921600 }
182
183#define CFG_LOAD_ADDR 0x100000 /* default load address */
184#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
185
186#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
187
188#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
189
190/*-----------------------------------------------------------------------
191 * NAND-FLASH stuff
192 *-----------------------------------------------------------------------
193 */
194#define CFG_NAND0_BASE 0xFF400000
195#define CFG_NAND1_BASE 0xFF000000
196
197/* For CATcenter there is only NAND on the module */
198#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */
199#define SECTORSIZE 512
200#define NAND_NO_RB
201
202#define ADDR_COLUMN 1
203#define ADDR_PAGE 2
204#define ADDR_COLUMN_PAGE 3
205
206#define NAND_ChipID_UNKNOWN 0x00
207#define NAND_MAX_FLOORS 1
208#define NAND_MAX_CHIPS 1
209
210#define CFG_NAND0_CE (0x80000000 >> 1) /* our CE is GPIO1 */
211#define CFG_NAND0_CLE (0x80000000 >> 2) /* our CLE is GPIO2 */
212#define CFG_NAND0_ALE (0x80000000 >> 3) /* our ALE is GPIO3 */
213#define CFG_NAND0_RDY (0x80000000 >> 4) /* our RDY is GPIO4 */
214
215#define CFG_NAND1_CE (0x80000000 >> 14) /* our CE is GPIO14 */
216#define CFG_NAND1_CLE (0x80000000 >> 15) /* our CLE is GPIO15 */
217#define CFG_NAND1_ALE (0x80000000 >> 16) /* our ALE is GPIO16 */
218#define CFG_NAND1_RDY (0x80000000 >> 31) /* our RDY is GPIO31 */
219
220
221#define NAND_DISABLE_CE(nand) do \
222{ \
223 switch((unsigned long)(((struct nand_chip *)nand)->IO_ADDR)) \
224 { \
225 case CFG_NAND0_BASE: \
226 out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CE); \
227 break; \
228 case CFG_NAND1_BASE: \
229 out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_CE); \
230 break; \
231 } \
232} while(0)
233
234#define NAND_ENABLE_CE(nand) do \
235{ \
236 switch((unsigned long)(((struct nand_chip *)nand)->IO_ADDR)) \
237 { \
238 case CFG_NAND0_BASE: \
239 out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_CE); \
240 break; \
241 case CFG_NAND1_BASE: \
242 out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_CE); \
243 break; \
244 } \
245} while(0)
246
247
248#define NAND_CTL_CLRALE(nandptr) do \
249{ \
250 switch((unsigned long)nandptr) \
251 { \
252 case CFG_NAND0_BASE: \
253 out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_ALE); \
254 break; \
255 case CFG_NAND1_BASE: \
256 out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_ALE); \
257 break; \
258 } \
259} while(0)
260
261#define NAND_CTL_SETALE(nandptr) do \
262{ \
263 switch((unsigned long)nandptr) \
264 { \
265 case CFG_NAND0_BASE: \
266 out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_ALE); \
267 break; \
268 case CFG_NAND1_BASE: \
269 out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_ALE); \
270 break; \
271 } \
272} while(0)
273
274#define NAND_CTL_CLRCLE(nandptr) do \
275{ \
276 switch((unsigned long)nandptr) \
277 { \
278 case CFG_NAND0_BASE: \
279 out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND0_CLE); \
280 break; \
281 case CFG_NAND1_BASE: \
282 out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_NAND1_CLE); \
283 break; \
284 } \
285} while(0)
286
287#define NAND_CTL_SETCLE(nandptr) do { \
288 switch((unsigned long)nandptr) { \
289 case CFG_NAND0_BASE: \
290 out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND0_CLE); \
291 break; \
292 case CFG_NAND1_BASE: \
293 out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND1_CLE); \
294 break; \
295 } \
296} while(0)
297
298#ifdef NAND_NO_RB
299/* constant delay (see also tR in the datasheet) */
300#define NAND_WAIT_READY(nand) do { \
301 udelay(12); \
302} while (0)
303#else
304/* use the R/B pin */
305/* TBD */
306#endif
307
308#define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
309#define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)(d); } while(0)
310#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)adr) = (__u8)d; } while(0)
311#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)adr))
312
313/*-----------------------------------------------------------------------
314 * PCI stuff
315 *-----------------------------------------------------------------------
316 */
317#if 0 /* No PCI on CATcenter */
318#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
319#define PCI_HOST_FORCE 1 /* configure as pci host */
320#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
321
322#define CONFIG_PCI /* include pci support */
323#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
324#undef CONFIG_PCI_PNP /* do pci plug-and-play */
325 /* resource configuration */
326
327#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
328
wdenk1d6f9722004-09-09 17:44:35 +0000329#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* PCI Vendor ID: IBM */
330#define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: --- */
wdenk10767cc2004-05-13 13:23:58 +0000331#define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/
wdenk1d6f9722004-09-09 17:44:35 +0000332
wdenk10767cc2004-05-13 13:23:58 +0000333#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
334#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */
335#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
336#define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */
337#define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */
338#define CFG_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
339#endif /* No PCI */
340
341/*-----------------------------------------------------------------------
342 * Start addresses for the final memory configuration
343 * (Set up by the startup code)
344 * Please note that CFG_SDRAM_BASE _must_ start at 0
345 */
346#define CFG_SDRAM_BASE 0x00000000
347#define CFG_FLASH_BASE 0xFFFC0000
348#define CFG_MONITOR_BASE CFG_FLASH_BASE
349#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
350#define CFG_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */
351
352/*
353 * For booting Linux, the board info and command line data
354 * have to be in the first 8 MB of memory, since this is
355 * the maximum mapped by the Linux kernel during initialization.
356 */
357#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
358/*-----------------------------------------------------------------------
359 * FLASH organization
360 */
361#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
362#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
363
364#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
365#define CFG_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */
366
367#define CFG_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
368#define CFG_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
369#define CFG_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
370/*
371 * The following defines are added for buggy IOP480 byte interface.
372 * All other boards should use the standard values (CPCI405 etc.)
373 */
374#define CFG_FLASH_READ0 0x0000 /* 0 is standard */
375#define CFG_FLASH_READ1 0x0001 /* 1 is standard */
376#define CFG_FLASH_READ2 0x0002 /* 2 is standard */
377
378#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
379
wdenk10767cc2004-05-13 13:23:58 +0000380/*-----------------------------------------------------------------------
381 * Environment Variable setup
382 */
383#define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
384#define CFG_ENV_ADDR 0xFFFF8000 /* environment starts at the first small sector */
385#define CFG_ENV_SECT_SIZE 0x2000 /* 8196 bytes may be used for env vars*/
386#define CFG_ENV_ADDR_REDUND 0xFFFFA000
387#define CFG_ENV_SIZE_REDUND 0x2000
388
389#define CFG_NVRAM_BASE_ADDR 0xF0000500 /* NVRAM base address */
390#define CFG_NVRAM_SIZE 242 /* NVRAM size */
391
392/*-----------------------------------------------------------------------
393 * I2C EEPROM (CAT24WC16) for environment
394 */
395#define CONFIG_HARD_I2C /* I2c with hardware support */
396#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
397#define CFG_I2C_SLAVE 0x7F
398
399#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
400#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
401/* mask of address bits that overflow into the "EEPROM chip address" */
402/*#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07*/
403#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
404 /* 16 byte page write mode using*/
405 /* last 4 bits of the address */
406#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
407#define CFG_EEPROM_PAGE_WRITE_ENABLE
408
409/*-----------------------------------------------------------------------
410 * Cache Configuration
411 */
Wolfgang Denk0c8721a2005-09-23 11:05:55 +0200412#define CFG_DCACHE_SIZE 16384 /* For AMCC 405 CPUs, older 405 ppc's */
wdenk10767cc2004-05-13 13:23:58 +0000413 /* have only 8kB, 16kB is save here */
414#define CFG_CACHELINE_SIZE 32 /* ... */
415#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
416#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
417#endif
418
419/*
420 * Init Memory Controller:
421 *
422 * BR0/1 and OR0/1 (FLASH)
423 */
424
425#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
426
427/*-----------------------------------------------------------------------
428 * External Bus Controller (EBC) Setup
429 */
430
431/* Memory Bank 0 (Flash Bank 0, NOR-FLASH) initialization */
432#define CFG_EBC_PB0AP 0x92015480
433#define CFG_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
434
435/* Memory Bank 1 (External SRAM) initialization */
436/* Since this must replace NOR Flash, we use the same settings for CS0 */
437#define CFG_EBC_PB1AP 0x92015480
438#define CFG_EBC_PB1CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit */
439
440/* Memory Bank 2 (Flash Bank 1, NAND-FLASH) initialization */
441#define CFG_EBC_PB2AP 0x92015480
442#define CFG_EBC_PB2CR 0xFF458000 /* BAS=0xFF4,BS=4MB,BU=R/W,BW=8bit */
443
444/* Memory Bank 3 (Flash Bank 2, NAND-FLASH) initialization */
445#define CFG_EBC_PB3AP 0x92015480
446#define CFG_EBC_PB3CR 0xFF058000 /* BAS=0xFF0,BS=4MB,BU=R/W,BW=8bit */
447
wdenk1d6f9722004-09-09 17:44:35 +0000448#ifdef CONFIG_PPCHAMELEON_SMI712
449/*
450 * Video console (graphic: SMI LynxEM)
451 */
452#define CONFIG_VIDEO
453#define CONFIG_CFB_CONSOLE
454#define CONFIG_VIDEO_SMI_LYNXEM
455#define CONFIG_VIDEO_LOGO
456/*#define CONFIG_VIDEO_BMP_LOGO*/
457#define CONFIG_CONSOLE_EXTRA_INFO
458#define CONFIG_VGA_AS_SINGLE_DEVICE
459/* This is the base address (on 405EP-side) used to generate I/O accesses on PCI bus */
460#define CFG_ISA_IO 0xE8000000
461/* see also drivers/videomodes.c */
462#define CFG_DEFAULT_VIDEO_MODE 0x303
wdenk10767cc2004-05-13 13:23:58 +0000463#endif
464
465/*-----------------------------------------------------------------------
466 * FPGA stuff
467 */
468/* FPGA internal regs */
469#define CFG_FPGA_MODE 0x00
470#define CFG_FPGA_STATUS 0x02
471#define CFG_FPGA_TS 0x04
472#define CFG_FPGA_TS_LOW 0x06
473#define CFG_FPGA_TS_CAP0 0x10
474#define CFG_FPGA_TS_CAP0_LOW 0x12
475#define CFG_FPGA_TS_CAP1 0x14
476#define CFG_FPGA_TS_CAP1_LOW 0x16
477#define CFG_FPGA_TS_CAP2 0x18
478#define CFG_FPGA_TS_CAP2_LOW 0x1a
479#define CFG_FPGA_TS_CAP3 0x1c
480#define CFG_FPGA_TS_CAP3_LOW 0x1e
481
482/* FPGA Mode Reg */
483#define CFG_FPGA_MODE_CF_RESET 0x0001
484#define CFG_FPGA_MODE_TS_IRQ_ENABLE 0x0100
485#define CFG_FPGA_MODE_TS_IRQ_CLEAR 0x1000
486#define CFG_FPGA_MODE_TS_CLEAR 0x2000
487
488/* FPGA Status Reg */
489#define CFG_FPGA_STATUS_DIP0 0x0001
490#define CFG_FPGA_STATUS_DIP1 0x0002
491#define CFG_FPGA_STATUS_DIP2 0x0004
492#define CFG_FPGA_STATUS_FLASH 0x0008
493#define CFG_FPGA_STATUS_TS_IRQ 0x1000
494
495#define CFG_FPGA_SPARTAN2 1 /* using Xilinx Spartan 2 now */
496#define CFG_FPGA_MAX_SIZE 128*1024 /* 128kByte is enough for XC2S50E*/
497
498/* FPGA program pin configuration */
499#define CFG_FPGA_PRG 0x04000000 /* FPGA program pin (ppc output) */
500#define CFG_FPGA_CLK 0x02000000 /* FPGA clk pin (ppc output) */
501#define CFG_FPGA_DATA 0x01000000 /* FPGA data pin (ppc output) */
502#define CFG_FPGA_INIT 0x00010000 /* FPGA init pin (ppc input) */
503#define CFG_FPGA_DONE 0x00008000 /* FPGA done pin (ppc input) */
504
505/*-----------------------------------------------------------------------
506 * Definitions for initial stack pointer and data area (in data cache)
507 */
508/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
wdenk1d6f9722004-09-09 17:44:35 +0000509#define CFG_TEMP_STACK_OCM 1
wdenk10767cc2004-05-13 13:23:58 +0000510
511/* On Chip Memory location */
512#define CFG_OCM_DATA_ADDR 0xF8000000
513#define CFG_OCM_DATA_SIZE 0x1000
514#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */
515#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
516
517#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
518#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
519#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
520
521/*-----------------------------------------------------------------------
522 * Definitions for GPIO setup (PPC405EP specific)
523 *
524 * GPIO0[0] - External Bus Controller BLAST output
525 * GPIO0[1-9] - Instruction trace outputs -> GPIO
526 * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
527 * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs -> GPIO
528 * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
529 * GPIO0[24-27] - UART0 control signal inputs/outputs
530 * GPIO0[28-29] - UART1 data signal input/output
531 * GPIO0[30] - EMAC0 input
532 * GPIO0[31] - EMAC1 reject packet as output
533 */
534#define CFG_GPIO0_OSRH 0x40000550
535#define CFG_GPIO0_OSRL 0x00000110
536#define CFG_GPIO0_ISR1H 0x00000000
537/*#define CFG_GPIO0_ISR1L 0x15555445*/
538#define CFG_GPIO0_ISR1L 0x15555444
539#define CFG_GPIO0_TSRH 0x00000000
540#define CFG_GPIO0_TSRL 0x00000000
541#define CFG_GPIO0_TCR 0xF7FF8014
542
543/*
544 * Internal Definitions
545 *
546 * Boot Flags
547 */
548#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
549#define BOOTFLAG_WARM 0x02 /* Software reboot */
550
551
552#define CONFIG_NO_SERIAL_EEPROM
553
554/*--------------------------------------------------------------------*/
555
556#ifdef CONFIG_NO_SERIAL_EEPROM
557
558/*
559!-----------------------------------------------------------------------
560! Defines for entry options.
561! Note: Because the 405EP SDRAM controller does not support ECC, ECC DIMMs that
562! are plugged in the board will be utilized as non-ECC DIMMs.
563!-----------------------------------------------------------------------
564*/
565#undef AUTO_MEMORY_CONFIG
566#define DIMM_READ_ADDR 0xAB
567#define DIMM_WRITE_ADDR 0xAA
568
wdenk10767cc2004-05-13 13:23:58 +0000569#define CPC0_PLLMR0 (CNTRL_DCR_BASE+0x0) /* PLL mode 0 register */
570#define CPC0_BOOT (CNTRL_DCR_BASE+0x1) /* Chip Clock Status register */
571#define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* Chip Control 1 register */
572#define CPC0_EPRCSR (CNTRL_DCR_BASE+0x3) /* EMAC PHY Rcv Clk Src register */
573#define CPC0_PLLMR1 (CNTRL_DCR_BASE+0x4) /* PLL mode 1 register */
574#define CPC0_UCR (CNTRL_DCR_BASE+0x5) /* UART Control register */
575#define CPC0_SRR (CNTRL_DCR_BASE+0x6) /* Soft Reset register */
576#define CPC0_JTAGID (CNTRL_DCR_BASE+0x7) /* JTAG ID register */
577#define CPC0_SPARE (CNTRL_DCR_BASE+0x8) /* Spare DCR */
578#define CPC0_PCI (CNTRL_DCR_BASE+0x9) /* PCI Control register */
579
580/* Defines for CPC0_PLLMR1 Register fields */
581#define PLL_ACTIVE 0x80000000
582#define CPC0_PLLMR1_SSCS 0x80000000
583#define PLL_RESET 0x40000000
584#define CPC0_PLLMR1_PLLR 0x40000000
585 /* Feedback multiplier */
586#define PLL_FBKDIV 0x00F00000
587#define CPC0_PLLMR1_FBDV 0x00F00000
588#define PLL_FBKDIV_16 0x00000000
589#define PLL_FBKDIV_1 0x00100000
590#define PLL_FBKDIV_2 0x00200000
591#define PLL_FBKDIV_3 0x00300000
592#define PLL_FBKDIV_4 0x00400000
593#define PLL_FBKDIV_5 0x00500000
594#define PLL_FBKDIV_6 0x00600000
595#define PLL_FBKDIV_7 0x00700000
596#define PLL_FBKDIV_8 0x00800000
597#define PLL_FBKDIV_9 0x00900000
598#define PLL_FBKDIV_10 0x00A00000
599#define PLL_FBKDIV_11 0x00B00000
600#define PLL_FBKDIV_12 0x00C00000
601#define PLL_FBKDIV_13 0x00D00000
602#define PLL_FBKDIV_14 0x00E00000
603#define PLL_FBKDIV_15 0x00F00000
604 /* Forward A divisor */
605#define PLL_FWDDIVA 0x00070000
606#define CPC0_PLLMR1_FWDVA 0x00070000
607#define PLL_FWDDIVA_8 0x00000000
608#define PLL_FWDDIVA_7 0x00010000
609#define PLL_FWDDIVA_6 0x00020000
610#define PLL_FWDDIVA_5 0x00030000
611#define PLL_FWDDIVA_4 0x00040000
612#define PLL_FWDDIVA_3 0x00050000
613#define PLL_FWDDIVA_2 0x00060000
614#define PLL_FWDDIVA_1 0x00070000
615 /* Forward B divisor */
616#define PLL_FWDDIVB 0x00007000
617#define CPC0_PLLMR1_FWDVB 0x00007000
618#define PLL_FWDDIVB_8 0x00000000
619#define PLL_FWDDIVB_7 0x00001000
620#define PLL_FWDDIVB_6 0x00002000
621#define PLL_FWDDIVB_5 0x00003000
622#define PLL_FWDDIVB_4 0x00004000
623#define PLL_FWDDIVB_3 0x00005000
624#define PLL_FWDDIVB_2 0x00006000
625#define PLL_FWDDIVB_1 0x00007000
626 /* PLL tune bits */
627#define PLL_TUNE_MASK 0x000003FF
628#define PLL_TUNE_2_M_3 0x00000133 /* 2 <= M <= 3 */
629#define PLL_TUNE_4_M_6 0x00000134 /* 3 < M <= 6 */
630#define PLL_TUNE_7_M_10 0x00000138 /* 6 < M <= 10 */
631#define PLL_TUNE_11_M_14 0x0000013C /* 10 < M <= 14 */
632#define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */
633#define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */
634#define PLL_TUNE_VCO_HI 0x00000080 /* 800MHz < VCO <= 1000MHz */
635
636/* Defines for CPC0_PLLMR0 Register fields */
637 /* CPU divisor */
638#define PLL_CPUDIV 0x00300000
639#define CPC0_PLLMR0_CCDV 0x00300000
640#define PLL_CPUDIV_1 0x00000000
641#define PLL_CPUDIV_2 0x00100000
642#define PLL_CPUDIV_3 0x00200000
643#define PLL_CPUDIV_4 0x00300000
644 /* PLB divisor */
645#define PLL_PLBDIV 0x00030000
646#define CPC0_PLLMR0_CBDV 0x00030000
647#define PLL_PLBDIV_1 0x00000000
648#define PLL_PLBDIV_2 0x00010000
649#define PLL_PLBDIV_3 0x00020000
650#define PLL_PLBDIV_4 0x00030000
651 /* OPB divisor */
652#define PLL_OPBDIV 0x00003000
653#define CPC0_PLLMR0_OPDV 0x00003000
654#define PLL_OPBDIV_1 0x00000000
655#define PLL_OPBDIV_2 0x00001000
656#define PLL_OPBDIV_3 0x00002000
657#define PLL_OPBDIV_4 0x00003000
658 /* EBC divisor */
659#define PLL_EXTBUSDIV 0x00000300
660#define CPC0_PLLMR0_EPDV 0x00000300
661#define PLL_EXTBUSDIV_2 0x00000000
662#define PLL_EXTBUSDIV_3 0x00000100
663#define PLL_EXTBUSDIV_4 0x00000200
664#define PLL_EXTBUSDIV_5 0x00000300
665 /* MAL divisor */
666#define PLL_MALDIV 0x00000030
667#define CPC0_PLLMR0_MPDV 0x00000030
668#define PLL_MALDIV_1 0x00000000
669#define PLL_MALDIV_2 0x00000010
670#define PLL_MALDIV_3 0x00000020
671#define PLL_MALDIV_4 0x00000030
672 /* PCI divisor */
673#define PLL_PCIDIV 0x00000003
674#define CPC0_PLLMR0_PPFD 0x00000003
675#define PLL_PCIDIV_1 0x00000000
676#define PLL_PCIDIV_2 0x00000001
677#define PLL_PCIDIV_3 0x00000002
678#define PLL_PCIDIV_4 0x00000003
679
wdenk1d6f9722004-09-09 17:44:35 +0000680#ifdef CONFIG_PPCHAMELEON_CLK_25
681/* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 25.0 MHz input clock to the 405EP) */
682#define PPCHAMELEON_PLLMR0_133_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \
683 PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
684 PLL_MALDIV_1 | PLL_PCIDIV_4)
685#define PPCHAMELEON_PLLMR1_133_133_33_66_33 (PLL_FBKDIV_8 | \
686 PLL_FWDDIVA_6 | PLL_FWDDIVB_4 | \
687 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
688
689#define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
690 PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
691 PLL_MALDIV_1 | PLL_PCIDIV_4)
692#define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_8 | \
693 PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \
694 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
695
696#define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
697 PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
698 PLL_MALDIV_1 | PLL_PCIDIV_4)
699#define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8 | \
700 PLL_FWDDIVA_3 | PLL_FWDDIVB_4 | \
701 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
702
703#define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
704 PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
705 PLL_MALDIV_1 | PLL_PCIDIV_2)
706#define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10 | \
707 PLL_FWDDIVA_3 | PLL_FWDDIVB_4 | \
708 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
709
710#elif (defined (CONFIG_PPCHAMELEON_CLK_33))
711
wdenk10767cc2004-05-13 13:23:58 +0000712/* CPU - PLB/SDRAM - EBC - OPB - PCI (assuming a 33.3MHz input clock to the 405EP) */
wdenk1d6f9722004-09-09 17:44:35 +0000713#define PPCHAMELEON_PLLMR0_133_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \
714 PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
wdenk10767cc2004-05-13 13:23:58 +0000715 PLL_MALDIV_1 | PLL_PCIDIV_4)
wdenk1d6f9722004-09-09 17:44:35 +0000716#define PPCHAMELEON_PLLMR1_133_133_33_66_33 (PLL_FBKDIV_4 | \
717 PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \
wdenk10767cc2004-05-13 13:23:58 +0000718 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
wdenk1d6f9722004-09-09 17:44:35 +0000719
720#define PPCHAMELEON_PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
721 PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
wdenk10767cc2004-05-13 13:23:58 +0000722 PLL_MALDIV_1 | PLL_PCIDIV_4)
wdenk1d6f9722004-09-09 17:44:35 +0000723#define PPCHAMELEON_PLLMR1_200_100_50_33 (PLL_FBKDIV_6 | \
724 PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \
wdenk10767cc2004-05-13 13:23:58 +0000725 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
wdenk1d6f9722004-09-09 17:44:35 +0000726
727#define PPCHAMELEON_PLLMR0_266_133_33_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \
728 PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \
wdenk10767cc2004-05-13 13:23:58 +0000729 PLL_MALDIV_1 | PLL_PCIDIV_4)
wdenk1d6f9722004-09-09 17:44:35 +0000730#define PPCHAMELEON_PLLMR1_266_133_33_66_33 (PLL_FBKDIV_8 | \
731 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
wdenk10767cc2004-05-13 13:23:58 +0000732 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW)
wdenk1d6f9722004-09-09 17:44:35 +0000733
734#define PPCHAMELEON_PLLMR0_333_111_37_55_55 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \
735 PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \
wdenk10767cc2004-05-13 13:23:58 +0000736 PLL_MALDIV_1 | PLL_PCIDIV_2)
wdenk1d6f9722004-09-09 17:44:35 +0000737#define PPCHAMELEON_PLLMR1_333_111_37_55_55 (PLL_FBKDIV_10 | \
738 PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \
wdenk10767cc2004-05-13 13:23:58 +0000739 PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
740
wdenk1d6f9722004-09-09 17:44:35 +0000741#else
742#error "* External frequency (SysClk) not defined! *"
743#endif
744
wdenk10767cc2004-05-13 13:23:58 +0000745#if (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_HI)
746/* Model HI */
wdenk1d6f9722004-09-09 17:44:35 +0000747#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_333_111_37_55_55
748#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_333_111_37_55_55
749#define CFG_OPB_FREQ 55555555
wdenk10767cc2004-05-13 13:23:58 +0000750/* Model ME */
751#elif (CONFIG_PPCHAMELEON_MODULE_MODEL == CONFIG_PPCHAMELEON_MODULE_ME)
wdenk1d6f9722004-09-09 17:44:35 +0000752#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_266_133_33_66_33
753#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_266_133_33_66_33
754#define CFG_OPB_FREQ 66666666
wdenk10767cc2004-05-13 13:23:58 +0000755#else
756/* Model BA (default) */
wdenk1d6f9722004-09-09 17:44:35 +0000757#define PLLMR0_DEFAULT PPCHAMELEON_PLLMR0_133_133_33_66_33
758#define PLLMR1_DEFAULT PPCHAMELEON_PLLMR1_133_133_33_66_33
759#define CFG_OPB_FREQ 66666666
wdenk10767cc2004-05-13 13:23:58 +0000760#endif
761
762#endif /* CONFIG_NO_SERIAL_EEPROM */
763
764#define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */
wdenk10767cc2004-05-13 13:23:58 +0000765#define NAND_CACHE_PAGES 16 /* size of nand cache in 512 bytes pages */
766
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200767/*
768 * JFFS2 partitions
769 *
770 */
771/* No command line, one static partition */
772#undef CONFIG_JFFS2_CMDLINE
773#define CONFIG_JFFS2_DEV "nand"
774#define CONFIG_JFFS2_PART_SIZE 0x00200000
775#define CONFIG_JFFS2_PART_OFFSET 0x00000000
776
777/* mtdparts command line support
778 *
779 * Note: fake mtd_id used, no linux mtd map file
780 */
781/*
782#define CONFIG_JFFS2_CMDLINE
783#define MTDIDS_DEFAULT "nand0=catcenter"
784#define MTDPARTS_DEFAULT "mtdparts=catcenter:2m(nand)"
785*/
786
wdenk10767cc2004-05-13 13:23:58 +0000787#endif /* __CONFIG_H */