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wdenkbf9e3b32004-02-12 00:47:09 +00001/*
2 * Configuation settings for the Motorola MC5282EVB board.
3 *
4 * (C) Copyright 2003 Josef Baumgartner <josef.baumgartner@telex.de>
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
wdenkbf9e3b32004-02-12 00:47:09 +00007 */
8
9/*
10 * board/config.h - configuration options, board specific
11 */
12
wdenk4e5ca3e2003-12-08 01:34:36 +000013#ifndef _CONFIG_M5282EVB_H
14#define _CONFIG_M5282EVB_H
15
wdenkbf9e3b32004-02-12 00:47:09 +000016/*
17 * High Level Configuration Options
18 * (easy to change)
19 */
TsiChungLiewf28e1bd2007-08-15 20:32:06 -050020#define CONFIG_MCF52x2 /* define processor family */
21#define CONFIG_M5282 /* define processor type */
wdenk4e5ca3e2003-12-08 01:34:36 +000022
TsiChungLiewf28e1bd2007-08-15 20:32:06 -050023#define CONFIG_MCFTMR
wdenk4e5ca3e2003-12-08 01:34:36 +000024
TsiChungLiewf28e1bd2007-08-15 20:32:06 -050025#define CONFIG_MCFUART
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020026#define CONFIG_SYS_UART_PORT (0)
TsiChung Liew79e07992008-08-15 16:50:07 +000027#define CONFIG_BAUDRATE 115200
wdenkbf9e3b32004-02-12 00:47:09 +000028
TsiChungLiewf28e1bd2007-08-15 20:32:06 -050029#undef CONFIG_MONITOR_IS_IN_RAM /* define if monitor is started from a pre-loader */
wdenkbf9e3b32004-02-12 00:47:09 +000030
31/* Configuration for environment
32 * Environment is embedded in u-boot in the second sector of the flash
33 */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +020034#define CONFIG_ENV_ADDR 0xffe04000
35#define CONFIG_ENV_SIZE 0x2000
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +020036#define CONFIG_ENV_IS_IN_FLASH 1
wdenkbf9e3b32004-02-12 00:47:09 +000037
Jon Loeliger8353e132007-07-08 14:14:17 -050038/*
Jon Loeliger659e2f62007-07-10 09:10:49 -050039 * BOOTP options
40 */
41#define CONFIG_BOOTP_BOOTFILESIZE
42#define CONFIG_BOOTP_BOOTPATH
43#define CONFIG_BOOTP_GATEWAY
44#define CONFIG_BOOTP_HOSTNAME
45
Jon Loeliger659e2f62007-07-10 09:10:49 -050046/*
Jon Loeliger8353e132007-07-08 14:14:17 -050047 * Command line configuration.
48 */
49#include <config_cmd_default.h>
TsiChung Liewdd9f0542010-03-11 22:12:53 -060050#define CONFIG_CMD_CACHE
TsiChungLiewf28e1bd2007-08-15 20:32:06 -050051#define CONFIG_CMD_NET
52#define CONFIG_CMD_PING
53#define CONFIG_CMD_MII
wdenkbf9e3b32004-02-12 00:47:09 +000054
Jon Loeliger8353e132007-07-08 14:14:17 -050055#undef CONFIG_CMD_LOADS
56#undef CONFIG_CMD_LOADB
57
TsiChungLiewf28e1bd2007-08-15 20:32:06 -050058#define CONFIG_MCFFEC
59#ifdef CONFIG_MCFFEC
TsiChungLiewf28e1bd2007-08-15 20:32:06 -050060# define CONFIG_MII 1
TsiChung Liew0f3ba7e2008-03-30 01:22:13 -050061# define CONFIG_MII_INIT 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020062# define CONFIG_SYS_DISCOVER_PHY
63# define CONFIG_SYS_RX_ETH_BUFFER 8
64# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
TsiChungLiewf28e1bd2007-08-15 20:32:06 -050065
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020066# define CONFIG_SYS_FEC0_PINMUX 0
67# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
Wolfgang Denk53677ef2008-05-20 16:00:29 +020068# define MCFFEC_TOUT_LOOP 50000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020069/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
70# ifndef CONFIG_SYS_DISCOVER_PHY
TsiChungLiewf28e1bd2007-08-15 20:32:06 -050071# define FECDUPLEX FULL
72# define FECSPEED _100BASET
73# else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020074# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
75# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
TsiChungLiewf28e1bd2007-08-15 20:32:06 -050076# endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020077# endif /* CONFIG_SYS_DISCOVER_PHY */
TsiChungLiewf28e1bd2007-08-15 20:32:06 -050078#endif
Jon Loeliger8353e132007-07-08 14:14:17 -050079
wdenkbf9e3b32004-02-12 00:47:09 +000080#define CONFIG_BOOTDELAY 5
TsiChungLiewf28e1bd2007-08-15 20:32:06 -050081#ifdef CONFIG_MCFFEC
82# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
83# define CONFIG_IPADDR 192.162.1.2
84# define CONFIG_NETMASK 255.255.255.0
85# define CONFIG_SERVERIP 192.162.1.1
86# define CONFIG_GATEWAYIP 192.162.1.1
87# define CONFIG_OVERWRITE_ETHADDR_ONCE
88#endif /* CONFIG_MCFFEC */
89
TsiChung Liew4cb4e652008-08-11 15:54:25 +000090#define CONFIG_HOSTNAME M5282EVB
TsiChungLiewf28e1bd2007-08-15 20:32:06 -050091#define CONFIG_EXTRA_ENV_SETTINGS \
92 "netdev=eth0\0" \
93 "loadaddr=10000\0" \
94 "u-boot=u-boot.bin\0" \
95 "load=tftp ${loadaddr) ${u-boot}\0" \
96 "upd=run load; run prog\0" \
97 "prog=prot off ffe00000 ffe3ffff;" \
98 "era ffe00000 ffe3ffff;" \
99 "cp.b ${loadaddr} ffe00000 ${filesize};"\
100 "save\0" \
101 ""
wdenkbf9e3b32004-02-12 00:47:09 +0000102
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200103#define CONFIG_SYS_PROMPT "-> "
104#define CONFIG_SYS_LONGHELP /* undef to save memory */
wdenkbf9e3b32004-02-12 00:47:09 +0000105
Jon Loeliger8353e132007-07-08 14:14:17 -0500106#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200107#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkbf9e3b32004-02-12 00:47:09 +0000108#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200109#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkbf9e3b32004-02-12 00:47:09 +0000110#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200111#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
112#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
113#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenkbf9e3b32004-02-12 00:47:09 +0000114
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200115#define CONFIG_SYS_LOAD_ADDR 0x20000
wdenkbf9e3b32004-02-12 00:47:09 +0000116
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200117#define CONFIG_SYS_MEMTEST_START 0x400
118#define CONFIG_SYS_MEMTEST_END 0x380000
wdenkbf9e3b32004-02-12 00:47:09 +0000119
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200120#define CONFIG_SYS_CLK 64000000
wdenkbf9e3b32004-02-12 00:47:09 +0000121
TsiChungLiewf28e1bd2007-08-15 20:32:06 -0500122/* PLL Configuration: Ext Clock * 6 (see table 9-4 of MCF user manual) */
123
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200124#define CONFIG_SYS_MFD 0x02 /* PLL Multiplication Factor Devider */
125#define CONFIG_SYS_RFD 0x00 /* PLL Reduce Frecuency Devider */
wdenkbf9e3b32004-02-12 00:47:09 +0000126
127/*
128 * Low Level Configuration Settings
129 * (address mappings, register initial values, etc.)
130 * You should know what you are doing if you make changes here.
131 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200132#define CONFIG_SYS_MBAR 0x40000000
wdenkbf9e3b32004-02-12 00:47:09 +0000133
wdenkbf9e3b32004-02-12 00:47:09 +0000134/*-----------------------------------------------------------------------
135 * Definitions for initial stack pointer and data area (in DPRAM)
136 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200137#define CONFIG_SYS_INIT_RAM_ADDR 0x20000000
Wolfgang Denk553f0982010-10-26 13:32:32 +0200138#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200139#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200140#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkbf9e3b32004-02-12 00:47:09 +0000141
142/*-----------------------------------------------------------------------
143 * Start addresses for the final memory configuration
144 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200145 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenkbf9e3b32004-02-12 00:47:09 +0000146 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200147#define CONFIG_SYS_SDRAM_BASE 0x00000000
148#define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
TsiChung Liew012522f2008-10-21 10:03:07 +0000149#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200150#define CONFIG_SYS_INT_FLASH_BASE 0xf0000000
151#define CONFIG_SYS_INT_FLASH_ENABLE 0x21
wdenkbf9e3b32004-02-12 00:47:09 +0000152
153/* If M5282 port is fully implemented the monitor base will be behind
154 * the vector table. */
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200155#if (CONFIG_SYS_TEXT_BASE != CONFIG_SYS_INT_FLASH_BASE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200156#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
TsiChungLiewf28e1bd2007-08-15 20:32:06 -0500157#else
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200158#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x418) /* 24 Byte for CFM-Config */
TsiChungLiewf28e1bd2007-08-15 20:32:06 -0500159#endif
wdenkbf9e3b32004-02-12 00:47:09 +0000160
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200161#define CONFIG_SYS_MONITOR_LEN 0x20000
162#define CONFIG_SYS_MALLOC_LEN (256 << 10)
163#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
wdenkbf9e3b32004-02-12 00:47:09 +0000164
wdenkbf9e3b32004-02-12 00:47:09 +0000165/*
166 * For booting Linux, the board info and command line data
167 * have to be in the first 8 MB of memory, since this is
168 * the maximum mapped by the Linux kernel during initialization ??
169 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200170#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
wdenkbf9e3b32004-02-12 00:47:09 +0000171
172/*-----------------------------------------------------------------------
173 * FLASH organization
174 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200175#define CONFIG_SYS_FLASH_CFI
176#ifdef CONFIG_SYS_FLASH_CFI
TsiChungLiewf28e1bd2007-08-15 20:32:06 -0500177
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200178# define CONFIG_FLASH_CFI_DRIVER 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200179# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
180# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
181# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
182# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
183# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
184# define CONFIG_SYS_FLASH_CHECKSUM
185# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
TsiChungLiewf28e1bd2007-08-15 20:32:06 -0500186#endif
wdenkbf9e3b32004-02-12 00:47:09 +0000187
188/*-----------------------------------------------------------------------
189 * Cache Configuration
190 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200191#define CONFIG_SYS_CACHELINE_SIZE 16
wdenkbf9e3b32004-02-12 00:47:09 +0000192
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600193#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk553f0982010-10-26 13:32:32 +0200194 CONFIG_SYS_INIT_RAM_SIZE - 8)
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600195#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
Wolfgang Denk553f0982010-10-26 13:32:32 +0200196 CONFIG_SYS_INIT_RAM_SIZE - 4)
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600197#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV + CF_CACR_DCM)
198#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \
199 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
200 CF_ACR_EN | CF_ACR_SM_ALL)
201#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \
202 CF_CACR_CEIB | CF_CACR_DBWE | \
203 CF_CACR_EUSP)
204
wdenkbf9e3b32004-02-12 00:47:09 +0000205/*-----------------------------------------------------------------------
206 * Memory bank definitions
207 */
TsiChung Liew012522f2008-10-21 10:03:07 +0000208#define CONFIG_SYS_CS0_BASE 0xFFE00000
209#define CONFIG_SYS_CS0_CTRL 0x00001980
210#define CONFIG_SYS_CS0_MASK 0x001F0001
211
wdenkbf9e3b32004-02-12 00:47:09 +0000212/*-----------------------------------------------------------------------
213 * Port configuration
214 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200215#define CONFIG_SYS_PACNT 0x0000000 /* Port A D[31:24] */
216#define CONFIG_SYS_PADDR 0x0000000
217#define CONFIG_SYS_PADAT 0x0000000
wdenkbf9e3b32004-02-12 00:47:09 +0000218
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200219#define CONFIG_SYS_PBCNT 0x0000000 /* Port B D[23:16] */
220#define CONFIG_SYS_PBDDR 0x0000000
221#define CONFIG_SYS_PBDAT 0x0000000
wdenk4e5ca3e2003-12-08 01:34:36 +0000222
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200223#define CONFIG_SYS_PCCNT 0x0000000 /* Port C D[15:08] */
224#define CONFIG_SYS_PCDDR 0x0000000
225#define CONFIG_SYS_PCDAT 0x0000000
TsiChungLiewf28e1bd2007-08-15 20:32:06 -0500226
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200227#define CONFIG_SYS_PDCNT 0x0000000 /* Port D D[07:00] */
228#define CONFIG_SYS_PCDDR 0x0000000
229#define CONFIG_SYS_PCDAT 0x0000000
TsiChungLiewf28e1bd2007-08-15 20:32:06 -0500230
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200231#define CONFIG_SYS_PEHLPAR 0xC0
232#define CONFIG_SYS_PUAPAR 0x0F /* UA0..UA3 = Uart 0 +1 */
233#define CONFIG_SYS_DDRUA 0x05
234#define CONFIG_SYS_PJPAR 0xFF
TsiChungLiewf28e1bd2007-08-15 20:32:06 -0500235
236#endif /* _CONFIG_M5282EVB_H */