blob: 5b4bba8c26cd5c5660785e82f093f07fe8199b8c [file] [log] [blame]
TsiChungLiew8ae158c2007-08-16 15:05:11 -05001/*
2 * Configuation settings for the Freescale MCF54455 EVB board.
3 *
4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26/*
27 * board/config.h - configuration options, board specific
28 */
29
TsiChungLiewe8ee8f32007-10-25 17:16:22 -050030#ifndef _M54455EVB_H
31#define _M54455EVB_H
TsiChungLiew8ae158c2007-08-16 15:05:11 -050032
33/*
34 * High Level Configuration Options
35 * (easy to change)
36 */
37#define CONFIG_MCF5445x /* define processor family */
38#define CONFIG_M54455 /* define processor type */
39#define CONFIG_M54455EVB /* M54455EVB board */
40
TsiChungLiew8ae158c2007-08-16 15:05:11 -050041#define CONFIG_MCFUART
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020042#define CONFIG_SYS_UART_PORT (0)
TsiChungLiew8ae158c2007-08-16 15:05:11 -050043#define CONFIG_BAUDRATE 115200
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020044#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 }
TsiChungLiew8ae158c2007-08-16 15:05:11 -050045
46#undef CONFIG_WATCHDOG
47
48#define CONFIG_TIMESTAMP /* Print image info with timestamp */
49
50/*
51 * BOOTP options
52 */
53#define CONFIG_BOOTP_BOOTFILESIZE
54#define CONFIG_BOOTP_BOOTPATH
55#define CONFIG_BOOTP_GATEWAY
56#define CONFIG_BOOTP_HOSTNAME
57
58/* Command line configuration */
59#include <config_cmd_default.h>
60
61#define CONFIG_CMD_BOOTD
62#define CONFIG_CMD_CACHE
63#define CONFIG_CMD_DATE
64#define CONFIG_CMD_DHCP
65#define CONFIG_CMD_ELF
66#define CONFIG_CMD_EXT2
67#define CONFIG_CMD_FAT
68#define CONFIG_CMD_FLASH
69#define CONFIG_CMD_I2C
70#define CONFIG_CMD_IDE
71#define CONFIG_CMD_JFFS2
72#define CONFIG_CMD_MEMORY
73#define CONFIG_CMD_MISC
74#define CONFIG_CMD_MII
75#define CONFIG_CMD_NET
TsiChungLiewe8ee8f32007-10-25 17:16:22 -050076#undef CONFIG_CMD_PCI
TsiChungLiew8ae158c2007-08-16 15:05:11 -050077#define CONFIG_CMD_PING
78#define CONFIG_CMD_REGINFO
TsiChung Liewa7323bb2008-07-23 17:53:36 -050079#define CONFIG_CMD_SPI
TsiChung Liew922cd752008-08-06 19:14:08 -050080#define CONFIG_CMD_SF
TsiChungLiew8ae158c2007-08-16 15:05:11 -050081
82#undef CONFIG_CMD_LOADB
83#undef CONFIG_CMD_LOADS
84
85/* Network configuration */
86#define CONFIG_MCFFEC
87#ifdef CONFIG_MCFFEC
TsiChung Liew0f3ba7e2008-03-30 01:22:13 -050088# define CONFIG_NET_MULTI 1
TsiChungLiew8ae158c2007-08-16 15:05:11 -050089# define CONFIG_MII 1
TsiChung Liew0f3ba7e2008-03-30 01:22:13 -050090# define CONFIG_MII_INIT 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020091# define CONFIG_SYS_DISCOVER_PHY
92# define CONFIG_SYS_RX_ETH_BUFFER 8
93# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
TsiChungLiew8ae158c2007-08-16 15:05:11 -050094
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020095# define CONFIG_SYS_FEC0_PINMUX 0
96# define CONFIG_SYS_FEC1_PINMUX 0
97# define CONFIG_SYS_FEC0_MIIBASE CONFIG_SYS_FEC0_IOBASE
98# define CONFIG_SYS_FEC1_MIIBASE CONFIG_SYS_FEC0_IOBASE
TsiChungLiew8ae158c2007-08-16 15:05:11 -050099# define MCFFEC_TOUT_LOOP 50000
100# define CONFIG_HAS_ETH1
101
102# define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
103# define CONFIG_BOOTARGS "root=/dev/mtdblock1 rw rootfstype=jffs2 ip=none mtdparts=physmap-flash.0:5M(kernel)ro,-(jffs2)"
104# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60
105# define CONFIG_ETH1ADDR 00:e0:0c:bc:e5:61
106# define CONFIG_ETHPRIME "FEC0"
107# define CONFIG_IPADDR 192.162.1.2
108# define CONFIG_NETMASK 255.255.255.0
109# define CONFIG_SERVERIP 192.162.1.1
110# define CONFIG_GATEWAYIP 192.162.1.1
111# define CONFIG_OVERWRITE_ETHADDR_ONCE
112
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200113/* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
114# ifndef CONFIG_SYS_DISCOVER_PHY
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500115# define FECDUPLEX FULL
116# define FECSPEED _100BASET
117# else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200118# ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
119# define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500120# endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200121# endif /* CONFIG_SYS_DISCOVER_PHY */
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500122#endif
123
124#define CONFIG_HOSTNAME M54455EVB
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200125#ifdef CONFIG_SYS_STMICRO_BOOT
TsiChung Liew9f751552008-07-23 20:38:53 -0500126/* ST Micro serial flash */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200127#define CONFIG_SYS_LOAD_ADDR2 0x40010013
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500128#define CONFIG_EXTRA_ENV_SETTINGS \
129 "netdev=eth0\0" \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200130 "inpclk=" MK_STR(CONFIG_SYS_INPUT_CLKSRC) "\0" \
TsiChung Liew9f751552008-07-23 20:38:53 -0500131 "loadaddr=0x40010000\0" \
132 "sbfhdr=sbfhdr.bin\0" \
133 "uboot=u-boot.bin\0" \
134 "load=tftp ${loadaddr} ${sbfhdr};" \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200135 "tftp " MK_STR(CONFIG_SYS_LOAD_ADDR2) " ${uboot} \0" \
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500136 "upd=run load; run prog\0" \
TsiChung Liew9f751552008-07-23 20:38:53 -0500137 "prog=sf probe 0:1 10000 1;" \
138 "sf erase 0 30000;" \
139 "sf write ${loadaddr} 0 0x30000;" \
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500140 "save\0" \
141 ""
TsiChung Liew9f751552008-07-23 20:38:53 -0500142#else
143/* Atmel and Intel */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144#ifdef CONFIG_SYS_ATMEL_BOOT
145# define CONFIG_SYS_UBOOT_END 0x0403FFFF
146#elif defined(CONFIG_SYS_INTEL_BOOT)
147# define CONFIG_SYS_UBOOT_END 0x3FFFF
TsiChung Liew9f751552008-07-23 20:38:53 -0500148#endif
149#define CONFIG_EXTRA_ENV_SETTINGS \
150 "netdev=eth0\0" \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200151 "inpclk=" MK_STR(CONFIG_SYS_INPUT_CLKSRC) "\0" \
TsiChung Liew9f751552008-07-23 20:38:53 -0500152 "loadaddr=0x40010000\0" \
153 "uboot=u-boot.bin\0" \
154 "load=tftp ${loadaddr} ${uboot}\0" \
155 "upd=run load; run prog\0" \
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200156 "prog=prot off " MK_STR(CONFIG_SYS_FLASH_BASE) \
157 " " MK_STR(CONFIG_SYS_UBOOT_END) ";" \
158 "era " MK_STR(CONFIG_SYS_FLASH_BASE) " " \
159 MK_STR(CONFIG_SYS_UBOOT_END) ";" \
160 "cp.b ${loadaddr} " MK_STR(CONFIG_SYS_FLASH_BASE) \
TsiChung Liew9f751552008-07-23 20:38:53 -0500161 " ${filesize}; save\0" \
162 ""
163#endif
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500164
165/* ATA configuration */
166#define CONFIG_ISO_PARTITION
167#define CONFIG_DOS_PARTITION
168#define CONFIG_IDE_RESET 1
169#define CONFIG_IDE_PREINIT 1
170#define CONFIG_ATAPI
171#undef CONFIG_LBA48
172
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173#define CONFIG_SYS_IDE_MAXBUS 1
174#define CONFIG_SYS_IDE_MAXDEVICE 2
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500175
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200176#define CONFIG_SYS_ATA_BASE_ADDR 0x90000000
177#define CONFIG_SYS_ATA_IDE0_OFFSET 0
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500178
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200179#define CONFIG_SYS_ATA_DATA_OFFSET 0xA0 /* Offset for data I/O */
180#define CONFIG_SYS_ATA_REG_OFFSET 0xA0 /* Offset for normal register accesses */
181#define CONFIG_SYS_ATA_ALT_OFFSET 0xC0 /* Offset for alternate registers */
182#define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500183
184/* Realtime clock */
185#define CONFIG_MCFRTC
186#undef RTC_DEBUG
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200187#define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ)
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500188
189/* Timer */
190#define CONFIG_MCFTMR
191#undef CONFIG_MCFPIT
192
193/* I2c */
194#define CONFIG_FSL_I2C
195#define CONFIG_HARD_I2C /* I2C with hardware support */
196#undef CONFIG_SOFT_I2C /* I2C bit-banged */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200197#define CONFIG_SYS_I2C_SPEED 80000 /* I2C speed and slave address */
198#define CONFIG_SYS_I2C_SLAVE 0x7F
199#define CONFIG_SYS_I2C_OFFSET 0x58000
200#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500201
TsiChung Liewbae61ee2008-03-25 15:41:15 -0500202/* DSPI and Serial Flash */
TsiChung Liewee0a8462009-06-30 14:18:29 +0000203#define CONFIG_CF_SPI
TsiChung Liewbae61ee2008-03-25 15:41:15 -0500204#define CONFIG_CF_DSPI
TsiChung Liewa7323bb2008-07-23 17:53:36 -0500205#define CONFIG_HARD_SPI
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200206#define CONFIG_SYS_SBFHDR_SIZE 0x13
TsiChung Liewa7323bb2008-07-23 17:53:36 -0500207#ifdef CONFIG_CMD_SPI
TsiChung Liew922cd752008-08-06 19:14:08 -0500208# define CONFIG_SPI_FLASH
209# define CONFIG_SPI_FLASH_STMICRO
210
TsiChung Liewee0a8462009-06-30 14:18:29 +0000211# define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \
212 DSPI_CTAR_PCSSCK_1CLK | \
213 DSPI_CTAR_PASC(0) | \
214 DSPI_CTAR_PDT(0) | \
215 DSPI_CTAR_CSSCK(0) | \
216 DSPI_CTAR_ASC(0) | \
217 DSPI_CTAR_DT(1))
TsiChung Liewa7323bb2008-07-23 17:53:36 -0500218#endif
TsiChung Liewbae61ee2008-03-25 15:41:15 -0500219
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500220/* PCI */
TsiChungLiewe8ee8f32007-10-25 17:16:22 -0500221#ifdef CONFIG_CMD_PCI
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500222#define CONFIG_PCI 1
TsiChungLiew2e72ad02008-01-14 17:11:47 -0600223#define CONFIG_PCI_PNP 1
TsiChung Liewf33fca22008-03-30 01:19:06 -0500224#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
TsiChungLiew2e72ad02008-01-14 17:11:47 -0600225
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200226#define CONFIG_SYS_PCI_CACHE_LINE_SIZE 4
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500227
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200228#define CONFIG_SYS_PCI_MEM_BUS 0xA0000000
229#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BUS
230#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500231
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200232#define CONFIG_SYS_PCI_IO_BUS 0xB1000000
233#define CONFIG_SYS_PCI_IO_PHYS CONFIG_SYS_PCI_IO_BUS
234#define CONFIG_SYS_PCI_IO_SIZE 0x01000000
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500235
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200236#define CONFIG_SYS_PCI_CFG_BUS 0xB0000000
237#define CONFIG_SYS_PCI_CFG_PHYS CONFIG_SYS_PCI_CFG_BUS
238#define CONFIG_SYS_PCI_CFG_SIZE 0x01000000
TsiChungLiewe8ee8f32007-10-25 17:16:22 -0500239#endif
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500240
241/* FPGA - Spartan 2 */
242/* experiment
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200243#define CONFIG_FPGA CONFIG_SYS_SPARTAN3
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500244#define CONFIG_FPGA_COUNT 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200245#define CONFIG_SYS_FPGA_PROG_FEEDBACK
246#define CONFIG_SYS_FPGA_CHECK_CTRLC
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500247*/
248
249/* Input, PCI, Flexbus, and VCO */
250#define CONFIG_EXTRA_CLOCK
251
TsiChung Liew9f751552008-07-23 20:38:53 -0500252#define CONFIG_PRAM 2048 /* 2048 KB */
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500253
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200254#define CONFIG_SYS_PROMPT "-> "
255#define CONFIG_SYS_LONGHELP /* undef to save memory */
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500256
257#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200258#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500259#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200260#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500261#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200262#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
263#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
264#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500265
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200266#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000)
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500267
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200268#define CONFIG_SYS_HZ 1000
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500269
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200270#define CONFIG_SYS_MBAR 0xFC000000
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500271
272/*
273 * Low Level Configuration Settings
274 * (address mappings, register initial values, etc.)
275 * You should know what you are doing if you make changes here.
276 */
277
278/*-----------------------------------------------------------------------
279 * Definitions for initial stack pointer and data area (in DPRAM)
280 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200281#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600282#define CONFIG_SYS_INIT_RAM_END 0x8000 /* End of used area in internal SRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200283#define CONFIG_SYS_INIT_RAM_CTRL 0x221
284#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
285#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) - 32)
286#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
287#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - 32)
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500288
289/*-----------------------------------------------------------------------
290 * Start addresses for the final memory configuration
291 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200292 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500293 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200294#define CONFIG_SYS_SDRAM_BASE 0x40000000
295#define CONFIG_SYS_SDRAM_BASE1 0x48000000
296#define CONFIG_SYS_SDRAM_SIZE 256 /* SDRAM size in MB */
297#define CONFIG_SYS_SDRAM_CFG1 0x65311610
298#define CONFIG_SYS_SDRAM_CFG2 0x59670000
299#define CONFIG_SYS_SDRAM_CTRL 0xEA0B2000
300#define CONFIG_SYS_SDRAM_EMOD 0x40010000
301#define CONFIG_SYS_SDRAM_MODE 0x00010033
302#define CONFIG_SYS_SDRAM_DRV_STRENGTH 0xAA
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500303
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200304#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400
305#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500306
TsiChung Liew9f751552008-07-23 20:38:53 -0500307#ifdef CONFIG_CF_SBF
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200308# define CONFIG_SYS_MONITOR_BASE (TEXT_BASE + 0x400)
TsiChung Liew9f751552008-07-23 20:38:53 -0500309#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200310# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
TsiChung Liew9f751552008-07-23 20:38:53 -0500311#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200312#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024
313#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
314#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500315
316/*
317 * For booting Linux, the board info and command line data
318 * have to be in the first 8 MB of memory, since this is
319 * the maximum mapped by the Linux kernel during initialization ??
320 */
321/* Initial Memory map for Linux */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200322#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500323
TsiChung Liew9f751552008-07-23 20:38:53 -0500324/*
325 * Configuration for environment
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500326 * Environment is embedded in u-boot in the second sector of the flash
327 */
TsiChung Liew9f751552008-07-23 20:38:53 -0500328#ifdef CONFIG_CF_SBF
Jean-Christophe PLAGNIOL-VILLARD0b5099a2008-09-10 22:48:00 +0200329# define CONFIG_ENV_IS_IN_SPI_FLASH
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200330# define CONFIG_ENV_SPI_CS 1
TsiChung Liew9f751552008-07-23 20:38:53 -0500331#else
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200332# define CONFIG_ENV_IS_IN_FLASH 1
TsiChung Liew9f751552008-07-23 20:38:53 -0500333#endif
334#undef CONFIG_ENV_OVERWRITE
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500335
336/*-----------------------------------------------------------------------
337 * FLASH organization
338 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200339#ifdef CONFIG_SYS_STMICRO_BOOT
TsiChung Liewee0a8462009-06-30 14:18:29 +0000340# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
341# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS1_BASE
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200342# define CONFIG_ENV_OFFSET 0x30000
343# define CONFIG_ENV_SIZE 0x2000
344# define CONFIG_ENV_SECT_SIZE 0x10000
TsiChung Liew9f751552008-07-23 20:38:53 -0500345#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200346#ifdef CONFIG_SYS_ATMEL_BOOT
347# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
348# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE
349# define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_CS1_BASE
350# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x4000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200351# define CONFIG_ENV_SECT_SIZE 0x2000
TsiChung Liew9f751552008-07-23 20:38:53 -0500352#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200353#ifdef CONFIG_SYS_INTEL_BOOT
354# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
355# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE
356# define CONFIG_SYS_FLASH1_BASE CONFIG_SYS_CS1_BASE
357# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200358# define CONFIG_ENV_SIZE 0x2000
359# define CONFIG_ENV_SECT_SIZE 0x20000
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500360#endif
361
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200362#define CONFIG_SYS_FLASH_CFI
363#ifdef CONFIG_SYS_FLASH_CFI
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500364
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200365# define CONFIG_FLASH_CFI_DRIVER 1
TsiChung Liewbbf6bbf2009-06-11 12:50:05 +0000366# define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200367# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */
368# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
369# define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
370# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */
371# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
372# define CONFIG_SYS_FLASH_CHECKSUM
373# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE, CONFIG_SYS_CS1_BASE }
TsiChung Liewb2d022d2008-07-23 17:37:10 -0500374# define CONFIG_FLASH_CFI_LEGACY
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500375
TsiChung Liewb2d022d2008-07-23 17:37:10 -0500376#ifdef CONFIG_FLASH_CFI_LEGACY
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200377# define CONFIG_SYS_ATMEL_REGION 4
378# define CONFIG_SYS_ATMEL_TOTALSECT 11
379# define CONFIG_SYS_ATMEL_SECT {1, 2, 1, 7}
380# define CONFIG_SYS_ATMEL_SECTSZ {0x4000, 0x2000, 0x8000, 0x10000}
TsiChung Liewb2d022d2008-07-23 17:37:10 -0500381#endif
TsiChung Liewbae61ee2008-03-25 15:41:15 -0500382#endif
383
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500384/*
385 * This is setting for JFFS2 support in u-boot.
386 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support.
387 */
TsiChung Liew9f751552008-07-23 20:38:53 -0500388#ifdef CONFIG_CMD_JFFS2
389#ifdef CF_STMICRO_BOOT
390# define CONFIG_JFFS2_DEV "nor1"
391# define CONFIG_JFFS2_PART_SIZE 0x01000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200392# define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH2_BASE + 0x500000)
TsiChung Liew9f751552008-07-23 20:38:53 -0500393#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200394#ifdef CONFIG_SYS_ATMEL_BOOT
TsiChungLiewe8ee8f32007-10-25 17:16:22 -0500395# define CONFIG_JFFS2_DEV "nor1"
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500396# define CONFIG_JFFS2_PART_SIZE 0x01000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200397# define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH1_BASE + 0x500000)
TsiChung Liew9f751552008-07-23 20:38:53 -0500398#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200399#ifdef CONFIG_SYS_INTEL_BOOT
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500400# define CONFIG_JFFS2_DEV "nor0"
401# define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x500000)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200402# define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x500000)
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500403#endif
TsiChung Liew9f751552008-07-23 20:38:53 -0500404#endif
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500405
406/*-----------------------------------------------------------------------
407 * Cache Configuration
408 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200409#define CONFIG_SYS_CACHELINE_SIZE 16
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500410
TsiChung Liewdd9f0542010-03-11 22:12:53 -0600411#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
412 CONFIG_SYS_INIT_RAM_END - 8)
413#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \
414 CONFIG_SYS_INIT_RAM_END - 4)
415#define CONFIG_SYS_ICACHE_INV (CF_CACR_BCINVA + CF_CACR_ICINVA)
416#define CONFIG_SYS_DCACHE_INV (CF_CACR_DCINVA)
417#define CONFIG_SYS_CACHE_ACR2 (CONFIG_SYS_SDRAM_BASE | \
418 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
419 CF_ACR_EN | CF_ACR_SM_ALL)
420#define CONFIG_SYS_CACHE_ICACR (CF_CACR_BEC | CF_CACR_IEC | \
421 CF_CACR_ICINVA | CF_CACR_EUSP)
422#define CONFIG_SYS_CACHE_DCACR ((CONFIG_SYS_CACHE_ICACR | \
423 CF_CACR_DEC | CF_CACR_DDCM_P | \
424 CF_CACR_DCINVA) & ~CF_CACR_ICINVA)
425
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500426/*-----------------------------------------------------------------------
427 * Memory bank definitions
428 */
429/*
430 * CS0 - NOR Flash 1, 2, 4, or 8MB
431 * CS1 - CompactFlash and registers
432 * CS2 - CPLD
433 * CS3 - FPGA
434 * CS4 - Available
435 * CS5 - Available
436 */
437
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200438#if defined(CONFIG_SYS_ATMEL_BOOT) || defined(CONFIG_SYS_STMICRO_BOOT)
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500439 /* Atmel Flash */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200440#define CONFIG_SYS_CS0_BASE 0x04000000
441#define CONFIG_SYS_CS0_MASK 0x00070001
442#define CONFIG_SYS_CS0_CTRL 0x00001140
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500443/* Intel Flash */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200444#define CONFIG_SYS_CS1_BASE 0x00000000
445#define CONFIG_SYS_CS1_MASK 0x01FF0001
446#define CONFIG_SYS_CS1_CTRL 0x00000D60
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500447
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200448#define CONFIG_SYS_ATMEL_BASE CONFIG_SYS_CS0_BASE
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500449#else
450/* Intel Flash */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200451#define CONFIG_SYS_CS0_BASE 0x00000000
452#define CONFIG_SYS_CS0_MASK 0x01FF0001
453#define CONFIG_SYS_CS0_CTRL 0x00000D60
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500454 /* Atmel Flash */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200455#define CONFIG_SYS_CS1_BASE 0x04000000
456#define CONFIG_SYS_CS1_MASK 0x00070001
457#define CONFIG_SYS_CS1_CTRL 0x00001140
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500458
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200459#define CONFIG_SYS_ATMEL_BASE CONFIG_SYS_CS1_BASE
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500460#endif
461
462/* CPLD */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200463#define CONFIG_SYS_CS2_BASE 0x08000000
464#define CONFIG_SYS_CS2_MASK 0x00070001
465#define CONFIG_SYS_CS2_CTRL 0x003f1140
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500466
467/* FPGA */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200468#define CONFIG_SYS_CS3_BASE 0x09000000
469#define CONFIG_SYS_CS3_MASK 0x00070001
470#define CONFIG_SYS_CS3_CTRL 0x00000020
TsiChungLiew8ae158c2007-08-16 15:05:11 -0500471
TsiChungLiewe8ee8f32007-10-25 17:16:22 -0500472#endif /* _M54455EVB_H */