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Hou Zhiqiangb89e3d92019-04-24 22:33:02 +08001/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright 2019 NXP
4 *
5 * PCIe DM U-Boot driver for Freescale PowerPC SoCs
6 * Author: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
7 */
8
9#ifndef _PCIE_FSL_H_
10#define _PCIE_FSL_H_
11
Hou Zhiqiangd18d06a2019-08-27 10:13:51 +000012/* GPEX CSR */
13#define CSR_CLASSCODE 0x474
14
Hou Zhiqiangb89e3d92019-04-24 22:33:02 +080015#ifdef CONFIG_SYS_FSL_PCI_VER_3_X
16#define FSL_PCIE_CAP_ID 0x70
17#else
18#define FSL_PCIE_CAP_ID 0x4c
19#endif
20/* PCIe Device Control Register */
21#define PCI_DCR (FSL_PCIE_CAP_ID + 0x08)
22/* PCIe Device Status Register */
23#define PCI_DSR (FSL_PCIE_CAP_ID + 0x0a)
24/* PCIe Link Control Register */
25#define PCI_LCR (FSL_PCIE_CAP_ID + 0x10)
26/* PCIe Link Status Register */
27#define PCI_LSR (FSL_PCIE_CAP_ID + 0x12)
28
Hou Zhiqiang0205beb2020-10-15 14:54:34 +080029#define DBI_RO_WR_EN 0x8bc
30
Tom Riniecc8d422022-11-16 13:10:33 -050031#ifndef CFG_SYS_PCI_MEMORY_BUS
32#define CFG_SYS_PCI_MEMORY_BUS 0
Hou Zhiqiangb89e3d92019-04-24 22:33:02 +080033#endif
34
Tom Riniecc8d422022-11-16 13:10:33 -050035#ifndef CFG_SYS_PCI_MEMORY_PHYS
36#define CFG_SYS_PCI_MEMORY_PHYS 0
Hou Zhiqiangb89e3d92019-04-24 22:33:02 +080037#endif
38
Tom Riniecc8d422022-11-16 13:10:33 -050039#if defined(CONFIG_SYS_PCI_64BIT) && !defined(CFG_SYS_PCI64_MEMORY_BUS)
40#define CFG_SYS_PCI64_MEMORY_BUS (64ull * 1024 * 1024 * 1024)
Hou Zhiqiangb89e3d92019-04-24 22:33:02 +080041#endif
42
43#define PEX_CSR0_LTSSM_MASK 0xFC
44#define PEX_CSR0_LTSSM_SHIFT 2
45#define LTSSM_L0_REV3 0x11
46#define LTSSM_L0 0x16
47
Hou Zhiqiangfbcb2ff2019-08-27 10:13:54 +000048struct fsl_pcie_data {
49 u32 block_offset; /* Offset from CCSR of 1st controller */
50 u32 block_offset_mask; /* Mask out the CCSR base */
51 u32 stride; /* Offset stride between controllers */
52};
53
Hou Zhiqiangb89e3d92019-04-24 22:33:02 +080054struct fsl_pcie {
55 int idx;
56 struct udevice *bus;
57 void __iomem *regs;
58 u32 law_trgt_if; /* LAW target ID */
59 u32 block_rev; /* IP block revision */
60 bool mode; /* RC&EP mode flag */
61 bool enabled; /* Enable status */
62 struct list_head list;
Hou Zhiqiangfbcb2ff2019-08-27 10:13:54 +000063 struct fsl_pcie_data *info;
Hou Zhiqiangb89e3d92019-04-24 22:33:02 +080064};
65
66extern struct list_head fsl_pcie_list;
67
68#endif /* _PCIE_FSL_H_ */