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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / 884ad05d34c49ac6c8e21346a63a627c6c9d4c52 / . / arch / arm / dts / zynqmp-zc1751-xm018-dc4.dts
blob: 799b87a04c13ed11d6337eee34f8de1e36692ab0 [file] [log] [blame]
Michal Simek08ac3862016-05-26 08:06:38 +0200[diff] [blame]1/*
2 * dts file for Xilinx ZynqMP zc1751-xm018-dc4
3 *
4 * (C) Copyright 2015 - 2016, Xilinx, Inc.
5 *
6 * Michal Simek <michal.simek@xilinx.com>
7 *
Michal Simek5fe03262017-02-09 14:38:36 +0100[diff] [blame]8 * SPDX-License-Identifier: GPL-2.0+
Michal Simek08ac3862016-05-26 08:06:38 +0200[diff] [blame]9 */
10
11/dts-v1/;
12
13#include "zynqmp.dtsi"
14#include "zynqmp-clk.dtsi"
15
16/ {
17 model = "ZynqMP zc1751-xm018-dc4";
18 compatible = "xlnx,zynqmp-zc1751", "xlnx,zynqmp";
19
20 aliases {
21 can0 = &can0;
22 can1 = &can1;
23 ethernet0 = &gem0;
24 ethernet1 = &gem1;
25 ethernet2 = &gem2;
26 ethernet3 = &gem3;
27 gpio0 = &gpio;
28 i2c0 = &i2c0;
29 i2c1 = &i2c1;
30 rtc0 = &rtc;
31 serial0 = &uart0;
32 serial1 = &uart1;
33 spi0 = &qspi;
34 };
35
36 chosen {
37 bootargs = "earlycon";
38 stdout-path = "serial0:115200n8";
39 };
40
Michal Simekc926e6f2016-11-11 13:21:04 +0100[diff] [blame]41 memory@0 {
Michal Simek08ac3862016-05-26 08:06:38 +0200[diff] [blame]42 device_type = "memory";
43 reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
44 };
45};
46
47&can0 {
48 status = "okay";
49};
50
51&can1 {
52 status = "okay";
53};
54
55/* fpd_dma clk 667MHz, lpd_dma 500MHz */
56&fpd_dma_chan1 {
57 status = "okay";
58 xlnx,include-sg; /* for testing purpose */
59 xlnx,overfetch; /* for testing purpose */
60 xlnx,ratectrl = <0>; /* for testing purpose */
61 xlnx,src-issue = <31>;
62};
63
64&fpd_dma_chan2 {
65 status = "okay";
66 xlnx,ratectrl = <100>; /* for testing purpose */
67 xlnx,src-issue = <4>; /* for testing purpose */
68};
69
70&fpd_dma_chan3 {
71 status = "okay";
72};
73
74&fpd_dma_chan4 {
75 status = "okay";
76 xlnx,include-sg; /* for testing purpose */
77};
78
79&fpd_dma_chan5 {
80 status = "okay";
81};
82
83&fpd_dma_chan6 {
84 status = "okay";
85 xlnx,include-sg; /* for testing purpose */
86};
87
88&fpd_dma_chan7 {
89 status = "okay";
90};
91
92&fpd_dma_chan8 {
93 status = "okay";
94 xlnx,include-sg; /* for testing purpose */
95};
96
97&lpd_dma_chan1 {
98 status = "okay";
99};
100
101&lpd_dma_chan2 {
102 status = "okay";
103};
104
105&lpd_dma_chan3 {
106 status = "okay";
107};
108
109&lpd_dma_chan4 {
110 status = "okay";
111};
112
113&lpd_dma_chan5 {
114 status = "okay";
115};
116
117&lpd_dma_chan6 {
118 status = "okay";
119};
120
121&lpd_dma_chan7 {
122 status = "okay";
123};
124
125&lpd_dma_chan8 {
126 status = "okay";
127};
128
129&xlnx_dp {
130 status = "okay";
131};
132
133&xlnx_dpdma {
134 status = "okay";
135};
136
137&gem0 {
138 status = "okay";
Michal Simek08ac3862016-05-26 08:06:38 +0200[diff] [blame]139 phy-mode = "rgmii-id";
140 phy-handle = <&ethernet_phy0>;
141 ethernet_phy0: ethernet-phy@0 { /* Marvell 88e1512 */
142 reg = <0>;
143 };
144 ethernet_phy7: ethernet-phy@7 { /* Vitesse VSC8211 */
145 reg = <7>;
146 };
147 ethernet_phy3: ethernet-phy@3 { /* Realtek RTL8211DN */
148 reg = <3>;
149 };
150 ethernet_phy8: ethernet-phy@8 { /* Vitesse VSC8211 */
151 reg = <8>;
152 };
153};
154
155&gem1 {
156 status = "okay";
Michal Simek08ac3862016-05-26 08:06:38 +0200[diff] [blame]157 phy-mode = "rgmii-id";
158 phy-handle = <&ethernet_phy7>;
159};
160
161&gem2 {
162 status = "okay";
Michal Simek08ac3862016-05-26 08:06:38 +0200[diff] [blame]163 phy-mode = "rgmii-id";
164 phy-handle = <&ethernet_phy3>;
165};
166
167&gem3 {
168 status = "okay";
Michal Simek08ac3862016-05-26 08:06:38 +0200[diff] [blame]169 phy-mode = "rgmii-id";
170 phy-handle = <&ethernet_phy8>;
171};
172
173&gpio {
174 status = "okay";
175};
176
177&gpu {
178 status = "okay";
179};
180
181&i2c0 {
182 clock-frequency = <400000>;
183 status = "okay";
184};
185
186&i2c1 {
187 clock-frequency = <400000>;
188 status = "okay";
189};
190
191&rtc {
192 status = "okay";
193};
194
195&uart0 {
196 status = "okay";
197};
198
199&uart1 {
200 status = "okay";
201};
202
203&watchdog0 {
204 status = "okay";
205};