| Xu Ziyuan | 744368d | 2016-07-05 18:06:30 +0800 | [diff] [blame] | 1 | CONFIG_ARM=y |
| 2 | CONFIG_ARCH_ROCKCHIP=y |
| 3 | CONFIG_SYS_MALLOC_F_LEN=0x2000 |
| 4 | CONFIG_ROCKCHIP_RK3288=y |
| Philipp Tomsich | ee14d29 | 2017-06-29 11:21:15 +0200 | [diff] [blame] | 5 | CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y |
| Xu Ziyuan | 744368d | 2016-07-05 18:06:30 +0800 | [diff] [blame] | 6 | CONFIG_TARGET_EVB_RK3288=y |
| 7 | CONFIG_SPL_STACK_R_ADDR=0x80000 |
| 8 | CONFIG_DEFAULT_DEVICE_TREE="rk3288-evb" |
| Tom Rini | fb82fe3 | 2017-06-19 09:47:40 -0400 | [diff] [blame] | 9 | CONFIG_DEBUG_UART=y |
| Simon Glass | 2be2965 | 2017-07-23 21:19:39 -0600 | [diff] [blame] | 10 | CONFIG_ENV_IS_IN_MMC=y |
| Simon Glass | 98af879 | 2016-10-17 20:12:35 -0600 | [diff] [blame] | 11 | CONFIG_SILENT_CONSOLE=y |
| Simon Glass | ef26d60 | 2016-10-17 20:12:37 -0600 | [diff] [blame] | 12 | # CONFIG_DISPLAY_CPUINFO is not set |
| Xu Ziyuan | 744368d | 2016-07-05 18:06:30 +0800 | [diff] [blame] | 13 | CONFIG_SPL_STACK_R=y |
| 14 | CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x2000 |
| Xu Ziyuan | 744368d | 2016-07-05 18:06:30 +0800 | [diff] [blame] | 15 | # CONFIG_CMD_IMLS is not set |
| Tom Rini | 8866312 | 2017-08-14 19:58:53 -0400 | [diff] [blame^] | 16 | CONFIG_CMD_GPIO=y |
| Patrick Delaunay | b331cd6 | 2017-01-27 11:00:42 +0100 | [diff] [blame] | 17 | CONFIG_CMD_GPT=y |
| Tom Rini | 8866312 | 2017-08-14 19:58:53 -0400 | [diff] [blame^] | 18 | CONFIG_CMD_I2C=y |
| Xu Ziyuan | 744368d | 2016-07-05 18:06:30 +0800 | [diff] [blame] | 19 | CONFIG_CMD_MMC=y |
| 20 | CONFIG_CMD_SF=y |
| 21 | CONFIG_CMD_SPI=y |
| Xu Ziyuan | 744368d | 2016-07-05 18:06:30 +0800 | [diff] [blame] | 22 | # CONFIG_CMD_SETEXPR is not set |
| Xu Ziyuan | 744368d | 2016-07-05 18:06:30 +0800 | [diff] [blame] | 23 | CONFIG_CMD_CACHE=y |
| 24 | CONFIG_CMD_TIME=y |
| 25 | CONFIG_CMD_PMIC=y |
| 26 | CONFIG_CMD_REGULATOR=y |
| Patrick Delaunay | b0cf733 | 2017-01-27 11:00:37 +0100 | [diff] [blame] | 27 | # CONFIG_SPL_DOS_PARTITION is not set |
| Patrick Delaunay | 1acc008 | 2017-01-27 11:00:38 +0100 | [diff] [blame] | 28 | # CONFIG_SPL_ISO_PARTITION is not set |
| Patrick Delaunay | bd42a94 | 2017-01-27 11:00:41 +0100 | [diff] [blame] | 29 | # CONFIG_SPL_EFI_PARTITION is not set |
| Patrick Delaunay | b331cd6 | 2017-01-27 11:00:42 +0100 | [diff] [blame] | 30 | CONFIG_SPL_PARTITION_UUIDS=y |
| Xu Ziyuan | 744368d | 2016-07-05 18:06:30 +0800 | [diff] [blame] | 31 | CONFIG_SPL_OF_CONTROL=y |
| 32 | CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" |
| 33 | CONFIG_REGMAP=y |
| 34 | CONFIG_SPL_REGMAP=y |
| 35 | CONFIG_SYSCON=y |
| 36 | CONFIG_SPL_SYSCON=y |
| 37 | CONFIG_CLK=y |
| 38 | CONFIG_SPL_CLK=y |
| 39 | CONFIG_ROCKCHIP_GPIO=y |
| 40 | CONFIG_SYS_I2C_ROCKCHIP=y |
| 41 | CONFIG_LED=y |
| 42 | CONFIG_LED_GPIO=y |
| Masahiro Yamada | 55ed3b4 | 2017-01-10 13:32:04 +0900 | [diff] [blame] | 43 | CONFIG_MMC_DW=y |
| Masahiro Yamada | fed4408 | 2017-01-10 13:32:03 +0900 | [diff] [blame] | 44 | CONFIG_MMC_DW_ROCKCHIP=y |
| Jacob Chen | 5c0206c | 2017-02-23 14:20:17 +0800 | [diff] [blame] | 45 | CONFIG_DM_ETH=y |
| Jacob Chen | 5c0206c | 2017-02-23 14:20:17 +0800 | [diff] [blame] | 46 | CONFIG_ETH_DESIGNWARE=y |
| 47 | CONFIG_GMAC_ROCKCHIP=y |
| Xu Ziyuan | 744368d | 2016-07-05 18:06:30 +0800 | [diff] [blame] | 48 | CONFIG_PINCTRL=y |
| Xu Ziyuan | 744368d | 2016-07-05 18:06:30 +0800 | [diff] [blame] | 49 | CONFIG_SPL_PINCTRL=y |
| 50 | # CONFIG_SPL_PINCTRL_FULL is not set |
| Philipp Tomsich | 51c7f34 | 2017-04-19 16:46:37 +0200 | [diff] [blame] | 51 | CONFIG_PINCTRL_ROCKCHIP_RK3288=y |
| Xu Ziyuan | 744368d | 2016-07-05 18:06:30 +0800 | [diff] [blame] | 52 | CONFIG_DM_PMIC=y |
| 53 | CONFIG_PMIC_ACT8846=y |
| Xu Ziyuan | 744368d | 2016-07-05 18:06:30 +0800 | [diff] [blame] | 54 | CONFIG_REGULATOR_ACT8846=y |
| 55 | CONFIG_DM_REGULATOR_FIXED=y |
| Xu Ziyuan | 744368d | 2016-07-05 18:06:30 +0800 | [diff] [blame] | 56 | CONFIG_PWM_ROCKCHIP=y |
| 57 | CONFIG_RAM=y |
| 58 | CONFIG_SPL_RAM=y |
| Xu Ziyuan | 744368d | 2016-07-05 18:06:30 +0800 | [diff] [blame] | 59 | CONFIG_DEBUG_UART_BASE=0xff690000 |
| 60 | CONFIG_DEBUG_UART_CLOCK=24000000 |
| 61 | CONFIG_DEBUG_UART_SHIFT=2 |
| 62 | CONFIG_SYS_NS16550=y |
| Tom Rini | aca5cd2 | 2016-09-08 16:11:59 -0400 | [diff] [blame] | 63 | CONFIG_SYSRESET=y |
| eric.gao@rock-chips.com | b713bc8 | 2017-06-21 11:22:03 +0800 | [diff] [blame] | 64 | CONFIG_DM_VIDEO=y |
| 65 | CONFIG_DISPLAY=y |
| 66 | CONFIG_VIDEO_ROCKCHIP=y |
| 67 | CONFIG_VIDEO_ROCKCHIP_MAX_YRES=1200 |
| 68 | CONFIG_DISPLAY_ROCKCHIP_MIPI=y |
| Xu Ziyuan | 744368d | 2016-07-05 18:06:30 +0800 | [diff] [blame] | 69 | CONFIG_USE_TINY_PRINTF=y |
| 70 | CONFIG_CMD_DHRYSTONE=y |
| 71 | CONFIG_ERRNO_STR=y |