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wdenkba56f622004-02-06 23:19:44 +00001/*----------------------------------------------------------------------------+
2|
3| This source code has been made available to you by IBM on an AS-IS
4| basis. Anyone receiving this source is licensed under IBM
5| copyrights to use it in any way he or she deems fit, including
6| copying it, modifying it, compiling it, and redistributing it either
7| with or without modifications. No license under IBM patents or
8| patent applications is to be implied by the copyright license.
9|
10| Any user of this software should understand that IBM cannot provide
11| technical support for this software and will not be responsible for
12| any consequences resulting from the use of this software.
13|
14| Any person who transfers this source code or any derivative work
15| must include the IBM copyright notice, this paragraph, and the
16| preceding two paragraphs in the transferred software.
17|
18| COPYRIGHT I B M CORPORATION 1999
19| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M
20+----------------------------------------------------------------------------*/
21/*----------------------------------------------------------------------------+
22|
23| File Name: enetemac.h
24|
25| Function: Header file for the EMAC3 macro on the 405GP.
26|
27| Author: Mark Wisner
28|
29| Change Activity-
30|
31| Date Description of Change BY
32| --------- --------------------- ---
33| 29-Apr-99 Created MKW
34|
35+----------------------------------------------------------------------------*/
36/*----------------------------------------------------------------------------+
37| 19-Nov-03 Travis Sawyer, Sandburst Corporation, tsawyer@sandburst.com
38| ported to handle 440GP and 440GX multiple EMACs
39+----------------------------------------------------------------------------*/
40
Stefan Roesed6c61aa2005-08-16 18:18:00 +020041#ifndef _PPC4XX_ENET_H_
42#define _PPC4XX_ENET_H_
wdenkba56f622004-02-06 23:19:44 +000043
wdenkba56f622004-02-06 23:19:44 +000044#include <net.h>
45#include "405_mal.h"
46
47
48/*-----------------------------------------------------------------------------+
49| General enternet defines. 802 frames are not supported.
50+-----------------------------------------------------------------------------*/
51#define ENET_ADDR_LENGTH 6
52#define ENET_ARPTYPE 0x806
53#define ARP_REQUEST 1
54#define ARP_REPLY 2
55#define ENET_IPTYPE 0x800
56#define ARP_CACHE_SIZE 5
57
58#define NUM_TX_BUFF 1
59#define NUM_RX_BUFF PKTBUFSRX
60
61struct enet_frame {
62 unsigned char dest_addr[ENET_ADDR_LENGTH];
63 unsigned char source_addr[ENET_ADDR_LENGTH];
64 unsigned short type;
65 unsigned char enet_data[1];
66};
67
68struct arp_entry {
69 unsigned long inet_address;
70 unsigned char mac_address[ENET_ADDR_LENGTH];
71 unsigned long valid;
72 unsigned long sec;
73 unsigned long nsec;
74};
75
76
77/* Statistic Areas */
78#define MAX_ERR_LOG 10
79
80typedef struct emac_stats_st{ /* Statistic Block */
81 int data_len_err;
82 int rx_frames;
83 int rx;
84 int rx_prot_err;
85 int int_err;
Stefan Roesed6c61aa2005-08-16 18:18:00 +020086 int pkts_tx;
87 int pkts_rx;
88 int pkts_handled;
wdenkba56f622004-02-06 23:19:44 +000089 short tx_err_log[MAX_ERR_LOG];
90 short rx_err_log[MAX_ERR_LOG];
91} EMAC_STATS_ST, *EMAC_STATS_PST;
92
Stefan Roesed6c61aa2005-08-16 18:18:00 +020093/* Structure containing variables used by the shared code (4xx_enet.c) */
94typedef struct emac_4xx_hw_st {
wdenkba56f622004-02-06 23:19:44 +000095 uint32_t hw_addr; /* EMAC offset */
96 uint32_t tah_addr; /* TAH offset */
97 uint32_t phy_id;
98 uint32_t phy_addr;
99 uint32_t original_fc;
100 uint32_t txcw;
101 uint32_t autoneg_failed;
102 uint32_t emac_ier;
103 volatile mal_desc_t *tx;
104 volatile mal_desc_t *rx;
Stefan Roeseff768cb2007-10-31 18:01:24 +0100105 u32 tx_phys;
106 u32 rx_phys;
wdenkba56f622004-02-06 23:19:44 +0000107 bd_t *bis; /* for eth_init upon mal error */
108 mal_desc_t *alloc_tx_buf;
109 mal_desc_t *alloc_rx_buf;
110 char *txbuf_ptr;
111 uint16_t devnum;
112 int get_link_status;
113 int tbi_compatibility_en;
114 int tbi_compatibility_on;
115 int fc_send_xon;
116 int report_tx_early;
117 int first_init;
118 int tx_err_index;
119 int rx_err_index;
120 int rx_slot; /* MAL Receive Slot */
121 int rx_i_index; /* Receive Interrupt Queue Index */
122 int rx_u_index; /* Receive User Queue Index */
123 int tx_slot; /* MAL Transmit Slot */
124 int tx_i_index; /* Transmit Interrupt Queue Index */
125 int tx_u_index; /* Transmit User Queue Index */
126 int rx_ready[NUM_RX_BUFF]; /* Receive Ready Queue */
127 int tx_run[NUM_TX_BUFF]; /* Transmit Running Queue */
128 int is_receiving; /* sync with eth interrupt */
129 int print_speed; /* print speed message upon start */
130 EMAC_STATS_ST stats;
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200131} EMAC_4XX_HW_ST, *EMAC_4XX_HW_PST;
wdenkba56f622004-02-06 23:19:44 +0000132
133
Stefan Roese6f2eb3f2008-03-11 15:11:18 +0100134#if defined(CONFIG_440GX) || defined(CONFIG_460GT)
Stefan Roesee01bd212007-03-21 13:38:59 +0100135#define EMAC_NUM_DEV 4
Stefan Roese6e7fb6e2005-11-29 18:18:21 +0100136#elif (defined(CONFIG_440) || defined(CONFIG_405EP)) && \
137 defined(CONFIG_NET_MULTI) && \
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200138 !defined(CONFIG_440SP) && !defined(CONFIG_440SPE)
Stefan Roesee01bd212007-03-21 13:38:59 +0100139#define EMAC_NUM_DEV 2
wdenkba56f622004-02-06 23:19:44 +0000140#else
Stefan Roesee01bd212007-03-21 13:38:59 +0100141#define EMAC_NUM_DEV 1
wdenkba56f622004-02-06 23:19:44 +0000142#endif
143
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200144#ifdef CONFIG_IBM_EMAC4_V4 /* EMAC4 V4 changed bit setting */
145#define EMAC_STACR_OC_MASK (0x00008000)
146#else
147#define EMAC_STACR_OC_MASK (0x00000000)
148#endif
149
Stefan Roese887e2ec2006-09-07 11:51:23 +0200150#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
Stefan Roesedbbd1252007-10-05 17:10:59 +0200151 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
152 defined(CONFIG_405EX)
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200153#define SDR0_PFC1_EM_1000 (0x00200000)
154#endif
wdenkba56f622004-02-06 23:19:44 +0000155
Stefan Roesedbbd1252007-10-05 17:10:59 +0200156/* ZMII Bridge Register addresses */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200157#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
Stefan Roese6f2eb3f2008-03-11 15:11:18 +0100158 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
159 defined(CONFIG_460EX) || defined(CONFIG_460GT)
Stefan Roesee01bd212007-03-21 13:38:59 +0100160#define ZMII_BASE (CFG_PERIPHERAL_BASE + 0x0D00)
Stefan Roesec157d8e2005-08-01 16:41:48 +0200161#else
Stefan Roesee01bd212007-03-21 13:38:59 +0100162#define ZMII_BASE (CFG_PERIPHERAL_BASE + 0x0780)
Stefan Roesec157d8e2005-08-01 16:41:48 +0200163#endif
Stefan Roesee01bd212007-03-21 13:38:59 +0100164#define ZMII_FER (ZMII_BASE)
165#define ZMII_SSR (ZMII_BASE + 4)
166#define ZMII_SMIISR (ZMII_BASE + 8)
wdenkba56f622004-02-06 23:19:44 +0000167
wdenkba56f622004-02-06 23:19:44 +0000168/* ZMII FER Register Bit Definitions */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200169#define ZMII_FER_DIS (0x0)
wdenkba56f622004-02-06 23:19:44 +0000170#define ZMII_FER_MDI (0x8)
171#define ZMII_FER_SMII (0x4)
172#define ZMII_FER_RMII (0x2)
173#define ZMII_FER_MII (0x1)
174
175#define ZMII_FER_RSVD11 (0x00200000)
176#define ZMII_FER_RSVD10 (0x00100000)
177#define ZMII_FER_RSVD14_31 (0x0003FFFF)
178
179#define ZMII_FER_V(__x) (((3 - __x) * 4) + 16)
180
181
182/* ZMII Speed Selection Register Bit Definitions */
183#define ZMII_SSR_SCI (0x4)
184#define ZMII_SSR_FSS (0x2)
185#define ZMII_SSR_SP (0x1)
186#define ZMII_SSR_RSVD16_31 (0x0000FFFF)
187
188#define ZMII_SSR_V(__x) (((3 - __x) * 4) + 16)
189
190
191/* ZMII SMII Status Register Bit Definitions */
192#define ZMII_SMIISR_E1 (0x80)
193#define ZMII_SMIISR_EC (0x40)
194#define ZMII_SMIISR_EN (0x20)
195#define ZMII_SMIISR_EJ (0x10)
196#define ZMII_SMIISR_EL (0x08)
197#define ZMII_SMIISR_ED (0x04)
198#define ZMII_SMIISR_ES (0x02)
199#define ZMII_SMIISR_EF (0x01)
200
201#define ZMII_SMIISR_V(__x) ((3 - __x) * 8)
202
203/* RGMII Register Addresses */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200204#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
205#define RGMII_BASE (CFG_PERIPHERAL_BASE + 0x1000)
Stefan Roese6f2eb3f2008-03-11 15:11:18 +0100206#elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
207#define RGMII_BASE (CFG_PERIPHERAL_BASE + 0x1500)
Stefan Roesedbbd1252007-10-05 17:10:59 +0200208#elif defined(CONFIG_405EX)
209#define RGMII_BASE (CFG_PERIPHERAL_BASE + 0xB00)
Stefan Roese887e2ec2006-09-07 11:51:23 +0200210#else
wdenkba56f622004-02-06 23:19:44 +0000211#define RGMII_BASE (CFG_PERIPHERAL_BASE + 0x0790)
Stefan Roese887e2ec2006-09-07 11:51:23 +0200212#endif
wdenkba56f622004-02-06 23:19:44 +0000213#define RGMII_FER (RGMII_BASE + 0x00)
214#define RGMII_SSR (RGMII_BASE + 0x04)
215
Stefan Roese4c9e8552008-03-19 16:20:49 +0100216#if defined(CONFIG_460GT)
217#define RGMII1_BASE_OFFSET 0x100
218#endif
219
wdenkba56f622004-02-06 23:19:44 +0000220/* RGMII Function Enable (FER) Register Bit Definitions */
221/* Note: for EMAC 2 and 3 only, 440GX only */
222#define RGMII_FER_DIS (0x00)
223#define RGMII_FER_RTBI (0x04)
224#define RGMII_FER_RGMII (0x05)
225#define RGMII_FER_TBI (0x06)
226#define RGMII_FER_GMII (0x07)
227
228#define RGMII_FER_V(__x) ((__x - 2) * 4)
229
Stefan Roese6f2eb3f2008-03-11 15:11:18 +0100230#define RGMII_FER_MDIO(__x) (1 << (19 - (__x)))
231
wdenkba56f622004-02-06 23:19:44 +0000232/* RGMII Speed Selection Register Bit Definitions */
233#define RGMII_SSR_SP_10MBPS (0x00)
234#define RGMII_SSR_SP_100MBPS (0x02)
235#define RGMII_SSR_SP_1000MBPS (0x04)
236
Stefan Roesedbbd1252007-10-05 17:10:59 +0200237#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
Stefan Roese6f2eb3f2008-03-11 15:11:18 +0100238 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
Stefan Roesedbbd1252007-10-05 17:10:59 +0200239 defined(CONFIG_405EX)
Stefan Roese887e2ec2006-09-07 11:51:23 +0200240#define RGMII_SSR_V(__x) ((__x) * 8)
241#else
wdenkba56f622004-02-06 23:19:44 +0000242#define RGMII_SSR_V(__x) ((__x -2) * 8)
Stefan Roese887e2ec2006-09-07 11:51:23 +0200243#endif
wdenkba56f622004-02-06 23:19:44 +0000244
wdenkba56f622004-02-06 23:19:44 +0000245/*---------------------------------------------------------------------------+
246| TCP/IP Acceleration Hardware (TAH) 440GX Only
247+---------------------------------------------------------------------------*/
Stefan Roese846b0dd2005-08-08 12:42:22 +0200248#if defined(CONFIG_440GX)
wdenkba56f622004-02-06 23:19:44 +0000249#define TAH_BASE (CFG_PERIPHERAL_BASE + 0x0B50)
250#define TAH_REVID (TAH_BASE + 0x0) /* Revision ID (RO)*/
251#define TAH_MR (TAH_BASE + 0x10) /* Mode Register (R/W) */
252#define TAH_SSR0 (TAH_BASE + 0x14) /* Segment Size Reg 0 (R/W) */
253#define TAH_SSR1 (TAH_BASE + 0x18) /* Segment Size Reg 1 (R/W) */
254#define TAH_SSR2 (TAH_BASE + 0x1C) /* Segment Size Reg 2 (R/W) */
255#define TAH_SSR3 (TAH_BASE + 0x20) /* Segment Size Reg 3 (R/W) */
256#define TAH_SSR4 (TAH_BASE + 0x24) /* Segment Size Reg 4 (R/W) */
257#define TAH_SSR5 (TAH_BASE + 0x28) /* Segment Size Reg 5 (R/W) */
258#define TAH_TSR (TAH_BASE + 0x2C) /* Transmit Status Register (RO) */
259
wdenkba56f622004-02-06 23:19:44 +0000260/* TAH Revision */
261#define TAH_REV_RN_M (0x000FFF00) /* Revision Number */
262#define TAH_REV_BN_M (0x000000FF) /* Branch Revision Number */
263
264#define TAH_REV_RN_V (8)
265#define TAH_REV_BN_V (0)
266
267/* TAH Mode Register */
268#define TAH_MR_CVR (0x80000000) /* Checksum verification on RX */
269#define TAH_MR_SR (0x40000000) /* Software reset */
270#define TAH_MR_ST (0x3F000000) /* Send Threshold */
271#define TAH_MR_TFS (0x00E00000) /* Transmit FIFO size */
272#define TAH_MR_DTFP (0x00100000) /* Disable TX FIFO parity */
273#define TAH_MR_DIG (0x00080000) /* Disable interrupt generation */
274#define TAH_MR_RSVD (0x0007FFFF) /* Reserved */
275
276#define TAH_MR_ST_V (20)
277#define TAH_MR_TFS_V (17)
278
279#define TAH_MR_TFS_2K (0x1) /* Transmit FIFO size 2Kbyte */
280#define TAH_MR_TFS_4K (0x2) /* Transmit FIFO size 4Kbyte */
281#define TAH_MR_TFS_6K (0x3) /* Transmit FIFO size 6Kbyte */
282#define TAH_MR_TFS_8K (0x4) /* Transmit FIFO size 8Kbyte */
283#define TAH_MR_TFS_10K (0x5) /* Transmit FIFO size 10Kbyte (max)*/
284
285
286/* TAH Segment Size Registers 0:5 */
287#define TAH_SSR_RSVD0 (0xC0000000) /* Reserved */
288#define TAH_SSR_SS (0x3FFE0000) /* Segment size in multiples of 2 */
289#define TAH_SSR_RSVD1 (0x0001FFFF) /* Reserved */
290
291/* TAH Transmit Status Register */
292#define TAH_TSR_TFTS (0x80000000) /* Transmit FIFO too small */
293#define TAH_TSR_UH (0x40000000) /* Unrecognized header */
294#define TAH_TSR_NIPF (0x20000000) /* Not IPv4 */
295#define TAH_TSR_IPOP (0x10000000) /* IP option present */
296#define TAH_TSR_NISF (0x08000000) /* No IEEE SNAP format */
297#define TAH_TSR_ILTS (0x04000000) /* IP length too short */
298#define TAH_TSR_IPFP (0x02000000) /* IP fragment present */
299#define TAH_TSR_UP (0x01000000) /* Unsupported protocol */
300#define TAH_TSR_TFP (0x00800000) /* TCP flags present */
301#define TAH_TSR_SUDP (0x00400000) /* Segmentation for UDP */
302#define TAH_TSR_DLM (0x00200000) /* Data length mismatch */
303#define TAH_TSR_SIEEE (0x00100000) /* Segmentation for IEEE */
304#define TAH_TSR_TFPE (0x00080000) /* Transmit FIFO parity error */
305#define TAH_TSR_SSTS (0x00040000) /* Segment size too small */
306#define TAH_TSR_RSVD (0x0003FFFF) /* Reserved */
Stefan Roese846b0dd2005-08-08 12:42:22 +0200307#endif /* CONFIG_440GX */
wdenkba56f622004-02-06 23:19:44 +0000308
309
310/* Ethernet MAC Regsiter Addresses */
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200311#if defined(CONFIG_440)
Stefan Roese887e2ec2006-09-07 11:51:23 +0200312#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
Stefan Roese6f2eb3f2008-03-11 15:11:18 +0100313 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
314 defined(CONFIG_460EX) || defined(CONFIG_460GT)
Stefan Roesee01bd212007-03-21 13:38:59 +0100315#define EMAC_BASE (CFG_PERIPHERAL_BASE + 0x0E00)
Stefan Roesec157d8e2005-08-01 16:41:48 +0200316#else
Stefan Roesee01bd212007-03-21 13:38:59 +0100317#define EMAC_BASE (CFG_PERIPHERAL_BASE + 0x0800)
Stefan Roesec157d8e2005-08-01 16:41:48 +0200318#endif
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200319#else
Stefan Roesedbbd1252007-10-05 17:10:59 +0200320#if defined(CONFIG_405EZ) || defined(CONFIG_405EX)
Stefan Roesee01bd212007-03-21 13:38:59 +0100321#define EMAC_BASE 0xEF600900
322#else
323#define EMAC_BASE 0xEF600800
324#endif
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200325#endif
wdenkba56f622004-02-06 23:19:44 +0000326
Stefan Roesee01bd212007-03-21 13:38:59 +0100327#define EMAC_M0 (EMAC_BASE)
328#define EMAC_M1 (EMAC_BASE + 4)
329#define EMAC_TXM0 (EMAC_BASE + 8)
330#define EMAC_TXM1 (EMAC_BASE + 12)
331#define EMAC_RXM (EMAC_BASE + 16)
332#define EMAC_ISR (EMAC_BASE + 20)
333#define EMAC_IER (EMAC_BASE + 24)
334#define EMAC_IAH (EMAC_BASE + 28)
335#define EMAC_IAL (EMAC_BASE + 32)
wdenkba56f622004-02-06 23:19:44 +0000336#define EMAC_PAUSE_TIME_REG (EMAC_BASE + 44)
wdenkba56f622004-02-06 23:19:44 +0000337#define EMAC_I_FRAME_GAP_REG (EMAC_BASE + 88)
Stefan Roesee01bd212007-03-21 13:38:59 +0100338#define EMAC_STACR (EMAC_BASE + 92)
339#define EMAC_TRTR (EMAC_BASE + 96)
340#define EMAC_RX_HI_LO_WMARK (EMAC_BASE + 100)
wdenkba56f622004-02-06 23:19:44 +0000341
342/* bit definitions */
343/* MODE REG 0 */
Stefan Roesee01bd212007-03-21 13:38:59 +0100344#define EMAC_M0_RXI (0x80000000)
345#define EMAC_M0_TXI (0x40000000)
346#define EMAC_M0_SRST (0x20000000)
347#define EMAC_M0_TXE (0x10000000)
348#define EMAC_M0_RXE (0x08000000)
349#define EMAC_M0_WKE (0x04000000)
wdenkba56f622004-02-06 23:19:44 +0000350
Stefan Roese17f50f222005-08-04 17:09:16 +0200351/* on 440GX EMAC_MR1 has a different layout! */
Stefan Roese887e2ec2006-09-07 11:51:23 +0200352#if defined(CONFIG_440GX) || \
353 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
Stefan Roesedbbd1252007-10-05 17:10:59 +0200354 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
Stefan Roese6f2eb3f2008-03-11 15:11:18 +0100355 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
Stefan Roesedbbd1252007-10-05 17:10:59 +0200356 defined(CONFIG_405EX)
wdenkba56f622004-02-06 23:19:44 +0000357/* MODE Reg 1 */
358#define EMAC_M1_FDE (0x80000000)
359#define EMAC_M1_ILE (0x40000000)
360#define EMAC_M1_VLE (0x20000000)
Stefan Roesee01bd212007-03-21 13:38:59 +0100361#define EMAC_M1_EIFC (0x10000000)
362#define EMAC_M1_APP (0x08000000)
363#define EMAC_M1_RSVD (0x06000000)
364#define EMAC_M1_IST (0x01000000)
365#define EMAC_M1_MF_1000MBPS (0x00800000) /* 0's for 10MBPS */
366#define EMAC_M1_MF_100MBPS (0x00400000)
Stefan Roese76957cb2008-03-01 12:11:40 +0100367#define EMAC_M1_RFS_MASK (0x00380000)
368#define EMAC_M1_RFS_16K (0x00280000)
369#define EMAC_M1_RFS_8K (0x00200000)
370#define EMAC_M1_RFS_4K (0x00180000)
Stefan Roesee01bd212007-03-21 13:38:59 +0100371#define EMAC_M1_RFS_2K (0x00100000)
372#define EMAC_M1_RFS_1K (0x00080000)
Stefan Roese76957cb2008-03-01 12:11:40 +0100373#define EMAC_M1_TX_FIFO_MASK (0x00070000)
374#define EMAC_M1_TX_FIFO_16K (0x00050000)
Stefan Roesee01bd212007-03-21 13:38:59 +0100375#define EMAC_M1_TX_FIFO_8K (0x00040000)
376#define EMAC_M1_TX_FIFO_4K (0x00030000)
wdenkba56f622004-02-06 23:19:44 +0000377#define EMAC_M1_TX_FIFO_2K (0x00020000)
Stefan Roesee01bd212007-03-21 13:38:59 +0100378#define EMAC_M1_TX_FIFO_1K (0x00010000)
379#define EMAC_M1_TR_MULTI (0x00008000) /* 0'x for single packet */
wdenkba56f622004-02-06 23:19:44 +0000380#define EMAC_M1_MWSW (0x00007000)
381#define EMAC_M1_JUMBO_ENABLE (0x00000800)
382#define EMAC_M1_IPPA (0x000007c0)
383#define EMAC_M1_OBCI_GT100 (0x00000020)
384#define EMAC_M1_OBCI_100 (0x00000018)
385#define EMAC_M1_OBCI_83 (0x00000010)
386#define EMAC_M1_OBCI_66 (0x00000008)
387#define EMAC_M1_RSVD1 (0x00000007)
Stefan Roese846b0dd2005-08-08 12:42:22 +0200388#else /* defined(CONFIG_440GX) */
Stefan Roese17f50f222005-08-04 17:09:16 +0200389/* EMAC_MR1 is the same on 405GP, 405GPr, 405EP, 440GP, 440EP */
Stefan Roesee01bd212007-03-21 13:38:59 +0100390#define EMAC_M1_FDE 0x80000000
391#define EMAC_M1_ILE 0x40000000
392#define EMAC_M1_VLE 0x20000000
393#define EMAC_M1_EIFC 0x10000000
394#define EMAC_M1_APP 0x08000000
395#define EMAC_M1_AEMI 0x02000000
396#define EMAC_M1_IST 0x01000000
397#define EMAC_M1_MF_1000MBPS 0x00800000 /* 0's for 10MBPS */
398#define EMAC_M1_MF_100MBPS 0x00400000
Stefan Roese76957cb2008-03-01 12:11:40 +0100399#define EMAC_M1_RFS_MASK 0x00300000
400#define EMAC_M1_RFS_4K 0x00300000
Stefan Roesee01bd212007-03-21 13:38:59 +0100401#define EMAC_M1_RFS_2K 0x00200000
402#define EMAC_M1_RFS_1K 0x00100000
Stefan Roese76957cb2008-03-01 12:11:40 +0100403#define EMAC_M1_RFS_512 0x00000000
404#define EMAC_M1_TX_FIFO_MASK 0x000c0000
405#define EMAC_M1_TX_FIFO_2K 0x00080000
Stefan Roesee01bd212007-03-21 13:38:59 +0100406#define EMAC_M1_TX_FIFO_1K 0x00040000
Stefan Roese76957cb2008-03-01 12:11:40 +0100407#define EMAC_M1_TX_FIFO_512 0x00000000
Stefan Roesee01bd212007-03-21 13:38:59 +0100408#define EMAC_M1_TR0_DEPEND 0x00010000 /* 0'x for single packet */
409#define EMAC_M1_TR0_MULTI 0x00008000
410#define EMAC_M1_TR1_DEPEND 0x00004000
411#define EMAC_M1_TR1_MULTI 0x00002000
Stefan Roese846b0dd2005-08-08 12:42:22 +0200412#if defined(CONFIG_440EP) || defined(CONFIG_440GR)
Stefan Roesee01bd212007-03-21 13:38:59 +0100413#define EMAC_M1_JUMBO_ENABLE 0x00001000
Stefan Roese846b0dd2005-08-08 12:42:22 +0200414#endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */
415#endif /* defined(CONFIG_440GX) */
Stefan Roese17f50f222005-08-04 17:09:16 +0200416
Stefan Roese76957cb2008-03-01 12:11:40 +0100417#define EMAC_MR1_FIFO_MASK (EMAC_M1_RFS_MASK | EMAC_M1_TX_FIFO_MASK)
418#if defined(CONFIG_405EZ)
419/* 405EZ only supports 512 bytes fifos */
420#define EMAC_MR1_FIFO_SIZE (EMAC_M1_RFS_512 | EMAC_M1_TX_FIFO_512)
421#else
422/* Set receive fifo to 4k and tx fifo to 2k */
423#define EMAC_MR1_FIFO_SIZE (EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K)
424#endif
425
wdenkba56f622004-02-06 23:19:44 +0000426/* Transmit Mode Register 0 */
Stefan Roesee01bd212007-03-21 13:38:59 +0100427#define EMAC_TXM0_GNP0 (0x80000000)
428#define EMAC_TXM0_GNP1 (0x40000000)
429#define EMAC_TXM0_GNPD (0x20000000)
430#define EMAC_TXM0_FC (0x10000000)
wdenkba56f622004-02-06 23:19:44 +0000431
432/* Receive Mode Register */
433#define EMAC_RMR_SP (0x80000000)
434#define EMAC_RMR_SFCS (0x40000000)
435#define EMAC_RMR_ARRP (0x20000000)
436#define EMAC_RMR_ARP (0x10000000)
437#define EMAC_RMR_AROP (0x08000000)
438#define EMAC_RMR_ARPI (0x04000000)
439#define EMAC_RMR_PPP (0x02000000)
440#define EMAC_RMR_PME (0x01000000)
441#define EMAC_RMR_PMME (0x00800000)
442#define EMAC_RMR_IAE (0x00400000)
443#define EMAC_RMR_MIAE (0x00200000)
444#define EMAC_RMR_BAE (0x00100000)
445#define EMAC_RMR_MAE (0x00080000)
446
447/* Interrupt Status & enable Regs */
448#define EMAC_ISR_OVR (0x02000000)
449#define EMAC_ISR_PP (0x01000000)
450#define EMAC_ISR_BP (0x00800000)
451#define EMAC_ISR_RP (0x00400000)
Stefan Roesee01bd212007-03-21 13:38:59 +0100452#define EMAC_ISR_SE (0x00200000)
453#define EMAC_ISR_SYE (0x00100000)
454#define EMAC_ISR_BFCS (0x00080000)
455#define EMAC_ISR_PTLE (0x00040000)
456#define EMAC_ISR_ORE (0x00020000)
457#define EMAC_ISR_IRE (0x00010000)
458#define EMAC_ISR_DBDM (0x00000200)
459#define EMAC_ISR_DB0 (0x00000100)
460#define EMAC_ISR_SE0 (0x00000080)
461#define EMAC_ISR_TE0 (0x00000040)
462#define EMAC_ISR_DB1 (0x00000020)
463#define EMAC_ISR_SE1 (0x00000010)
464#define EMAC_ISR_TE1 (0x00000008)
465#define EMAC_ISR_MOS (0x00000002)
466#define EMAC_ISR_MOF (0x00000001)
wdenkba56f622004-02-06 23:19:44 +0000467
468/* STA CONTROL REG */
Stefan Roesee01bd212007-03-21 13:38:59 +0100469#define EMAC_STACR_OC (0x00008000)
470#define EMAC_STACR_PHYE (0x00004000)
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200471
472#ifdef CONFIG_IBM_EMAC4_V4 /* EMAC4 V4 changed bit setting */
Stefan Roesee01bd212007-03-21 13:38:59 +0100473#define EMAC_STACR_INDIRECT_MODE (0x00002000)
474#define EMAC_STACR_WRITE (0x00000800) /* $BUC */
475#define EMAC_STACR_READ (0x00001000) /* $BUC */
476#define EMAC_STACR_OP_MASK (0x00001800)
477#define EMAC_STACR_MDIO_ADDR (0x00000000)
478#define EMAC_STACR_MDIO_WRITE (0x00000800)
479#define EMAC_STACR_MDIO_READ (0x00001800)
480#define EMAC_STACR_MDIO_READ_INC (0x00001000)
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200481#else
Stefan Roesee01bd212007-03-21 13:38:59 +0100482#define EMAC_STACR_WRITE (0x00002000)
483#define EMAC_STACR_READ (0x00001000)
Marian Balakowicz6c5879f2006-06-30 16:30:46 +0200484#endif
485
wdenkba56f622004-02-06 23:19:44 +0000486#define EMAC_STACR_CLK_83MHZ (0x00000800) /* 0's for 50Mhz */
487#define EMAC_STACR_CLK_66MHZ (0x00000400)
488#define EMAC_STACR_CLK_100MHZ (0x00000C00)
489
490/* Transmit Request Threshold Register */
Stefan Roesee01bd212007-03-21 13:38:59 +0100491#define EMAC_TRTR_256 (0x18000000) /* 0's for 64 Bytes */
492#define EMAC_TRTR_192 (0x10000000)
493#define EMAC_TRTR_128 (0x01000000)
wdenkba56f622004-02-06 23:19:44 +0000494
495/* the follwing defines are for the MadMAL status and control registers. */
496/* For bits 0..5 look at the mal.h file */
497#define EMAC_TX_CTRL_GFCS (0x0200)
498#define EMAC_TX_CTRL_GP (0x0100)
499#define EMAC_TX_CTRL_ISA (0x0080)
500#define EMAC_TX_CTRL_RSA (0x0040)
501#define EMAC_TX_CTRL_IVT (0x0020)
502#define EMAC_TX_CTRL_RVT (0x0010)
503
504#define EMAC_TX_CTRL_DEFAULT (EMAC_TX_CTRL_GFCS |EMAC_TX_CTRL_GP)
505
506#define EMAC_TX_ST_BFCS (0x0200)
507#define EMAC_TX_ST_BPP (0x0100)
508#define EMAC_TX_ST_LCS (0x0080)
509#define EMAC_TX_ST_ED (0x0040)
510#define EMAC_TX_ST_EC (0x0020)
511#define EMAC_TX_ST_LC (0x0010)
512#define EMAC_TX_ST_MC (0x0008)
513#define EMAC_TX_ST_SC (0x0004)
514#define EMAC_TX_ST_UR (0x0002)
515#define EMAC_TX_ST_SQE (0x0001)
516
517#define EMAC_TX_ST_DEFAULT (0x03F3)
518
519
520/* madmal receive status / Control bits */
521
522#define EMAC_RX_ST_OE (0x0200)
523#define EMAC_RX_ST_PP (0x0100)
524#define EMAC_RX_ST_BP (0x0080)
525#define EMAC_RX_ST_RP (0x0040)
526#define EMAC_RX_ST_SE (0x0020)
527#define EMAC_RX_ST_AE (0x0010)
528#define EMAC_RX_ST_BFCS (0x0008)
529#define EMAC_RX_ST_PTL (0x0004)
530#define EMAC_RX_ST_ORE (0x0002)
531#define EMAC_RX_ST_IRE (0x0001)
532/* all the errors we care about */
533#define EMAC_RX_ERRORS (0x03FF)
534
Stefan Roesed6c61aa2005-08-16 18:18:00 +0200535#endif /* _PPC4XX_ENET_H_ */