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Nobuhiro Iwamatsu8d811ca2012-06-21 14:55:07 +09001/*
2 * Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
3 * Copyright (C) 2012 Renesas Solutions Corp.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
Nobuhiro Iwamatsu8d811ca2012-06-21 14:55:07 +09006 */
7
8#ifndef __KZM9G_H
9#define __KZM9G_H
10
11#undef DEBUG
12
Nobuhiro Iwamatsu8d811ca2012-06-21 14:55:07 +090013#define CONFIG_SH73A0
14#define CONFIG_KZM_A9_GT
Nobuhiro Iwamatsu1cc95f62015-10-10 05:58:28 +090015#define CONFIG_ARCH_RMOBILE_BOARD_STRING "KMC KZM-A9-GT"
Nobuhiro Iwamatsu8d811ca2012-06-21 14:55:07 +090016#define CONFIG_MACH_TYPE MACH_TYPE_KZM9G
17
18#include <asm/arch/rmobile.h>
19
20#define CONFIG_ARCH_CPU_INIT
Nobuhiro Iwamatsu8d811ca2012-06-21 14:55:07 +090021
Nobuhiro Iwamatsu8d811ca2012-06-21 14:55:07 +090022#define CONFIG_CMDLINE_TAG
23#define CONFIG_SETUP_MEMORY_TAGS
24#define CONFIG_INITRD_TAG
Nobuhiro Iwamatsu8d811ca2012-06-21 14:55:07 +090025
Nobuhiro Iwamatsu8d811ca2012-06-21 14:55:07 +090026#define CONFIG_BOOTARGS "root=/dev/null console=ttySC4,115200"
Nobuhiro Iwamatsu8d811ca2012-06-21 14:55:07 +090027
Nobuhiro Iwamatsu8d811ca2012-06-21 14:55:07 +090028#undef CONFIG_SHOW_BOOT_PROGRESS
29
30/* MEMORY */
31#define KZM_SDRAM_BASE (0x40000000)
32#define PHYS_SDRAM KZM_SDRAM_BASE
33#define PHYS_SDRAM_SIZE (512 * 1024 * 1024)
34#define CONFIG_NR_DRAM_BANKS (1)
35
36/* NOR Flash */
37#define KZM_FLASH_BASE (0x00000000)
38#define CONFIG_SYS_FLASH_BASE (KZM_FLASH_BASE)
39#define CONFIG_SYS_FLASH_CFI_WIDTH (FLASH_CFI_16BIT)
40#define CONFIG_SYS_MAX_FLASH_BANKS (1)
41#define CONFIG_SYS_MAX_FLASH_SECT (512)
42
43/* prompt */
44#define CONFIG_SYS_LONGHELP
Nobuhiro Iwamatsu8d811ca2012-06-21 14:55:07 +090045#define CONFIG_SYS_CBSIZE 256
46#define CONFIG_SYS_PBSIZE 256
47#define CONFIG_SYS_MAXARGS 16
48#define CONFIG_SYS_BARGSIZE 512
49#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
50
51/* SCIF */
52#define CONFIG_SCIF_CONSOLE
53#define CONFIG_CONS_SCIF4
Nobuhiro Iwamatsu8d811ca2012-06-21 14:55:07 +090054
55#define CONFIG_SYS_MEMTEST_START (KZM_SDRAM_BASE)
56#define CONFIG_SYS_MEMTEST_END \
57 (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
58#undef CONFIG_SYS_ALT_MEMTEST
59#undef CONFIG_SYS_MEMTEST_SCRATCH
60#undef CONFIG_SYS_LOADS_BAUD_CHANGE
61
62#define CONFIG_SYS_INIT_RAM_ADDR (0xE5600000) /* on MERAM */
63#define CONFIG_SYS_INIT_RAM_SIZE (0x10000)
64#define LOW_LEVEL_MERAM_STACK (CONFIG_SYS_INIT_RAM_ADDR - 4)
65#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
66 CONFIG_SYS_INIT_RAM_SIZE - \
67 GENERATED_GBL_DATA_SIZE)
Tetsuyuki Kobayashi9415cf92012-07-05 01:43:44 +000068#define CONFIG_SDRAM_OFFSET_FOR_RT (16 * 1024 * 1024)
69#define CONFIG_SYS_SDRAM_BASE (KZM_SDRAM_BASE + CONFIG_SDRAM_OFFSET_FOR_RT)
70#define CONFIG_SYS_SDRAM_SIZE (PHYS_SDRAM_SIZE - CONFIG_SDRAM_OFFSET_FOR_RT)
Nobuhiro Iwamatsu8d811ca2012-06-21 14:55:07 +090071#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024)
72
73#define CONFIG_SYS_MONITOR_BASE (KZM_FLASH_BASE)
74#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 128 * 1024)
Nobuhiro Iwamatsu8d811ca2012-06-21 14:55:07 +090075#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
76
77#define CONFIG_SYS_TEXT_BASE 0x00000000
78#define CONFIG_STANDALONE_LOAD_ADDR 0x41000000
79
80/* FLASH */
81#define CONFIG_FLASH_CFI_DRIVER
82#define CONFIG_SYS_FLASH_CFI
83#undef CONFIG_SYS_FLASH_QUIET_TEST
84#define CONFIG_SYS_FLASH_EMPTY_INFO
85#define FLASH_SECTOR_SIZE (256 * 1024) /* 256 KB sectors */
86#define CONFIG_ENV_SIZE FLASH_SECTOR_SIZE
87#define CONFIG_ENV_OFFSET FLASH_SECTOR_SIZE
88#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
89
90/* Timeout for Flash erase operations (in ms) */
91#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000)
92/* Timeout for Flash write operations (in ms) */
93#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000)
94/* Timeout for Flash set sector lock bit operations (in ms) */
95#define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000)
96/* Timeout for Flash clear lock bit operations (in ms) */
97#define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000)
98
99#undef CONFIG_SYS_FLASH_PROTECTION
100#undef CONFIG_SYS_DIRECT_FLASH_TFTP
101#define CONFIG_ENV_IS_IN_FLASH
102
103/* GPIO / PFC */
104#define CONFIG_SH_GPIO_PFC
105
106/* Clock */
Nobuhiro Iwamatsueae6c8a2012-08-03 13:56:52 +0900107#define CONFIG_GLOBAL_TIMER
Nobuhiro Iwamatsu8d811ca2012-06-21 14:55:07 +0900108#define CONFIG_SYS_CLK_FREQ (48000000)
109#define CONFIG_SYS_CPU_CLK (1196000000)
Nobuhiro Iwamatsu59562ff2013-09-30 10:30:40 +0900110#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
Nobuhiro Iwamatsu8d811ca2012-06-21 14:55:07 +0900111#define TMU_CLK_DIVIDER (4) /* 4 (default), 16, 64, 256 or 1024 */
Nobuhiro Iwamatsu8d811ca2012-06-21 14:55:07 +0900112
113/* Ether */
Nobuhiro Iwamatsu8d811ca2012-06-21 14:55:07 +0900114#define CONFIG_SMC911X
115#define CONFIG_SMC911X_BASE (0x10000000)
116#define CONFIG_SMC911X_32_BIT
Tetsuyuki Kobayashi38263df2012-07-25 18:24:18 +0000117#define CONFIG_NFS_TIMEOUT 10000UL
Nobuhiro Iwamatsu8d811ca2012-06-21 14:55:07 +0900118
119/* I2C */
Nobuhiro Iwamatsu2035d772013-10-29 13:33:51 +0900120#define CONFIG_SYS_I2C
121#define CONFIG_SYS_I2C_SH
122#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 5
123#define CONFIG_SYS_I2C_SH_BASE0 0xE6820000
124#define CONFIG_SYS_I2C_SH_SPEED0 100000
125#define CONFIG_SYS_I2C_SH_BASE1 0xE6822000
126#define CONFIG_SYS_I2C_SH_SPEED1 100000
127#define CONFIG_SYS_I2C_SH_BASE2 0xE6824000
128#define CONFIG_SYS_I2C_SH_SPEED2 100000
129#define CONFIG_SYS_I2C_SH_BASE3 0xE6826000
130#define CONFIG_SYS_I2C_SH_SPEED3 100000
131#define CONFIG_SYS_I2C_SH_BASE4 0xE6828000
132#define CONFIG_SYS_I2C_SH_SPEED4 100000
Tetsuyuki Kobayashib1af67f2012-09-13 19:07:56 +0000133#define CONFIG_SH_I2C_8BIT
Nobuhiro Iwamatsu2035d772013-10-29 13:33:51 +0900134#define CONFIG_SH_I2C_DATA_HIGH 4
135#define CONFIG_SH_I2C_DATA_LOW 5
136#define CONFIG_SH_I2C_CLOCK 104000000 /* 104 MHz */
Nobuhiro Iwamatsu8d811ca2012-06-21 14:55:07 +0900137
138#endif /* __KZM9G_H */