blob: 2793a9bfb962ca155261f9a243b1a8cf29deb1bb [file] [log] [blame]
John Schmollerbfe18812010-10-22 00:20:34 -05001/*
2 * Copyright 2010 Extreme Engineering Solutions, Inc.
3 * Copyright 2007-2008 Freescale Semiconductor, Inc.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
John Schmollerbfe18812010-10-22 00:20:34 -05006 */
7
8/*
9 * xpedite550x board configuration file
10 */
11#ifndef __CONFIG_H
12#define __CONFIG_H
13
14/*
15 * High Level Configuration Options
16 */
John Schmollerbfe18812010-10-22 00:20:34 -050017#define CONFIG_XPEDITE550X 1
18#define CONFIG_SYS_BOARD_NAME "XPedite5500"
19#define CONFIG_SYS_FORM_PMC_XMC 1
20#define CONFIG_PRPMC_PCI_ALIAS "pci0" /* Processor PMC interface on pci0 */
21#define CONFIG_BOARD_EARLY_INIT_R /* Call board_pre_init */
22
23#ifndef CONFIG_SYS_TEXT_BASE
24#define CONFIG_SYS_TEXT_BASE 0xfff80000
25#endif
26
John Schmollerbfe18812010-10-22 00:20:34 -050027#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
Robert P. J. Dayb38eaec2016-05-03 19:52:49 -040028#define CONFIG_PCIE1 1 /* PCIE controller 1 (PEX8112 or XMC) */
John Schmollerbfe18812010-10-22 00:20:34 -050029#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
Gabor Juhos842033e2013-05-30 07:06:12 +000030#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */
John Schmollerbfe18812010-10-22 00:20:34 -050031#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
32#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
John Schmollerbfe18812010-10-22 00:20:34 -050033
34/*
35 * Multicore config
36 */
37#define CONFIG_MP
38#define CONFIG_BPTR_VIRT_ADDR 0xee000000 /* virt boot page address */
39#define CONFIG_MPC8xxx_DISABLE_BPTR /* Don't leave BPTR enabled */
40
41/*
42 * DDR config
43 */
John Schmollerbfe18812010-10-22 00:20:34 -050044#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
45#define CONFIG_DDR_SPD
46#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
Kumar Galac39f44d2011-01-31 22:18:47 -060047#define SPD_EEPROM_ADDRESS 0x54
John Schmollerbfe18812010-10-22 00:20:34 -050048#define SPD_EEPROM_OFFSET 0x200 /* OFFSET of SPD in EEPROM */
John Schmollerbfe18812010-10-22 00:20:34 -050049#define CONFIG_DIMM_SLOTS_PER_CTLR 1
50#define CONFIG_CHIP_SELECTS_PER_CTRL 2
51#define CONFIG_DDR_ECC
52#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
53#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
54#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
55#define CONFIG_VERY_BIG_RAM
56
57#ifndef __ASSEMBLY__
58extern unsigned long get_board_sys_clk(unsigned long dummy);
59extern unsigned long get_board_ddr_clk(unsigned long dummy);
60#endif
61
62#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0) /* sysclk for MPC85xx */
63#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk(0) /* ddrclk for MPC85xx */
64
65/*
66 * These can be toggled for performance analysis, otherwise use default.
67 */
68#define CONFIG_L2_CACHE /* toggle L2 cache */
69#define CONFIG_BTB /* toggle branch predition */
70#define CONFIG_ENABLE_36BIT_PHYS 1
71
Timur Tabie46fedf2011-08-04 18:03:41 -050072#define CONFIG_SYS_CCSRBAR 0xef000000
73#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
John Schmollerbfe18812010-10-22 00:20:34 -050074
75/*
76 * Diagnostics
77 */
78#define CONFIG_SYS_ALT_MEMTEST
79#define CONFIG_SYS_MEMTEST_START 0x10000000
80#define CONFIG_SYS_MEMTEST_END 0x20000000
81#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \
82 CONFIG_SYS_POST_I2C)
83#define I2C_ADDR_LIST {CONFIG_SYS_I2C_EEPROM_ADDR, \
84 CONFIG_SYS_I2C_LM75_ADDR, \
85 CONFIG_SYS_I2C_LM90_ADDR, \
86 CONFIG_SYS_I2C_PCA953X_ADDR0, \
87 CONFIG_SYS_I2C_PCA953X_ADDR2, \
88 CONFIG_SYS_I2C_PCA953X_ADDR3, \
89 CONFIG_SYS_I2C_RTC_ADDR}
90
91/*
92 * Memory map
93 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
94 * 0x8000_0000 0xbfff_ffff PCIe1 Mem 1G non-cacheable
95 * 0xe000_0000 0xe7ff_ffff SRAM/SSRAM/L1 Cache 128M non-cacheable
96 * 0xe800_0000 0xe87f_ffff PCIe1 IO 8M non-cacheable
97 * 0xee00_0000 0xee00_ffff Boot page translation 4K non-cacheable
98 * 0xef00_0000 0xef0f_ffff CCSR/IMMR 1M non-cacheable
99 * 0xef80_0000 0xef8f_ffff NAND Flash 1M non-cacheable
100 * 0xf000_0000 0xf7ff_ffff NOR Flash 2 128M non-cacheable
101 * 0xf800_0000 0xffff_ffff NOR Flash 1 128M non-cacheable
102 */
103
104#define CONFIG_SYS_LBC_LCRR (LCRR_CLKDIV_8 | LCRR_EADC_3)
105
106/*
107 * NAND flash configuration
108 */
109#define CONFIG_SYS_NAND_BASE 0xef800000
110#define CONFIG_SYS_NAND_BASE2 0xef840000 /* Unused at this time */
111#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, \
112 CONFIG_SYS_NAND_BASE2}
113#define CONFIG_SYS_MAX_NAND_DEVICE 2
John Schmollerbfe18812010-10-22 00:20:34 -0500114#define CONFIG_NAND_FSL_ELBC
115
116/*
117 * NOR flash configuration
118 */
119#define CONFIG_SYS_FLASH_BASE 0xf8000000
120#define CONFIG_SYS_FLASH_BASE2 0xf0000000
121#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
122#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
123#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
124#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
125#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
126#define CONFIG_FLASH_CFI_DRIVER
127#define CONFIG_SYS_FLASH_CFI
128#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
129#define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { {0xfff40000, 0xc0000}, \
130 {0xf7f40000, 0xc0000} }
131#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
132
133/*
134 * Chip select configuration
135 */
136/* NOR Flash 0 on CS0 */
137#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | \
138 BR_PS_16 | \
139 BR_V)
140#define CONFIG_SYS_OR0_PRELIM (OR_AM_128MB | \
141 OR_GPCM_CSNT | \
142 OR_GPCM_XACS | \
143 OR_GPCM_ACS_DIV2 | \
144 OR_GPCM_SCY_8 | \
145 OR_GPCM_TRLX | \
146 OR_GPCM_EHTR | \
147 OR_GPCM_EAD)
148
149/* NOR Flash 1 on CS1 */
150#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_FLASH_BASE2 | \
151 BR_PS_16 | \
152 BR_V)
153#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
154
155/* NAND flash on CS2 */
156#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_NAND_BASE | \
157 (2<<BR_DECC_SHIFT) | \
158 BR_PS_8 | \
159 BR_MS_FCM | \
160 BR_V)
161
162/* NAND flash on CS2 */
163#define CONFIG_SYS_OR2_PRELIM (OR_AM_256KB | \
164 OR_FCM_PGS | \
165 OR_FCM_CSCT | \
166 OR_FCM_CST | \
167 OR_FCM_CHT | \
168 OR_FCM_SCY_1 | \
169 OR_FCM_TRLX | \
170 OR_FCM_EHTR)
171
172/* NAND flash on CS3 */
173#define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_NAND_BASE2 | \
174 (2<<BR_DECC_SHIFT) | \
175 BR_PS_8 | \
176 BR_MS_FCM | \
177 BR_V)
178#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
179
180/*
181 * Use L1 as initial stack
182 */
183#define CONFIG_SYS_INIT_RAM_LOCK 1
184#define CONFIG_SYS_INIT_RAM_ADDR 0xe0000000
Wolfgang Denk553f0982010-10-26 13:32:32 +0200185#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
John Schmollerbfe18812010-10-22 00:20:34 -0500186
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200187#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
John Schmollerbfe18812010-10-22 00:20:34 -0500188#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
189
190#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 KB for Mon */
191#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */
192
193/*
194 * Serial Port
195 */
196#define CONFIG_CONS_INDEX 1
John Schmollerbfe18812010-10-22 00:20:34 -0500197#define CONFIG_SYS_NS16550_SERIAL
198#define CONFIG_SYS_NS16550_REG_SIZE 1
199#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
200#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
201#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
202#define CONFIG_SYS_BAUDRATE_TABLE \
203 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
John Schmollerbfe18812010-10-22 00:20:34 -0500204#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
205#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
206
John Schmollerbfe18812010-10-22 00:20:34 -0500207#define CONFIG_FDT_FIXUP_PCI_IRQ 1
208
209/*
210 * I2C
211 */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200212#define CONFIG_SYS_I2C
213#define CONFIG_SYS_I2C_FSL
214#define CONFIG_SYS_FSL_I2C_SPEED 400000
215#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
216#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
217#define CONFIG_SYS_FSL_I2C2_SPEED 400000
218#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
219#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
John Schmollerbfe18812010-10-22 00:20:34 -0500220
221/* I2C DS7505 temperature sensor */
222#define CONFIG_DTT_LM75
223#define CONFIG_DTT_SENSORS { 0 }
224#define CONFIG_SYS_I2C_LM75_ADDR 0x48
225
226/* I2C ADT7461 temperature sensor */
227#define CONFIG_SYS_I2C_LM90_ADDR 0x4C
228
229/* I2C EEPROM - AT24C128B */
230#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54
231#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
232#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 byte pages */
233#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* take up to 10 msec */
234
235/* I2C RTC */
236#define CONFIG_RTC_M41T11 1
237#define CONFIG_SYS_I2C_RTC_ADDR 0x68
238#define CONFIG_SYS_M41T11_BASE_YEAR 2000
239
240/* GPIO */
241#define CONFIG_PCA953X
242#define CONFIG_SYS_I2C_PCA953X_ADDR0 0x18
243#define CONFIG_SYS_I2C_PCA953X_ADDR1 0x1c
244#define CONFIG_SYS_I2C_PCA953X_ADDR2 0x1e
245#define CONFIG_SYS_I2C_PCA953X_ADDR3 0x1f
246#define CONFIG_SYS_I2C_PCA953X_ADDR CONFIG_SYS_I2C_PCA953X_ADDR0
247
248/*
249 * GPIO pin definitions, PU = pulled high, PD = pulled low
250 */
251/* PCA9557 @ 0x18*/
252#define CONFIG_SYS_PCA953X_C0_SER0_EN 0x01 /* PU; UART0 enable (1: enabled) */
253#define CONFIG_SYS_PCA953X_C0_SER0_MODE 0x02 /* PU; UART0 serial mode select (1: RS-485, 0: RS-232) */
254#define CONFIG_SYS_PCA953X_C0_SER1_EN 0x04 /* PU; UART1 enable (1: enabled) */
255#define CONFIG_SYS_PCA953X_C0_SER1_MODE 0x08 /* PU; UART1 serial mode select (1: RS-485, 0: RS-232) */
256#define CONFIG_SYS_PCA953X_C0_FLASH_PASS_CS 0x10 /* PU; Boot flash CS select */
257#define CONFIG_SYS_PCA953X_NVM_WP 0x20 /* PU; Write protection (0: disabled, 1: enabled) */
258
259/* PCA9557 @ 0x1e*/
260#define CONFIG_SYS_PCA953X_XMC_GA0 0x01 /* PU; */
261#define CONFIG_SYS_PCA953X_XMC_GA1 0x02 /* PU; */
262#define CONFIG_SYS_PCA953X_XMC_GA2 0x04 /* PU; */
263#define CONFIG_SYS_PCA953X_XMC_WAKE 0x10 /* PU; */
264#define CONFIG_SYS_PCA953X_XMC_BIST 0x20 /* Enable XMC BIST */
265#define CONFIG_SYS_PCA953X_PMC_EREADY 0x40 /* PU; PMC PCI eready */
266#define CONFIG_SYS_PCA953X_PMC_MONARCH 0x80 /* PMC monarch mode enable */
267
268/* PCA9557 @ 0x1f */
269#define CONFIG_SYS_PCA953X_MC_GPIO0 0x01 /* PU; */
270#define CONFIG_SYS_PCA953X_MC_GPIO1 0x02 /* PU; */
271#define CONFIG_SYS_PCA953X_MC_GPIO2 0x04 /* PU; */
272#define CONFIG_SYS_PCA953X_MC_GPIO3 0x08 /* PU; */
273#define CONFIG_SYS_PCA953X_MC_GPIO4 0x10 /* PU; */
274#define CONFIG_SYS_PCA953X_MC_GPIO5 0x20 /* PU; */
275#define CONFIG_SYS_PCA953X_MC_GPIO6 0x40 /* PU; */
276#define CONFIG_SYS_PCA953X_MC_GPIO7 0x80 /* PU; */
277
278/*
279 * General PCI
280 * Memory space is mapped 1-1, but I/O space must start from 0.
281 */
282
283/* controller 1 - PEX8112 or XMC, depending on build option */
284#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000
285#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
286#define CONFIG_SYS_PCIE1_MEM_SIZE 0x40000000 /* 1G */
287#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
288#define CONFIG_SYS_PCIE1_IO_PHYS 0xe8000000
289#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */
290
John Schmollerbfe18812010-10-22 00:20:34 -0500291/*
292 * Networking options
293 */
294#define CONFIG_TSEC_ENET /* tsec ethernet support */
295#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
John Schmollerbfe18812010-10-22 00:20:34 -0500296#define CONFIG_TSEC_TBI
297#define CONFIG_MII 1 /* MII PHY management */
298#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */
299#define CONFIG_ETHPRIME "eTSEC2"
300
Kumar Gala72c96a62010-12-01 22:55:54 -0600301/*
302 * In-band SGMII auto-negotiation between TBI and BCM5482S PHY fails, force
303 * 1000mbps SGMII link
304 */
305#define CONFIG_TSEC_TBICR_SETTINGS ( \
306 TBICR_PHY_RESET \
307 | TBICR_FULL_DUPLEX \
308 | TBICR_SPEED1_SET \
309 )
310
John Schmollerbfe18812010-10-22 00:20:34 -0500311#define CONFIG_TSEC1 1
312#define CONFIG_TSEC1_NAME "eTSEC1"
313#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
314#define TSEC1_PHY_ADDR 1
315#define TSEC1_PHYIDX 0
316#define CONFIG_HAS_ETH0
317
318#define CONFIG_TSEC2 1
319#define CONFIG_TSEC2_NAME "eTSEC2"
320#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
321#define TSEC2_PHY_ADDR 2
322#define TSEC2_PHYIDX 0
323#define CONFIG_HAS_ETH1
324
325#define CONFIG_TSEC3 1
326#define CONFIG_TSEC3_NAME "eTSEC3"
327#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
328#define TSEC3_PHY_ADDR 3
329#define TSEC3_PHYIDX 0
330#define CONFIG_HAS_ETH2
331
332/*
333 * USB
334 */
John Schmollerbfe18812010-10-22 00:20:34 -0500335#define CONFIG_USB_EHCI
336#define CONFIG_USB_EHCI_FSL
337#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
John Schmollerbfe18812010-10-22 00:20:34 -0500338
339/*
340 * Command configuration.
341 */
John Schmollerbfe18812010-10-22 00:20:34 -0500342#define CONFIG_CMD_DTT
343#define CONFIG_CMD_EEPROM
John Schmollerbfe18812010-10-22 00:20:34 -0500344#define CONFIG_CMD_JFFS2
John Schmollerbfe18812010-10-22 00:20:34 -0500345#define CONFIG_CMD_NAND
John Schmollerbfe18812010-10-22 00:20:34 -0500346#define CONFIG_CMD_PCA953X
347#define CONFIG_CMD_PCA953X_INFO
348#define CONFIG_CMD_PCI
349#define CONFIG_CMD_PCI_ENUM
John Schmollerbfe18812010-10-22 00:20:34 -0500350#define CONFIG_CMD_REGINFO
John Schmollerbfe18812010-10-22 00:20:34 -0500351
352/*
353 * Miscellaneous configurable options
354 */
355#define CONFIG_SYS_LONGHELP /* undef to save memory */
356#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
John Schmollerbfe18812010-10-22 00:20:34 -0500357#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
358#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
359#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
360#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
John Schmollerbfe18812010-10-22 00:20:34 -0500361#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
362#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
363#define CONFIG_LOADADDR 0x1000000 /* default location for tftp and bootm */
John Schmollerbfe18812010-10-22 00:20:34 -0500364#define CONFIG_PANIC_HANG /* do not reset board on panic */
365#define CONFIG_PREBOOT /* enable preboot variable */
John Schmollerbfe18812010-10-22 00:20:34 -0500366#define CONFIG_INTEGRITY /* support booting INTEGRITY OS */
367
368/*
369 * For booting Linux, the board info and command line data
370 * have to be in the first 16 MB of memory, since this is
371 * the maximum mapped by the Linux kernel during initialization.
372 */
373#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
374#define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
375
376/*
John Schmollerbfe18812010-10-22 00:20:34 -0500377 * Environment Configuration
378 */
379#define CONFIG_ENV_IS_IN_FLASH 1
380#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128k (one sector) for env */
381#define CONFIG_ENV_SIZE 0x8000
382#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - (256 * 1024))
383
384/*
385 * Flash memory map:
386 * fff80000 - ffffffff Pri U-Boot (512 KB)
387 * fff40000 - fff7ffff Pri U-Boot Environment (256 KB)
388 * fff00000 - fff3ffff Pri FDT (256KB)
389 * fef00000 - ffefffff Pri OS image (16MB)
390 * f8000000 - feefffff Pri OS Use/Filesystem (111MB)
391 *
392 * f7f80000 - f7ffffff Sec U-Boot (512 KB)
393 * f7f40000 - f7f7ffff Sec U-Boot Environment (256 KB)
394 * f7f00000 - f7f3ffff Sec FDT (256KB)
395 * f6f00000 - f7efffff Sec OS image (16MB)
396 * f0000000 - f6efffff Sec OS Use/Filesystem (111MB)
397 */
Marek Vasut5368c552012-09-23 17:41:24 +0200398#define CONFIG_UBOOT1_ENV_ADDR __stringify(0xfff80000)
399#define CONFIG_UBOOT2_ENV_ADDR __stringify(0xf7f80000)
400#define CONFIG_FDT1_ENV_ADDR __stringify(0xfff00000)
401#define CONFIG_FDT2_ENV_ADDR __stringify(0xf7f00000)
402#define CONFIG_OS1_ENV_ADDR __stringify(0xfef00000)
403#define CONFIG_OS2_ENV_ADDR __stringify(0xf6f00000)
John Schmollerbfe18812010-10-22 00:20:34 -0500404
405#define CONFIG_PROG_UBOOT1 \
406 "$download_cmd $loadaddr $ubootfile; " \
407 "if test $? -eq 0; then " \
408 "protect off "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
409 "erase "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
410 "cp.w $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 40000; " \
411 "protect on "CONFIG_UBOOT1_ENV_ADDR" +80000; " \
412 "cmp.b $loadaddr "CONFIG_UBOOT1_ENV_ADDR" 80000; " \
413 "if test $? -ne 0; then " \
414 "echo PROGRAM FAILED; " \
415 "else; " \
416 "echo PROGRAM SUCCEEDED; " \
417 "fi; " \
418 "else; " \
419 "echo DOWNLOAD FAILED; " \
420 "fi;"
421
422#define CONFIG_PROG_UBOOT2 \
423 "$download_cmd $loadaddr $ubootfile; " \
424 "if test $? -eq 0; then " \
425 "protect off "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
426 "erase "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
427 "cp.w $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 40000; " \
428 "protect on "CONFIG_UBOOT2_ENV_ADDR" +80000; " \
429 "cmp.b $loadaddr "CONFIG_UBOOT2_ENV_ADDR" 80000; " \
430 "if test $? -ne 0; then " \
431 "echo PROGRAM FAILED; " \
432 "else; " \
433 "echo PROGRAM SUCCEEDED; " \
434 "fi; " \
435 "else; " \
436 "echo DOWNLOAD FAILED; " \
437 "fi;"
438
439#define CONFIG_BOOT_OS_NET \
440 "$download_cmd $osaddr $osfile; " \
441 "if test $? -eq 0; then " \
442 "if test -n $fdtaddr; then " \
443 "$download_cmd $fdtaddr $fdtfile; " \
444 "if test $? -eq 0; then " \
445 "bootm $osaddr - $fdtaddr; " \
446 "else; " \
447 "echo FDT DOWNLOAD FAILED; " \
448 "fi; " \
449 "else; " \
450 "bootm $osaddr; " \
451 "fi; " \
452 "else; " \
453 "echo OS DOWNLOAD FAILED; " \
454 "fi;"
455
456#define CONFIG_PROG_OS1 \
457 "$download_cmd $osaddr $osfile; " \
458 "if test $? -eq 0; then " \
459 "erase "CONFIG_OS1_ENV_ADDR" +$filesize; " \
460 "cp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
461 "cmp.b $osaddr "CONFIG_OS1_ENV_ADDR" $filesize; " \
462 "if test $? -ne 0; then " \
463 "echo OS PROGRAM FAILED; " \
464 "else; " \
465 "echo OS PROGRAM SUCCEEDED; " \
466 "fi; " \
467 "else; " \
468 "echo OS DOWNLOAD FAILED; " \
469 "fi;"
470
471#define CONFIG_PROG_OS2 \
472 "$download_cmd $osaddr $osfile; " \
473 "if test $? -eq 0; then " \
474 "erase "CONFIG_OS2_ENV_ADDR" +$filesize; " \
475 "cp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
476 "cmp.b $osaddr "CONFIG_OS2_ENV_ADDR" $filesize; " \
477 "if test $? -ne 0; then " \
478 "echo OS PROGRAM FAILED; " \
479 "else; " \
480 "echo OS PROGRAM SUCCEEDED; " \
481 "fi; " \
482 "else; " \
483 "echo OS DOWNLOAD FAILED; " \
484 "fi;"
485
486#define CONFIG_PROG_FDT1 \
487 "$download_cmd $fdtaddr $fdtfile; " \
488 "if test $? -eq 0; then " \
489 "erase "CONFIG_FDT1_ENV_ADDR" +$filesize;" \
490 "cp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
491 "cmp.b $fdtaddr "CONFIG_FDT1_ENV_ADDR" $filesize; " \
492 "if test $? -ne 0; then " \
493 "echo FDT PROGRAM FAILED; " \
494 "else; " \
495 "echo FDT PROGRAM SUCCEEDED; " \
496 "fi; " \
497 "else; " \
498 "echo FDT DOWNLOAD FAILED; " \
499 "fi;"
500
501#define CONFIG_PROG_FDT2 \
502 "$download_cmd $fdtaddr $fdtfile; " \
503 "if test $? -eq 0; then " \
504 "erase "CONFIG_FDT2_ENV_ADDR" +$filesize;" \
505 "cp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
506 "cmp.b $fdtaddr "CONFIG_FDT2_ENV_ADDR" $filesize; " \
507 "if test $? -ne 0; then " \
508 "echo FDT PROGRAM FAILED; " \
509 "else; " \
510 "echo FDT PROGRAM SUCCEEDED; " \
511 "fi; " \
512 "else; " \
513 "echo FDT DOWNLOAD FAILED; " \
514 "fi;"
515
516#define CONFIG_EXTRA_ENV_SETTINGS \
517 "autoload=yes\0" \
518 "download_cmd=tftp\0" \
519 "console_args=console=ttyS0,115200\0" \
520 "root_args=root=/dev/nfs rw\0" \
521 "misc_args=ip=on\0" \
522 "set_bootargs=setenv bootargs ${console_args} ${root_args} ${misc_args}\0" \
523 "bootfile=/home/user/file\0" \
524 "osfile=/home/user/board.uImage\0" \
525 "fdtfile=/home/user/board.dtb\0" \
526 "ubootfile=/home/user/u-boot.bin\0" \
Scott Woodb24a4f62016-07-19 17:52:06 -0500527 "fdtaddr=0x1e00000\0" \
John Schmollerbfe18812010-10-22 00:20:34 -0500528 "osaddr=0x1000000\0" \
529 "loadaddr=0x1000000\0" \
530 "prog_uboot1="CONFIG_PROG_UBOOT1"\0" \
531 "prog_uboot2="CONFIG_PROG_UBOOT2"\0" \
532 "prog_os1="CONFIG_PROG_OS1"\0" \
533 "prog_os2="CONFIG_PROG_OS2"\0" \
534 "prog_fdt1="CONFIG_PROG_FDT1"\0" \
535 "prog_fdt2="CONFIG_PROG_FDT2"\0" \
536 "bootcmd_net=run set_bootargs; "CONFIG_BOOT_OS_NET"\0" \
537 "bootcmd_flash1=run set_bootargs; " \
538 "bootm "CONFIG_OS1_ENV_ADDR" - "CONFIG_FDT1_ENV_ADDR"\0"\
539 "bootcmd_flash2=run set_bootargs; " \
540 "bootm "CONFIG_OS2_ENV_ADDR" - "CONFIG_FDT2_ENV_ADDR"\0"\
541 "bootcmd=run bootcmd_flash1\0"
542#endif /* __CONFIG_H */