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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Prabhakar Kushwaha9d044fc2016-06-03 18:41:34 +05302/*
3 * Copyright 2016 Freescale Semiconductor, Inc.
Prabhakar Kushwaha9d044fc2016-06-03 18:41:34 +05304 */
5
6#ifndef __LS1012AQDS_H__
7#define __LS1012AQDS_H__
8
9#include "ls1012a_common.h"
10
Shengzhou Liub9e745b2016-08-26 18:30:39 +080011/* DDR */
Prabhakar Kushwaha9d044fc2016-06-03 18:41:34 +053012#define CONFIG_DIMM_SLOTS_PER_CTLR 1
13#define CONFIG_CHIP_SELECTS_PER_CTRL 1
Prabhakar Kushwaha9d044fc2016-06-03 18:41:34 +053014#define CONFIG_SYS_SDRAM_SIZE 0x40000000
Shengzhou Liub9e745b2016-08-26 18:30:39 +080015#define CONFIG_CMD_MEMINFO
Shengzhou Liub9e745b2016-08-26 18:30:39 +080016#define CONFIG_SYS_MEMTEST_START 0x80000000
17#define CONFIG_SYS_MEMTEST_END 0x9fffffff
Prabhakar Kushwaha9d044fc2016-06-03 18:41:34 +053018
Prabhakar Kushwaha9d044fc2016-06-03 18:41:34 +053019/*
20 * QIXIS Definitions
21 */
22#define CONFIG_FSL_QIXIS
23
24#ifdef CONFIG_FSL_QIXIS
25#define CONFIG_QIXIS_I2C_ACCESS
26#define CONFIG_SYS_I2C_FPGA_ADDR 0x66
27#define QIXIS_LBMAP_BRDCFG_REG 0x04
28#define QIXIS_LBMAP_SWITCH 6
Prabhakar Kushwaha3b4dbd32016-07-19 14:05:47 +053029#define QIXIS_LBMAP_MASK 0x08
Prabhakar Kushwaha9d044fc2016-06-03 18:41:34 +053030#define QIXIS_LBMAP_SHIFT 0
31#define QIXIS_LBMAP_DFLTBANK 0x00
32#define QIXIS_LBMAP_ALTBANK 0x08
Prabhakar Kushwaha3b4dbd32016-07-19 14:05:47 +053033#define QIXIS_RST_CTL_RESET 0x31
Prabhakar Kushwaha9d044fc2016-06-03 18:41:34 +053034#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
35#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
36#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
37#endif
38
39/*
40 * I2C bus multiplexer
41 */
42#define I2C_MUX_PCA_ADDR_PRI 0x77
43#define I2C_MUX_PCA_ADDR_SEC 0x76 /* Secondary multiplexer */
44#define I2C_RETIMER_ADDR 0x18
45#define I2C_MUX_CH_DEFAULT 0x8
46#define I2C_MUX_CH_CH7301 0xC
47#define I2C_MUX_CH5 0xD
48#define I2C_MUX_CH7 0xF
49
50#define I2C_MUX_CH_VOL_MONITOR 0xa
51
52/*
53* RTC configuration
54*/
55#define RTC
56#define CONFIG_RTC_PCF8563 1
57#define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/
Prabhakar Kushwaha9d044fc2016-06-03 18:41:34 +053058
59/* EEPROM */
60#define CONFIG_ID_EEPROM
Prabhakar Kushwaha9d044fc2016-06-03 18:41:34 +053061#define CONFIG_SYS_I2C_EEPROM_NXID
62#define CONFIG_SYS_EEPROM_BUS_NUM 0
63#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
64#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
65#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
66#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
67
68
69/* Voltage monitor on channel 2*/
70#define I2C_VOL_MONITOR_ADDR 0x40
71#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
72#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
73#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
74
75/* DSPI */
76#define CONFIG_FSL_DSPI1
77#define CONFIG_DEFAULT_SPI_BUS 1
78
79#define CONFIG_CMD_SPI
80#define MMAP_DSPI DSPI1_BASE_ADDR
81
82#define CONFIG_SYS_DSPI_CTAR0 1
83
84#define CONFIG_SYS_DSPI_CTAR1 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
85 DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
86 DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \
87 DSPI_CTAR_DT(0))
88#define CONFIG_SPI_FLASH_SST /* cs1 */
89
90#define CONFIG_SYS_DSPI_CTAR2 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
91 DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
92 DSPI_CTAR_CSSCK(0) | DSPI_CTAR_ASC(0) | \
93 DSPI_CTAR_DT(0))
94#define CONFIG_SPI_FLASH_STMICRO /* cs2 */
95
96#define CONFIG_SYS_DSPI_CTAR3 (DSPI_CTAR_TRSZ(7) | DSPI_CTAR_PCSSCK_1CLK |\
97 DSPI_CTAR_PASC(0) | DSPI_CTAR_PDT(0) | \
98 DSPI_CTAR_CSSCK(2) | DSPI_CTAR_ASC(0) | \
99 DSPI_CTAR_DT(0))
100#define CONFIG_SPI_FLASH_EON /* cs3 */
101
102#define CONFIG_SF_DEFAULT_SPEED 10000000
103#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
104#define CONFIG_SF_DEFAULT_BUS 1
105#define CONFIG_SF_DEFAULT_CS 0
106
Prabhakar Kushwaha9d044fc2016-06-03 18:41:34 +0530107/* MMC */
Prabhakar Kushwaha9d044fc2016-06-03 18:41:34 +0530108#ifdef CONFIG_MMC
Prabhakar Kushwaha9d044fc2016-06-03 18:41:34 +0530109#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
Prabhakar Kushwaha9d044fc2016-06-03 18:41:34 +0530110#endif
111
Prabhakar Kushwaha9d044fc2016-06-03 18:41:34 +0530112#define CONFIG_PCIE1 /* PCIE controller 1 */
Prabhakar Kushwaha9d044fc2016-06-03 18:41:34 +0530113
Prabhakar Kushwaha9d044fc2016-06-03 18:41:34 +0530114#define CONFIG_PCI_SCAN_SHOW
Prabhakar Kushwaha9d044fc2016-06-03 18:41:34 +0530115
116#define CONFIG_CMD_MEMINFO
Prabhakar Kushwaha9d044fc2016-06-03 18:41:34 +0530117#define CONFIG_SYS_MEMTEST_START 0x80000000
118#define CONFIG_SYS_MEMTEST_END 0x9fffffff
119
Rajesh Bhagate5141cb2018-11-05 18:02:59 +0000120#include <asm/fsl_secure_boot.h>
Prabhakar Kushwaha9d044fc2016-06-03 18:41:34 +0530121#endif /* __LS1012AQDS_H__ */