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wdenkf4675562002-10-02 14:20:15 +00001/*
Wolfgang Denk23c5d252014-10-24 15:31:26 +02002 * (C) Copyright 2000-2014
wdenkf4675562002-10-02 14:20:15 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02005 * SPDX-License-Identifier: GPL-2.0+
wdenkf4675562002-10-02 14:20:15 +00006 */
7
8/*
9 * board/config.h - configuration options, board specific
10 */
11
12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15/*
16 * High Level Configuration Options
17 * (easy to change)
18 */
19
20#define CONFIG_MPC850 1 /* This is a MPC850 CPU */
21#define CONFIG_TQM850L 1 /* ...on a TQM8xxL module */
Wolfgang Denk23c5d252014-10-24 15:31:26 +020022#define CONFIG_DISPLAY_BOARDINFO
wdenkf4675562002-10-02 14:20:15 +000023
Wolfgang Denk2ae18242010-10-06 09:05:45 +020024#define CONFIG_SYS_TEXT_BASE 0x40000000
25
wdenkf4675562002-10-02 14:20:15 +000026#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
Wolfgang Denk3cb7a482009-07-28 22:13:52 +020027#define CONFIG_SYS_SMC_RXBUFLEN 128
28#define CONFIG_SYS_MAXIDLE 10
wdenkf4675562002-10-02 14:20:15 +000029#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */
wdenkf4675562002-10-02 14:20:15 +000030
wdenkae3af052003-08-07 22:18:11 +000031#define CONFIG_BOOTCOUNT_LIMIT
32
33#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
wdenkf4675562002-10-02 14:20:15 +000034
35#define CONFIG_BOARD_TYPES 1 /* support board types */
36
Wolfgang Denk32bf3d12008-03-03 12:16:44 +010037#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
wdenkf4675562002-10-02 14:20:15 +000038
39#undef CONFIG_BOOTARGS
wdenk6aff3112002-12-17 01:51:00 +000040
41#define CONFIG_EXTRA_ENV_SETTINGS \
wdenkae3af052003-08-07 22:18:11 +000042 "netdev=eth0\0" \
wdenk6aff3112002-12-17 01:51:00 +000043 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010044 "nfsroot=${serverip}:${rootpath}\0" \
wdenk6aff3112002-12-17 01:51:00 +000045 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010046 "addip=setenv bootargs ${bootargs} " \
47 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
48 ":${hostname}:${netdev}:off panic=1\0" \
wdenk6aff3112002-12-17 01:51:00 +000049 "flash_nfs=run nfsargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010050 "bootm ${kernel_addr}\0" \
wdenk6aff3112002-12-17 01:51:00 +000051 "flash_self=run ramargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010052 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
53 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
wdenk6aff3112002-12-17 01:51:00 +000054 "rootpath=/opt/eldk/ppc_8xx\0" \
Wolfgang Denk29f8f582008-08-09 23:17:32 +020055 "hostname=TQM850L\0" \
56 "bootfile=TQM850L/uImage\0" \
Wolfgang Denkeb6da802007-09-16 02:39:35 +020057 "fdt_addr=40040000\0" \
58 "kernel_addr=40060000\0" \
59 "ramdisk_addr=40200000\0" \
Wolfgang Denk29f8f582008-08-09 23:17:32 +020060 "u-boot=TQM850L/u-image.bin\0" \
61 "load=tftp 200000 ${u-boot}\0" \
62 "update=prot off 40000000 +${filesize};" \
63 "era 40000000 +${filesize};" \
64 "cp.b 200000 40000000 ${filesize};" \
65 "sete filesize;save\0" \
wdenk6aff3112002-12-17 01:51:00 +000066 ""
67#define CONFIG_BOOTCOMMAND "run flash_self"
wdenkf4675562002-10-02 14:20:15 +000068
69#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020070#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
wdenkf4675562002-10-02 14:20:15 +000071
72#undef CONFIG_WATCHDOG /* watchdog disabled */
73
74#define CONFIG_STATUS_LED 1 /* Status LED enabled */
75
76#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
77
Jon Loeliger37d4bb72007-07-09 21:38:02 -050078/*
79 * BOOTP options
80 */
81#define CONFIG_BOOTP_SUBNETMASK
82#define CONFIG_BOOTP_GATEWAY
83#define CONFIG_BOOTP_HOSTNAME
84#define CONFIG_BOOTP_BOOTPATH
85#define CONFIG_BOOTP_BOOTFILESIZE
86
wdenkf4675562002-10-02 14:20:15 +000087
88#define CONFIG_MAC_PARTITION
89#define CONFIG_DOS_PARTITION
90
91#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
92
Jon Loeliger26946902007-07-04 22:30:50 -050093/*
94 * Command line configuration.
95 */
Jon Loeliger26946902007-07-04 22:30:50 -050096#define CONFIG_CMD_ASKENV
97#define CONFIG_CMD_DATE
98#define CONFIG_CMD_DHCP
Wolfgang Denk9a63b7f2009-02-21 21:51:21 +010099#define CONFIG_CMD_EXT2
Jon Loeliger26946902007-07-04 22:30:50 -0500100#define CONFIG_CMD_IDE
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200101#define CONFIG_CMD_JFFS2
Jon Loeliger26946902007-07-04 22:30:50 -0500102#define CONFIG_CMD_SNTP
103
wdenkf4675562002-10-02 14:20:15 +0000104
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200105#define CONFIG_NETCONSOLE
106
wdenkf4675562002-10-02 14:20:15 +0000107/*
108 * Miscellaneous configurable options
109 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200110#define CONFIG_SYS_LONGHELP /* undef to save memory */
wdenk6aff3112002-12-17 01:51:00 +0000111
Wolfgang Denk2751a952006-10-28 02:29:14 +0200112#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200113#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
wdenk6aff3112002-12-17 01:51:00 +0000114
Jon Loeliger26946902007-07-04 22:30:50 -0500115#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200116#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenkf4675562002-10-02 14:20:15 +0000117#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200118#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenkf4675562002-10-02 14:20:15 +0000119#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200120#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
121#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
122#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenkf4675562002-10-02 14:20:15 +0000123
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200124#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
125#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
wdenkf4675562002-10-02 14:20:15 +0000126
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200127#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenkf4675562002-10-02 14:20:15 +0000128
wdenkf4675562002-10-02 14:20:15 +0000129/*
130 * Low Level Configuration Settings
131 * (address mappings, register initial values, etc.)
132 * You should know what you are doing if you make changes here.
133 */
134/*-----------------------------------------------------------------------
135 * Internal Memory Mapped Register
136 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200137#define CONFIG_SYS_IMMR 0xFFF00000
wdenkf4675562002-10-02 14:20:15 +0000138
139/*-----------------------------------------------------------------------
140 * Definitions for initial stack pointer and data area (in DPRAM)
141 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200142#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk553f0982010-10-26 13:32:32 +0200143#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200144#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200145#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkf4675562002-10-02 14:20:15 +0000146
147/*-----------------------------------------------------------------------
148 * Start addresses for the final memory configuration
149 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200150 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenkf4675562002-10-02 14:20:15 +0000151 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200152#define CONFIG_SYS_SDRAM_BASE 0x00000000
153#define CONFIG_SYS_FLASH_BASE 0x40000000
154#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
155#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
156#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenkf4675562002-10-02 14:20:15 +0000157
158/*
159 * For booting Linux, the board info and command line data
160 * have to be in the first 8 MB of memory, since this is
161 * the maximum mapped by the Linux kernel during initialization.
162 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200163#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkf4675562002-10-02 14:20:15 +0000164
165/*-----------------------------------------------------------------------
166 * FLASH organization
167 */
wdenkf4675562002-10-02 14:20:15 +0000168
Martin Krausee318d9e2007-09-27 11:10:08 +0200169/* use CFI flash driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200170#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200171#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200172#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size }
173#define CONFIG_SYS_FLASH_EMPTY_INFO
174#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
175#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
176#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */
wdenkf4675562002-10-02 14:20:15 +0000177
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200178#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200179#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
180#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
wdenkf4675562002-10-02 14:20:15 +0000181
182/* Address and size of Redundant Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200183#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
184#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
wdenkf4675562002-10-02 14:20:15 +0000185
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200186#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
Wolfgang Denk67c31032007-09-16 17:10:04 +0200187
Wolfgang Denk7c803be2008-09-16 18:02:19 +0200188#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */
189
wdenkf4675562002-10-02 14:20:15 +0000190/*-----------------------------------------------------------------------
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200191 * Dynamic MTD partition support
192 */
Stefan Roese68d7d652009-03-19 13:30:36 +0100193#define CONFIG_CMD_MTDPARTS
Stefan Roese942556a2009-05-12 14:32:58 +0200194#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
195#define CONFIG_FLASH_CFI_MTD
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200196#define MTDIDS_DEFAULT "nor0=TQM8xxL-0"
197
198#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \
199 "128k(dtb)," \
200 "1664k(kernel)," \
201 "2m(rootfs)," \
Wolfgang Denkcd829192008-08-12 16:08:38 +0200202 "4m(data)"
Wolfgang Denk29f8f582008-08-09 23:17:32 +0200203
204/*-----------------------------------------------------------------------
wdenkf4675562002-10-02 14:20:15 +0000205 * Hardware Information Block
206 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200207#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
208#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
209#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
wdenkf4675562002-10-02 14:20:15 +0000210
211/*-----------------------------------------------------------------------
212 * Cache Configuration
213 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200214#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeliger26946902007-07-04 22:30:50 -0500215#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200216#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
wdenkf4675562002-10-02 14:20:15 +0000217#endif
218
219/*-----------------------------------------------------------------------
220 * SYPCR - System Protection Control 11-9
221 * SYPCR can only be written once after reset!
222 *-----------------------------------------------------------------------
223 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
224 */
225#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200226#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
wdenkf4675562002-10-02 14:20:15 +0000227 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
228#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200229#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
wdenkf4675562002-10-02 14:20:15 +0000230#endif
231
232/*-----------------------------------------------------------------------
233 * SIUMCR - SIU Module Configuration 11-6
234 *-----------------------------------------------------------------------
235 * PCMCIA config., multi-function pin tri-state
236 */
237#ifndef CONFIG_CAN_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200238#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
wdenkf4675562002-10-02 14:20:15 +0000239#else /* we must activate GPL5 in the SIUMCR for CAN */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200240#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
wdenkf4675562002-10-02 14:20:15 +0000241#endif /* CONFIG_CAN_DRIVER */
242
243/*-----------------------------------------------------------------------
244 * TBSCR - Time Base Status and Control 11-26
245 *-----------------------------------------------------------------------
246 * Clear Reference Interrupt Status, Timebase freezing enabled
247 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200248#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
wdenkf4675562002-10-02 14:20:15 +0000249
250/*-----------------------------------------------------------------------
251 * RTCSC - Real-Time Clock Status and Control Register 11-27
252 *-----------------------------------------------------------------------
253 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200254#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
wdenkf4675562002-10-02 14:20:15 +0000255
256/*-----------------------------------------------------------------------
257 * PISCR - Periodic Interrupt Status and Control 11-31
258 *-----------------------------------------------------------------------
259 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
260 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200261#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
wdenkf4675562002-10-02 14:20:15 +0000262
263/*-----------------------------------------------------------------------
264 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
265 *-----------------------------------------------------------------------
266 * Reset PLL lock status sticky bit, timer expired status bit and timer
267 * interrupt status bit
wdenkf4675562002-10-02 14:20:15 +0000268 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200269#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
wdenkf4675562002-10-02 14:20:15 +0000270
271/*-----------------------------------------------------------------------
272 * SCCR - System Clock and reset Control Register 15-27
273 *-----------------------------------------------------------------------
274 * Set clock output, timebase and RTC source and divider,
275 * power management and some other internal clocks
276 */
277#define SCCR_MASK SCCR_EBDF11
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200278#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
wdenkf4675562002-10-02 14:20:15 +0000279 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
280 SCCR_DFALCD00)
wdenkf4675562002-10-02 14:20:15 +0000281
282/*-----------------------------------------------------------------------
283 * PCMCIA stuff
284 *-----------------------------------------------------------------------
285 *
286 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200287#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
288#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
289#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
290#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
291#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
292#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
293#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
294#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
wdenkf4675562002-10-02 14:20:15 +0000295
296/*-----------------------------------------------------------------------
297 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
298 *-----------------------------------------------------------------------
299 */
300
Pavel Herrmann8d1165e11a2012-10-09 07:01:56 +0000301#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */
wdenkf4675562002-10-02 14:20:15 +0000302#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */
303
304#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
305#undef CONFIG_IDE_LED /* LED for ide not supported */
306#undef CONFIG_IDE_RESET /* reset for ide not supported */
307
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200308#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
309#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
wdenkf4675562002-10-02 14:20:15 +0000310
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200311#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
wdenkf4675562002-10-02 14:20:15 +0000312
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200313#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
wdenkf4675562002-10-02 14:20:15 +0000314
315/* Offset for data I/O */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200316#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenkf4675562002-10-02 14:20:15 +0000317
318/* Offset for normal register accesses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200319#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
wdenkf4675562002-10-02 14:20:15 +0000320
321/* Offset for alternate registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200322#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
wdenkf4675562002-10-02 14:20:15 +0000323
wdenkf4675562002-10-02 14:20:15 +0000324/*-----------------------------------------------------------------------
325 *
326 *-----------------------------------------------------------------------
327 *
328 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200329#define CONFIG_SYS_DER 0
wdenkf4675562002-10-02 14:20:15 +0000330
331/*
332 * Init Memory Controller:
333 *
334 * BR0/1 and OR0/1 (FLASH)
335 */
336
337#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
338#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
339
340/* used to re-map FLASH both when starting from SRAM or FLASH:
341 * restrict access enough to keep SRAM working (if any)
342 * but not too much to meddle with FLASH accesses
343 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200344#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
345#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
wdenkf4675562002-10-02 14:20:15 +0000346
347/*
348 * FLASH timing:
349 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200350#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \
wdenkf4675562002-10-02 14:20:15 +0000351 OR_SCY_3_CLK | OR_EHTR | OR_BI)
wdenkf4675562002-10-02 14:20:15 +0000352
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200353#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
354#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
355#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
wdenkf4675562002-10-02 14:20:15 +0000356
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200357#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
358#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
359#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
wdenkf4675562002-10-02 14:20:15 +0000360
361/*
362 * BR2/3 and OR2/3 (SDRAM)
363 *
364 */
365#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */
366#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */
367#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */
368
369/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200370#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
wdenkf4675562002-10-02 14:20:15 +0000371
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200372#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
373#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
wdenkf4675562002-10-02 14:20:15 +0000374
375#ifndef CONFIG_CAN_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200376#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM
377#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
wdenkf4675562002-10-02 14:20:15 +0000378#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200379#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */
380#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */
381#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI)
382#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \
wdenkf4675562002-10-02 14:20:15 +0000383 BR_PS_8 | BR_MS_UPMB | BR_V )
384#endif /* CONFIG_CAN_DRIVER */
385
386/*
387 * Memory Periodic Timer Prescaler
388 *
389 * The Divider for PTA (refresh timer) configuration is based on an
390 * example SDRAM configuration (64 MBit, one bank). The adjustment to
391 * the number of chip selects (NCS) and the actually needed refresh
392 * rate is done by setting MPTPR.
393 *
394 * PTA is calculated from
395 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
396 *
397 * gclk CPU clock (not bus clock!)
398 * Trefresh Refresh cycle * 4 (four word bursts used)
399 *
400 * 4096 Rows from SDRAM example configuration
401 * 1000 factor s -> ms
402 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
403 * 4 Number of refresh cycles per period
404 * 64 Refresh cycle in ms per number of rows
405 * --------------------------------------------
406 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
407 *
408 * 50 MHz => 50.000.000 / Divider = 98
409 * 66 Mhz => 66.000.000 / Divider = 129
410 * 80 Mhz => 80.000.000 / Divider = 156
411 */
wdenke9132ea2004-04-24 23:23:30 +0000412
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200413#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
414#define CONFIG_SYS_MAMR_PTA 98
wdenkf4675562002-10-02 14:20:15 +0000415
416/*
417 * For 16 MBit, refresh rates could be 31.3 us
418 * (= 64 ms / 2K = 125 / quad bursts).
419 * For a simpler initialization, 15.6 us is used instead.
420 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200421 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
422 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
wdenkf4675562002-10-02 14:20:15 +0000423 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200424#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
425#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
wdenkf4675562002-10-02 14:20:15 +0000426
427/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200428#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
429#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
wdenkf4675562002-10-02 14:20:15 +0000430
431/*
432 * MAMR settings for SDRAM
433 */
434
435/* 8 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200436#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenkf4675562002-10-02 14:20:15 +0000437 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
438 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
439/* 9 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200440#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenkf4675562002-10-02 14:20:15 +0000441 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
442 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
443
Heiko Schocher7026ead2010-02-09 15:50:27 +0100444/* pass open firmware flat tree */
445#define CONFIG_OF_LIBFDT 1
446#define CONFIG_OF_BOARD_SETUP 1
447#define CONFIG_HWCONFIG 1
448
wdenkf4675562002-10-02 14:20:15 +0000449#endif /* __CONFIG_H */