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Holger Brunck0f2b7212012-03-21 13:42:46 +01001/*
2 * (C) Copyright 2012
3 * Holger Brunck, Keymile GmbH Hannover, <holger.brunck@keymile.com>
4 * Christian Herzig, Keymile AG Switzerland, <christian.herzig@keymile.com>
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Holger Brunck0f2b7212012-03-21 13:42:46 +01007 */
8
9#ifndef __CONFIG_H
10#define __CONFIG_H
11
Kim Phillipsfdfaa292015-03-17 12:00:45 -050012#define CONFIG_DISPLAY_BOARDINFO
13
Holger Brunck0f2b7212012-03-21 13:42:46 +010014/* KMBEC FPGA (PRIO) */
15#define CONFIG_SYS_KMBEC_FPGA_BASE 0xE8000000
16#define CONFIG_SYS_KMBEC_FPGA_SIZE 64
17
18#if defined CONFIG_KMETER1
19#define CONFIG_HOSTNAME kmeter1
20#define CONFIG_KM_BOARD_NAME "kmeter1"
21#define CONFIG_KM_DEF_NETDEV "netdev=eth2\0"
22#elif defined CONFIG_KMCOGE5NE
23#define CONFIG_HOSTNAME kmcoge5ne
24#define CONFIG_KM_BOARD_NAME "kmcoge5ne"
25#define CONFIG_KM_DEF_NETDEV "netdev=eth1\0"
26#define CONFIG_CMD_NAND
Holger Brunckbe7576f2013-01-21 03:55:23 +000027#define CONFIG_NAND_ECC_BCH
28#define CONFIG_BCH
Holger Brunck0f2b7212012-03-21 13:42:46 +010029#define CONFIG_NAND_KMETER1
30#define CONFIG_SYS_MAX_NAND_DEVICE 1
31#define NAND_MAX_CHIPS 1
32#define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */
33
34#define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0"
35#define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1"
36#define MTDIDS_DEFAULT "nor0=boot,nand0=app"
37
38#define MTDPARTS_DEFAULT "mtdparts=" \
39 "boot:" \
40 "768k(u-boot)," \
41 "128k(env)," \
42 "128k(envred)," \
43 "-(" CONFIG_KM_UBI_PARTITION_NAME_BOOT ");" \
44 "app:" \
45 "-(" CONFIG_KM_UBI_PARTITION_NAME_APP ");"
46#else
47#error ("Board not supported")
48#endif
49
50/*
51 * High Level Configuration Options
52 */
53#define CONFIG_QE /* Has QE */
54#define CONFIG_MPC8360 /* MPC8360 CPU specific */
55
56#define CONFIG_SYS_TEXT_BASE 0xF0000000
57
58/* include common defines/options for all 83xx Keymile boards */
59#include "km/km83xx-common.h"
60
61/*
62 * System IO Setup
63 */
64#define CONFIG_SYS_SICRH (SICRH_UC1EOBI | SICRH_UC2E1OBI)
65
66/*
67 * Hardware Reset Configuration Word
68 */
69#define CONFIG_SYS_HRCW_LOW (\
70 HRCWL_CSB_TO_CLKIN_4X1 | \
71 HRCWL_CORE_TO_CSB_2X1 | \
72 HRCWL_CE_PLL_VCO_DIV_2 | \
73 HRCWL_CE_TO_PLL_1X6)
74
75#define CONFIG_SYS_HRCW_HIGH (\
76 HRCWH_CORE_ENABLE | \
77 HRCWH_FROM_0X00000100 | \
78 HRCWH_BOOTSEQ_DISABLE | \
79 HRCWH_SW_WATCHDOG_DISABLE | \
80 HRCWH_ROM_LOC_LOCAL_16BIT | \
81 HRCWH_BIG_ENDIAN | \
82 HRCWH_LALE_EARLY | \
83 HRCWH_LDP_CLEAR)
84
85/**
86 * DDR RAM settings
87 */
88#define CONFIG_SYS_DDR_SDRAM_CFG (\
89 SDRAM_CFG_SDRAM_TYPE_DDR2 | \
90 SDRAM_CFG_SREN | \
91 SDRAM_CFG_HSE)
92
93#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000
94
95#ifdef CONFIG_KMCOGE5NE
96/**
97 * KMCOGE5NE has 512 MB RAM
98 */
99#define CONFIG_SYS_DDR_CS0_CONFIG (\
100 CSCONFIG_EN | \
101 CSCONFIG_AP | \
Valentin Longchamp22554ba2015-11-17 10:53:33 +0100102 CSCONFIG_ODT_WR_ONLY_CURRENT | \
Holger Brunck0f2b7212012-03-21 13:42:46 +0100103 CSCONFIG_BANK_BIT_3 | \
104 CSCONFIG_ROW_BIT_13 | \
105 CSCONFIG_COL_BIT_10)
106#else
107#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_AP | \
108 CSCONFIG_ROW_BIT_13 | \
109 CSCONFIG_COL_BIT_10 | \
Valentin Longchamp22554ba2015-11-17 10:53:33 +0100110 CSCONFIG_ODT_WR_ONLY_CURRENT)
Holger Brunck0f2b7212012-03-21 13:42:46 +0100111#endif
112
113#define CONFIG_SYS_DDR_CLK_CNTL (\
114 DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
115
116#define CONFIG_SYS_DDR_INTERVAL (\
117 (0x080 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
118 (0x203 << SDRAM_INTERVAL_REFINT_SHIFT))
119
120#define CONFIG_SYS_DDR_CS0_BNDS 0x0000007f
121
122#define CONFIG_SYS_DDRCDR (\
123 DDRCDR_EN | \
124 DDRCDR_Q_DRN)
125#define CONFIG_SYS_DDR_MODE 0x47860452
126#define CONFIG_SYS_DDR_MODE2 0x8080c000
127
128#define CONFIG_SYS_DDR_TIMING_0 (\
129 (2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
130 (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
131 (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
132 (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
133 (0 << TIMING_CFG0_WWT_SHIFT) | \
134 (0 << TIMING_CFG0_RRT_SHIFT) | \
135 (0 << TIMING_CFG0_WRT_SHIFT) | \
136 (0 << TIMING_CFG0_RWT_SHIFT))
137
138#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \
139 (2 << TIMING_CFG1_WRTORD_SHIFT) | \
140 (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
141 (3 << TIMING_CFG1_WRREC_SHIFT) | \
142 (7 << TIMING_CFG1_REFREC_SHIFT) | \
143 (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
144 (8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
145 (3 << TIMING_CFG1_PRETOACT_SHIFT))
146
147#define CONFIG_SYS_DDR_TIMING_2 (\
148 (0xa << TIMING_CFG2_FOUR_ACT_SHIFT) | \
149 (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
150 (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
151 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
152 (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
153 (5 << TIMING_CFG2_CPO_SHIFT) | \
154 (0 << TIMING_CFG2_ADD_LAT_SHIFT))
155
156#define CONFIG_SYS_DDR_TIMING_3 0x00000000
157
158/* EEprom support */
159#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
160
161/*
162 * Local Bus Configuration & Clock Setup
163 */
164#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
165#define CONFIG_SYS_LCRR_EADC LCRR_EADC_2
166#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
167
168/*
169 * PAXE on the local bus CS3
170 */
171#define CONFIG_SYS_PAXE_BASE 0xA0000000
172#define CONFIG_SYS_PAXE_SIZE 256
173
174#define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_PAXE_BASE
175
176#define CONFIG_SYS_LBLAWAR3_PRELIM 0x8000001C /* 512MB window size */
177
178#define CONFIG_SYS_BR3_PRELIM (\
179 CONFIG_SYS_PAXE_BASE | \
180 (1 << BR_PS_SHIFT) | \
181 BR_V)
182
183#define CONFIG_SYS_OR3_PRELIM (\
184 MEG_TO_AM(CONFIG_SYS_PAXE_SIZE) | \
185 OR_GPCM_CSNT | \
186 OR_GPCM_ACS_DIV2 | \
187 OR_GPCM_SCY_2 | \
188 OR_GPCM_TRLX | \
189 OR_GPCM_EAD)
190
191#ifdef CONFIG_KMCOGE5NE
192/*
193 * BFTIC3 on the local bus CS4
194 */
195#define CONFIG_SYS_BFTIC3_BASE 0xB0000000
196#define CONFIG_SYS_BFTIC3_SIZE 256
197
198#define CONFIG_SYS_BR4_PRELIM (\
199 CONFIG_SYS_BFTIC3_BASE |\
200 (1 << BR_PS_SHIFT) | \
201 BR_V)
202
203#define CONFIG_SYS_OR4_PRELIM (\
204 MEG_TO_AM(CONFIG_SYS_BFTIC3_SIZE) |\
205 OR_GPCM_CSNT | \
206 OR_GPCM_ACS_DIV2 |\
207 OR_GPCM_SCY_2 |\
208 OR_GPCM_TRLX |\
209 OR_GPCM_EAD)
210#endif
211
212/*
213 * MMU Setup
214 */
215
216/* PAXE: icache cacheable, but dcache-inhibit and guarded */
217#define CONFIG_SYS_IBAT5L (\
218 CONFIG_SYS_PAXE_BASE | \
219 BATL_PP_10 | \
220 BATL_MEMCOHERENCE)
221
222#define CONFIG_SYS_IBAT5U (\
223 CONFIG_SYS_PAXE_BASE | \
224 BATU_BL_256M | \
225 BATU_VS | \
226 BATU_VP)
227
228#define CONFIG_SYS_DBAT5L (\
229 CONFIG_SYS_PAXE_BASE | \
230 BATL_PP_10 | \
231 BATL_CACHEINHIBIT | \
232 BATL_GUARDEDSTORAGE)
233
234#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
235
236
237#ifdef CONFIG_KMCOGE5NE
238/* BFTIC3: icache cacheable, but dcache-inhibit and guarded */
239#define CONFIG_SYS_IBAT6L (\
240 CONFIG_SYS_BFTIC3_BASE | \
241 BATL_PP_10 | \
242 BATL_MEMCOHERENCE)
243
244#define CONFIG_SYS_IBAT6U (\
245 CONFIG_SYS_BFTIC3_BASE | \
246 BATU_BL_256M | \
247 BATU_VS | \
248 BATU_VP)
249
250#define CONFIG_SYS_DBAT6L (\
251 CONFIG_SYS_BFTIC3_BASE | \
252 BATL_PP_10 | \
253 BATL_CACHEINHIBIT | \
254 BATL_GUARDEDSTORAGE)
255
256#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
257
258/* DDR/LBC SDRAM next 256M: cacheable */
259#define CONFIG_SYS_IBAT7L (\
260 CONFIG_SYS_SDRAM_BASE2 |\
261 BATL_PP_10 |\
262 BATL_CACHEINHIBIT |\
263 BATL_GUARDEDSTORAGE)
264
265#define CONFIG_SYS_IBAT7U (\
266 CONFIG_SYS_SDRAM_BASE2 |\
267 BATU_BL_256M |\
268 BATU_VS |\
269 BATU_VP)
Thomas Herzmann95209b62012-05-04 10:55:56 +0200270/* enable POST tests */
271#define CONFIG_POST (CONFIG_SYS_POST_MEMORY|CONFIG_SYS_POST_MEM_REGIONS)
272#define CONFIG_POST_EXTERNAL_WORD_FUNCS /* use own functions, not generic */
273#define CPM_POST_WORD_ADDR CONFIG_SYS_MEMTEST_END
274#define CONFIG_TESTPIN_REG gprt3 /* for kmcoge5ne */
275#define CONFIG_TESTPIN_MASK 0x20 /* for kmcoge5ne */
276#define CONFIG_CMD_DIAG /* so that testpin is inquired for POST test */
277
Holger Brunck0f2b7212012-03-21 13:42:46 +0100278#else
279#define CONFIG_SYS_IBAT6L (0)
280#define CONFIG_SYS_IBAT6U (0)
281#define CONFIG_SYS_IBAT7L (0)
282#define CONFIG_SYS_IBAT7U (0)
283#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
284#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
285#endif
286
287#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
288#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
289
290#endif /* CONFIG */