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wdenkc6097192002-11-03 00:24:07 +00001/*
2 * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
3 * Andreas Heppel <aheppel@sysgo.de>
4 *
wdenkf07771c2003-05-28 08:06:31 +00005 * (C) Copyright 2002, 2003
wdenkc6097192002-11-03 00:24:07 +00006 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02008 * SPDX-License-Identifier: GPL-2.0+
wdenkc6097192002-11-03 00:24:07 +00009 */
10
11/*
Simon Glass2b81e8a2015-11-29 13:17:46 -070012 * Old PCI routines
13 *
14 * Do not change this file. Instead, convert your board to use CONFIG_DM_PCI
15 * and change pci-uclass.c.
wdenkc6097192002-11-03 00:24:07 +000016 */
17
18#include <common.h>
19
wdenkc6097192002-11-03 00:24:07 +000020#include <command.h>
Simon Glass250e0392015-01-27 22:13:27 -070021#include <errno.h>
wdenkc6097192002-11-03 00:24:07 +000022#include <asm/processor.h>
23#include <asm/io.h>
24#include <pci.h>
25
Bin Meng8f9052f2014-12-30 22:53:21 +080026DECLARE_GLOBAL_DATA_PTR;
27
wdenkf07771c2003-05-28 08:06:31 +000028#define PCI_HOSE_OP(rw, size, type) \
Wolfgang Denk53677ef2008-05-20 16:00:29 +020029int pci_hose_##rw##_config_##size(struct pci_controller *hose, \
30 pci_dev_t dev, \
wdenkf07771c2003-05-28 08:06:31 +000031 int offset, type value) \
32{ \
33 return hose->rw##_##size(hose, dev, offset, value); \
wdenkc6097192002-11-03 00:24:07 +000034}
35
36PCI_HOSE_OP(read, byte, u8 *)
37PCI_HOSE_OP(read, word, u16 *)
38PCI_HOSE_OP(read, dword, u32 *)
39PCI_HOSE_OP(write, byte, u8)
40PCI_HOSE_OP(write, word, u16)
41PCI_HOSE_OP(write, dword, u32)
42
wdenkf07771c2003-05-28 08:06:31 +000043#define PCI_OP(rw, size, type, error_code) \
44int pci_##rw##_config_##size(pci_dev_t dev, int offset, type value) \
45{ \
46 struct pci_controller *hose = pci_bus_to_hose(PCI_BUS(dev)); \
47 \
48 if (!hose) \
49 { \
50 error_code; \
51 return -1; \
52 } \
53 \
54 return pci_hose_##rw##_config_##size(hose, dev, offset, value); \
wdenkc6097192002-11-03 00:24:07 +000055}
56
57PCI_OP(read, byte, u8 *, *value = 0xff)
58PCI_OP(read, word, u16 *, *value = 0xffff)
59PCI_OP(read, dword, u32 *, *value = 0xffffffff)
60PCI_OP(write, byte, u8, )
61PCI_OP(write, word, u16, )
62PCI_OP(write, dword, u32, )
63
wdenkf07771c2003-05-28 08:06:31 +000064#define PCI_READ_VIA_DWORD_OP(size, type, off_mask) \
65int pci_hose_read_config_##size##_via_dword(struct pci_controller *hose,\
Wolfgang Denk53677ef2008-05-20 16:00:29 +020066 pci_dev_t dev, \
wdenkf07771c2003-05-28 08:06:31 +000067 int offset, type val) \
68{ \
69 u32 val32; \
70 \
Shinya Kuribayashi815b5bd2007-08-17 12:43:44 +090071 if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0) { \
72 *val = -1; \
wdenkf07771c2003-05-28 08:06:31 +000073 return -1; \
Shinya Kuribayashi815b5bd2007-08-17 12:43:44 +090074 } \
wdenkf07771c2003-05-28 08:06:31 +000075 \
76 *val = (val32 >> ((offset & (int)off_mask) * 8)); \
77 \
78 return 0; \
wdenkc6097192002-11-03 00:24:07 +000079}
80
wdenkf07771c2003-05-28 08:06:31 +000081#define PCI_WRITE_VIA_DWORD_OP(size, type, off_mask, val_mask) \
82int pci_hose_write_config_##size##_via_dword(struct pci_controller *hose,\
Wolfgang Denk53677ef2008-05-20 16:00:29 +020083 pci_dev_t dev, \
wdenkf07771c2003-05-28 08:06:31 +000084 int offset, type val) \
85{ \
wdenk498b8db2004-04-18 22:26:17 +000086 u32 val32, mask, ldata, shift; \
wdenkf07771c2003-05-28 08:06:31 +000087 \
88 if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0)\
89 return -1; \
90 \
wdenk498b8db2004-04-18 22:26:17 +000091 shift = ((offset & (int)off_mask) * 8); \
92 ldata = (((unsigned long)val) & val_mask) << shift; \
93 mask = val_mask << shift; \
wdenkf07771c2003-05-28 08:06:31 +000094 val32 = (val32 & ~mask) | ldata; \
95 \
96 if (pci_hose_write_config_dword(hose, dev, offset & 0xfc, val32) < 0)\
97 return -1; \
98 \
99 return 0; \
wdenkc6097192002-11-03 00:24:07 +0000100}
101
102PCI_READ_VIA_DWORD_OP(byte, u8 *, 0x03)
103PCI_READ_VIA_DWORD_OP(word, u16 *, 0x02)
104PCI_WRITE_VIA_DWORD_OP(byte, u8, 0x03, 0x000000ff)
105PCI_WRITE_VIA_DWORD_OP(word, u16, 0x02, 0x0000ffff)
106
107/*
108 *
109 */
110
John Schmoller96d61602010-10-22 00:20:23 -0500111static struct pci_controller* hose_head;
wdenkc6097192002-11-03 00:24:07 +0000112
Bin Meng8f9052f2014-12-30 22:53:21 +0800113struct pci_controller *pci_get_hose_head(void)
114{
115 if (gd->hose)
116 return gd->hose;
117
118 return hose_head;
119}
120
wdenkc6097192002-11-03 00:24:07 +0000121void pci_register_hose(struct pci_controller* hose)
122{
123 struct pci_controller **phose = &hose_head;
124
125 while(*phose)
126 phose = &(*phose)->next;
127
128 hose->next = NULL;
129
130 *phose = hose;
131}
132
Andrew Sharpcb2bf932012-08-29 14:16:29 +0000133struct pci_controller *pci_bus_to_hose(int bus)
wdenkc6097192002-11-03 00:24:07 +0000134{
135 struct pci_controller *hose;
136
Bin Meng8f9052f2014-12-30 22:53:21 +0800137 for (hose = pci_get_hose_head(); hose; hose = hose->next) {
wdenkf07771c2003-05-28 08:06:31 +0000138 if (bus >= hose->first_busno && bus <= hose->last_busno)
wdenkc6097192002-11-03 00:24:07 +0000139 return hose;
Andrew Sharpcb2bf932012-08-29 14:16:29 +0000140 }
wdenkc6097192002-11-03 00:24:07 +0000141
Rafal Jaworowski6902df52005-10-17 02:39:53 +0200142 printf("pci_bus_to_hose() failed\n");
wdenkc6097192002-11-03 00:24:07 +0000143 return NULL;
144}
145
Kumar Gala3a0e3c22010-12-17 05:57:25 -0600146struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr)
147{
148 struct pci_controller *hose;
149
Bin Meng8f9052f2014-12-30 22:53:21 +0800150 for (hose = pci_get_hose_head(); hose; hose = hose->next) {
Kumar Gala3a0e3c22010-12-17 05:57:25 -0600151 if (hose->cfg_addr == cfg_addr)
152 return hose;
153 }
154
155 return NULL;
156}
157
Anton Vorontsovcc2a8c72009-02-19 18:20:41 +0300158int pci_last_busno(void)
159{
Bin Meng8f9052f2014-12-30 22:53:21 +0800160 struct pci_controller *hose = pci_get_hose_head();
Anton Vorontsovcc2a8c72009-02-19 18:20:41 +0300161
162 if (!hose)
163 return -1;
164
165 while (hose->next)
166 hose = hose->next;
167
168 return hose->last_busno;
169}
170
wdenkc6097192002-11-03 00:24:07 +0000171pci_dev_t pci_find_devices(struct pci_device_id *ids, int index)
172{
173 struct pci_controller * hose;
wdenkc6097192002-11-03 00:24:07 +0000174 pci_dev_t bdf;
Simon Glassaab67242015-03-05 12:25:24 -0700175 int bus;
wdenkc6097192002-11-03 00:24:07 +0000176
Bin Meng8f9052f2014-12-30 22:53:21 +0800177 for (hose = pci_get_hose_head(); hose; hose = hose->next) {
Simon Glassaab67242015-03-05 12:25:24 -0700178 for (bus = hose->first_busno; bus <= hose->last_busno; bus++) {
Simon Glassaab67242015-03-05 12:25:24 -0700179 bdf = pci_hose_find_devices(hose, bus, ids, &index);
180 if (bdf != -1)
Simon Glass250e0392015-01-27 22:13:27 -0700181 return bdf;
Simon Glass250e0392015-01-27 22:13:27 -0700182 }
183 }
184
Simon Glassaab67242015-03-05 12:25:24 -0700185 return -1;
wdenkc6097192002-11-03 00:24:07 +0000186}
187
wdenkc6097192002-11-03 00:24:07 +0000188int pci_hose_config_device(struct pci_controller *hose,
189 pci_dev_t dev,
190 unsigned long io,
Kumar Gala30e76d52008-10-21 08:36:08 -0500191 pci_addr_t mem,
wdenkc6097192002-11-03 00:24:07 +0000192 unsigned long command)
193{
Kumar Galacf5787f2012-09-19 04:47:36 +0000194 u32 bar_response;
Andrew Sharpaf778c62012-08-01 12:27:16 +0000195 unsigned int old_command;
Kumar Gala30e76d52008-10-21 08:36:08 -0500196 pci_addr_t bar_value;
197 pci_size_t bar_size;
wdenkc6097192002-11-03 00:24:07 +0000198 unsigned char pin;
199 int bar, found_mem64;
200
Andrew Sharpcb2bf932012-08-29 14:16:29 +0000201 debug("PCI Config: I/O=0x%lx, Memory=0x%llx, Command=0x%lx\n", io,
202 (u64)mem, command);
wdenkc6097192002-11-03 00:24:07 +0000203
Andrew Sharpcb2bf932012-08-29 14:16:29 +0000204 pci_hose_write_config_dword(hose, dev, PCI_COMMAND, 0);
wdenkc6097192002-11-03 00:24:07 +0000205
Wolfgang Denk252b4042010-03-09 14:27:25 +0100206 for (bar = PCI_BASE_ADDRESS_0; bar <= PCI_BASE_ADDRESS_5; bar += 4) {
Andrew Sharpcb2bf932012-08-29 14:16:29 +0000207 pci_hose_write_config_dword(hose, dev, bar, 0xffffffff);
208 pci_hose_read_config_dword(hose, dev, bar, &bar_response);
wdenkc6097192002-11-03 00:24:07 +0000209
210 if (!bar_response)
211 continue;
212
213 found_mem64 = 0;
214
215 /* Check the BAR type and set our address mask */
wdenkf07771c2003-05-28 08:06:31 +0000216 if (bar_response & PCI_BASE_ADDRESS_SPACE) {
wdenkc6097192002-11-03 00:24:07 +0000217 bar_size = ~(bar_response & PCI_BASE_ADDRESS_IO_MASK) + 1;
wdenkf07771c2003-05-28 08:06:31 +0000218 /* round up region base address to a multiple of size */
wdenkc6097192002-11-03 00:24:07 +0000219 io = ((io - 1) | (bar_size - 1)) + 1;
wdenkf07771c2003-05-28 08:06:31 +0000220 bar_value = io;
221 /* compute new region base address */
222 io = io + bar_size;
223 } else {
224 if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
Kumar Gala30e76d52008-10-21 08:36:08 -0500225 PCI_BASE_ADDRESS_MEM_TYPE_64) {
226 u32 bar_response_upper;
227 u64 bar64;
Andrew Sharpcb2bf932012-08-29 14:16:29 +0000228 pci_hose_write_config_dword(hose, dev, bar + 4,
229 0xffffffff);
230 pci_hose_read_config_dword(hose, dev, bar + 4,
231 &bar_response_upper);
wdenkc6097192002-11-03 00:24:07 +0000232
Kumar Gala30e76d52008-10-21 08:36:08 -0500233 bar64 = ((u64)bar_response_upper << 32) | bar_response;
234
235 bar_size = ~(bar64 & PCI_BASE_ADDRESS_MEM_MASK) + 1;
236 found_mem64 = 1;
237 } else {
238 bar_size = (u32)(~(bar_response & PCI_BASE_ADDRESS_MEM_MASK) + 1);
239 }
wdenkc6097192002-11-03 00:24:07 +0000240
wdenkf07771c2003-05-28 08:06:31 +0000241 /* round up region base address to multiple of size */
wdenkc6097192002-11-03 00:24:07 +0000242 mem = ((mem - 1) | (bar_size - 1)) + 1;
wdenkf07771c2003-05-28 08:06:31 +0000243 bar_value = mem;
244 /* compute new region base address */
245 mem = mem + bar_size;
wdenkc6097192002-11-03 00:24:07 +0000246 }
247
248 /* Write it out and update our limit */
Kumar Gala30e76d52008-10-21 08:36:08 -0500249 pci_hose_write_config_dword (hose, dev, bar, (u32)bar_value);
wdenkc6097192002-11-03 00:24:07 +0000250
wdenkf07771c2003-05-28 08:06:31 +0000251 if (found_mem64) {
wdenkc6097192002-11-03 00:24:07 +0000252 bar += 4;
Kumar Gala30e76d52008-10-21 08:36:08 -0500253#ifdef CONFIG_SYS_PCI_64BIT
Andrew Sharpcb2bf932012-08-29 14:16:29 +0000254 pci_hose_write_config_dword(hose, dev, bar,
255 (u32)(bar_value >> 32));
Kumar Gala30e76d52008-10-21 08:36:08 -0500256#else
Andrew Sharpcb2bf932012-08-29 14:16:29 +0000257 pci_hose_write_config_dword(hose, dev, bar, 0x00000000);
Kumar Gala30e76d52008-10-21 08:36:08 -0500258#endif
wdenkc6097192002-11-03 00:24:07 +0000259 }
260 }
261
262 /* Configure Cache Line Size Register */
Andrew Sharpcb2bf932012-08-29 14:16:29 +0000263 pci_hose_write_config_byte(hose, dev, PCI_CACHE_LINE_SIZE, 0x08);
wdenkc6097192002-11-03 00:24:07 +0000264
265 /* Configure Latency Timer */
Andrew Sharpcb2bf932012-08-29 14:16:29 +0000266 pci_hose_write_config_byte(hose, dev, PCI_LATENCY_TIMER, 0x80);
wdenkc6097192002-11-03 00:24:07 +0000267
268 /* Disable interrupt line, if device says it wants to use interrupts */
Andrew Sharpcb2bf932012-08-29 14:16:29 +0000269 pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &pin);
wdenkf07771c2003-05-28 08:06:31 +0000270 if (pin != 0) {
Simon Glass5f48d792015-07-27 15:47:17 -0600271 pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE,
272 PCI_INTERRUPT_LINE_DISABLE);
wdenkc6097192002-11-03 00:24:07 +0000273 }
274
Andrew Sharpcb2bf932012-08-29 14:16:29 +0000275 pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &old_command);
276 pci_hose_write_config_dword(hose, dev, PCI_COMMAND,
wdenkf07771c2003-05-28 08:06:31 +0000277 (old_command & 0xffff0000) | command);
wdenkc6097192002-11-03 00:24:07 +0000278
279 return 0;
280}
281
282/*
283 *
284 */
285
286struct pci_config_table *pci_find_config(struct pci_controller *hose,
287 unsigned short class,
288 unsigned int vendor,
289 unsigned int device,
290 unsigned int bus,
291 unsigned int dev,
292 unsigned int func)
293{
294 struct pci_config_table *table;
295
wdenkf07771c2003-05-28 08:06:31 +0000296 for (table = hose->config_table; table && table->vendor; table++) {
wdenkc6097192002-11-03 00:24:07 +0000297 if ((table->vendor == PCI_ANY_ID || table->vendor == vendor) &&
298 (table->device == PCI_ANY_ID || table->device == device) &&
299 (table->class == PCI_ANY_ID || table->class == class) &&
300 (table->bus == PCI_ANY_ID || table->bus == bus) &&
301 (table->dev == PCI_ANY_ID || table->dev == dev) &&
wdenkf07771c2003-05-28 08:06:31 +0000302 (table->func == PCI_ANY_ID || table->func == func)) {
wdenkc6097192002-11-03 00:24:07 +0000303 return table;
304 }
305 }
306
307 return NULL;
308}
309
310void pci_cfgfunc_config_device(struct pci_controller *hose,
311 pci_dev_t dev,
312 struct pci_config_table *entry)
313{
Andrew Sharpcb2bf932012-08-29 14:16:29 +0000314 pci_hose_config_device(hose, dev, entry->priv[0], entry->priv[1],
315 entry->priv[2]);
wdenkc6097192002-11-03 00:24:07 +0000316}
317
318void pci_cfgfunc_do_nothing(struct pci_controller *hose,
319 pci_dev_t dev, struct pci_config_table *entry)
320{
321}
322
323/*
Andrew Sharpcb2bf932012-08-29 14:16:29 +0000324 * HJF: Changed this to return int. I think this is required
wdenkc7de8292002-11-19 11:04:11 +0000325 * to get the correct result when scanning bridges
326 */
327extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);
wdenkc6097192002-11-03 00:24:07 +0000328
Stefan Roesedc1da422008-07-08 12:01:47 +0200329#ifdef CONFIG_PCI_SCAN_SHOW
Jeroen Hofstee7b19fd62014-10-08 22:57:27 +0200330__weak int pci_print_dev(struct pci_controller *hose, pci_dev_t dev)
Stefan Roesedc1da422008-07-08 12:01:47 +0200331{
332 if (dev == PCI_BDF(hose->first_busno, 0, 0))
333 return 0;
334
335 return 1;
336}
Stefan Roesedc1da422008-07-08 12:01:47 +0200337#endif /* CONFIG_PCI_SCAN_SHOW */
338
wdenkc6097192002-11-03 00:24:07 +0000339int pci_hose_scan_bus(struct pci_controller *hose, int bus)
340{
Andrew Sharpcb2bf932012-08-29 14:16:29 +0000341 unsigned int sub_bus, found_multi = 0;
wdenkc6097192002-11-03 00:24:07 +0000342 unsigned short vendor, device, class;
343 unsigned char header_type;
Andrew Sharp03992ac2012-08-29 14:16:30 +0000344#ifndef CONFIG_PCI_PNP
wdenkc6097192002-11-03 00:24:07 +0000345 struct pci_config_table *cfg;
Andrew Sharp03992ac2012-08-29 14:16:30 +0000346#endif
wdenkc6097192002-11-03 00:24:07 +0000347 pci_dev_t dev;
Peter Tyser009884a2010-10-29 17:59:29 -0500348#ifdef CONFIG_PCI_SCAN_SHOW
349 static int indent = 0;
350#endif
wdenkc6097192002-11-03 00:24:07 +0000351
352 sub_bus = bus;
353
354 for (dev = PCI_BDF(bus,0,0);
Andrew Sharpcb2bf932012-08-29 14:16:29 +0000355 dev < PCI_BDF(bus, PCI_MAX_PCI_DEVICES - 1,
356 PCI_MAX_PCI_FUNCTIONS - 1);
357 dev += PCI_BDF(0, 0, 1)) {
Stefan Roesedc1da422008-07-08 12:01:47 +0200358
359 if (pci_skip_dev(hose, dev))
360 continue;
wdenkc6097192002-11-03 00:24:07 +0000361
362 if (PCI_FUNC(dev) && !found_multi)
363 continue;
364
365 pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &header_type);
366
367 pci_hose_read_config_word(hose, dev, PCI_VENDOR_ID, &vendor);
368
Peter Tyser983eb9d2010-10-29 17:59:27 -0500369 if (vendor == 0xffff || vendor == 0x0000)
370 continue;
wdenkc6097192002-11-03 00:24:07 +0000371
Peter Tyser983eb9d2010-10-29 17:59:27 -0500372 if (!PCI_FUNC(dev))
373 found_multi = header_type & 0x80;
wdenkc6097192002-11-03 00:24:07 +0000374
Andrew Sharpcb2bf932012-08-29 14:16:29 +0000375 debug("PCI Scan: Found Bus %d, Device %d, Function %d\n",
376 PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev));
wdenkc6097192002-11-03 00:24:07 +0000377
Peter Tyser983eb9d2010-10-29 17:59:27 -0500378 pci_hose_read_config_word(hose, dev, PCI_DEVICE_ID, &device);
379 pci_hose_read_config_word(hose, dev, PCI_CLASS_DEVICE, &class);
wdenkc6097192002-11-03 00:24:07 +0000380
Tim Harvey09918662014-08-07 22:49:56 -0700381#ifdef CONFIG_PCI_FIXUP_DEV
382 board_pci_fixup_dev(hose, dev, vendor, device, class);
383#endif
384
Peter Tysera38d2162010-10-29 17:59:28 -0500385#ifdef CONFIG_PCI_SCAN_SHOW
Peter Tyser009884a2010-10-29 17:59:29 -0500386 indent++;
387
388 /* Print leading space, including bus indentation */
389 printf("%*c", indent + 1, ' ');
390
Peter Tysera38d2162010-10-29 17:59:28 -0500391 if (pci_print_dev(hose, dev)) {
Peter Tyser009884a2010-10-29 17:59:29 -0500392 printf("%02x:%02x.%-*x - %04x:%04x - %s\n",
393 PCI_BUS(dev), PCI_DEV(dev), 6 - indent, PCI_FUNC(dev),
Peter Tysera38d2162010-10-29 17:59:28 -0500394 vendor, device, pci_class_str(class >> 8));
395 }
396#endif
397
Andrew Sharp03992ac2012-08-29 14:16:30 +0000398#ifdef CONFIG_PCI_PNP
Masahiro Yamadab4141192014-11-07 03:03:31 +0900399 sub_bus = max((unsigned int)pciauto_config_device(hose, dev),
400 sub_bus);
Andrew Sharp03992ac2012-08-29 14:16:30 +0000401#else
Peter Tyser983eb9d2010-10-29 17:59:27 -0500402 cfg = pci_find_config(hose, class, vendor, device,
403 PCI_BUS(dev), PCI_DEV(dev), PCI_FUNC(dev));
404 if (cfg) {
405 cfg->config_device(hose, dev, cfg);
Masahiro Yamadab4141192014-11-07 03:03:31 +0900406 sub_bus = max(sub_bus,
407 (unsigned int)hose->current_busno);
wdenkc6097192002-11-03 00:24:07 +0000408 }
Andrew Sharp03992ac2012-08-29 14:16:30 +0000409#endif
Peter Tysera38d2162010-10-29 17:59:28 -0500410
Peter Tyser009884a2010-10-29 17:59:29 -0500411#ifdef CONFIG_PCI_SCAN_SHOW
412 indent--;
413#endif
414
Peter Tyser983eb9d2010-10-29 17:59:27 -0500415 if (hose->fixup_irq)
416 hose->fixup_irq(hose, dev);
wdenkc6097192002-11-03 00:24:07 +0000417 }
418
419 return sub_bus;
420}
421
422int pci_hose_scan(struct pci_controller *hose)
423{
Anatolij Gustschin0da1fb02011-10-11 22:44:30 +0000424#if defined(CONFIG_PCI_BOOTDELAY)
Anatolij Gustschin0da1fb02011-10-11 22:44:30 +0000425 char *s;
426 int i;
427
Bin Meng8f9052f2014-12-30 22:53:21 +0800428 if (!gd->pcidelay_done) {
Anatolij Gustschin0da1fb02011-10-11 22:44:30 +0000429 /* wait "pcidelay" ms (if defined)... */
Simon Glass00caae62017-08-03 12:22:12 -0600430 s = env_get("pcidelay");
Anatolij Gustschin0da1fb02011-10-11 22:44:30 +0000431 if (s) {
432 int val = simple_strtoul(s, NULL, 10);
433 for (i = 0; i < val; i++)
434 udelay(1000);
435 }
Bin Meng8f9052f2014-12-30 22:53:21 +0800436 gd->pcidelay_done = 1;
Anatolij Gustschin0da1fb02011-10-11 22:44:30 +0000437 }
438#endif /* CONFIG_PCI_BOOTDELAY */
439
Tim Harvey0373a7e2015-05-08 15:16:07 -0700440#ifdef CONFIG_PCI_SCAN_SHOW
441 puts("PCI:\n");
442#endif
443
Andrew Sharpcb2bf932012-08-29 14:16:29 +0000444 /*
445 * Start scan at current_busno.
Ed Swarthout40e81ad2007-07-11 14:51:35 -0500446 * PCIe will start scan at first_busno+1.
447 */
Andrew Sharpcb2bf932012-08-29 14:16:29 +0000448 /* For legacy support, ensure current >= first */
Ed Swarthout40e81ad2007-07-11 14:51:35 -0500449 if (hose->first_busno > hose->current_busno)
450 hose->current_busno = hose->first_busno;
wdenkc6097192002-11-03 00:24:07 +0000451#ifdef CONFIG_PCI_PNP
452 pciauto_config_init(hose);
453#endif
Ed Swarthout40e81ad2007-07-11 14:51:35 -0500454 return pci_hose_scan_bus(hose, hose->current_busno);
wdenkc6097192002-11-03 00:24:07 +0000455}
456
stroesead10dd92003-02-14 11:21:23 +0000457void pci_init(void)
458{
John Schmoller96d61602010-10-22 00:20:23 -0500459 hose_head = NULL;
460
Tim Harveyec21aee2016-06-17 06:20:25 -0700461 /* allow env to disable pci init/enum */
Simon Glass00caae62017-08-03 12:22:12 -0600462 if (env_get("pcidisable") != NULL)
Tim Harveyec21aee2016-06-17 06:20:25 -0700463 return;
464
stroesead10dd92003-02-14 11:21:23 +0000465 /* now call board specific pci_init()... */
466 pci_init_board();
467}
Zhao Qiang287df012013-10-12 13:46:33 +0800468
469/* Returns the address of the requested capability structure within the
470 * device's PCI configuration space or 0 in case the device does not
471 * support it.
472 * */
473int pci_hose_find_capability(struct pci_controller *hose, pci_dev_t dev,
474 int cap)
475{
476 int pos;
477 u8 hdr_type;
478
479 pci_hose_read_config_byte(hose, dev, PCI_HEADER_TYPE, &hdr_type);
480
481 pos = pci_hose_find_cap_start(hose, dev, hdr_type & 0x7F);
482
483 if (pos)
484 pos = pci_find_cap(hose, dev, pos, cap);
485
486 return pos;
487}
488
489/* Find the header pointer to the Capabilities*/
490int pci_hose_find_cap_start(struct pci_controller *hose, pci_dev_t dev,
491 u8 hdr_type)
492{
493 u16 status;
494
495 pci_hose_read_config_word(hose, dev, PCI_STATUS, &status);
496
497 if (!(status & PCI_STATUS_CAP_LIST))
498 return 0;
499
500 switch (hdr_type) {
501 case PCI_HEADER_TYPE_NORMAL:
502 case PCI_HEADER_TYPE_BRIDGE:
503 return PCI_CAPABILITY_LIST;
504 case PCI_HEADER_TYPE_CARDBUS:
505 return PCI_CB_CAPABILITY_LIST;
506 default:
507 return 0;
508 }
509}
510
511int pci_find_cap(struct pci_controller *hose, pci_dev_t dev, int pos, int cap)
512{
513 int ttl = PCI_FIND_CAP_TTL;
514 u8 id;
515 u8 next_pos;
516
517 while (ttl--) {
518 pci_hose_read_config_byte(hose, dev, pos, &next_pos);
519 if (next_pos < CAP_START_POS)
520 break;
521 next_pos &= ~3;
522 pos = (int) next_pos;
523 pci_hose_read_config_byte(hose, dev,
524 pos + PCI_CAP_LIST_ID, &id);
525 if (id == 0xff)
526 break;
527 if (id == cap)
528 return pos;
529 pos += PCI_CAP_LIST_NEXT;
530 }
531 return 0;
532}
Minghuan Lianed5b5802015-07-10 11:35:08 +0800533
534/**
535 * pci_find_next_ext_capability - Find an extended capability
536 *
537 * Returns the address of the next matching extended capability structure
538 * within the device's PCI configuration space or 0 if the device does
539 * not support it. Some capabilities can occur several times, e.g., the
540 * vendor-specific capability, and this provides a way to find them all.
541 */
542int pci_find_next_ext_capability(struct pci_controller *hose, pci_dev_t dev,
543 int start, int cap)
544{
545 u32 header;
546 int ttl, pos = PCI_CFG_SPACE_SIZE;
547
548 /* minimum 8 bytes per capability */
549 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
550
551 if (start)
552 pos = start;
553
554 pci_hose_read_config_dword(hose, dev, pos, &header);
555 if (header == 0xffffffff || header == 0)
556 return 0;
557
558 while (ttl-- > 0) {
559 if (PCI_EXT_CAP_ID(header) == cap && pos != start)
560 return pos;
561
562 pos = PCI_EXT_CAP_NEXT(header);
563 if (pos < PCI_CFG_SPACE_SIZE)
564 break;
565
566 pci_hose_read_config_dword(hose, dev, pos, &header);
567 if (header == 0xffffffff || header == 0)
568 break;
569 }
570
571 return 0;
572}
573
574/**
575 * pci_hose_find_ext_capability - Find an extended capability
576 *
577 * Returns the address of the requested extended capability structure
578 * within the device's PCI configuration space or 0 if the device does
579 * not support it.
580 */
581int pci_hose_find_ext_capability(struct pci_controller *hose, pci_dev_t dev,
582 int cap)
583{
584 return pci_find_next_ext_capability(hose, dev, 0, cap);
585}