blob: e013e725a8ddae2d09772121643398f3854b5c9f [file] [log] [blame]
Shengzhou Liu8d67c362014-03-05 15:04:48 +08001/*
2 * Copyright 2014 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7/*
8 * T2080 RDB/PCIe board configuration file
9 */
10
11#ifndef __T2080RDB_H
12#define __T2080RDB_H
13
14#define CONFIG_T2080RDB
15#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
16#define CONFIG_MMC
Shengzhou Liu8d67c362014-03-05 15:04:48 +080017#define CONFIG_USB_EHCI
18#define CONFIG_FSL_SATA_V2
19
20/* High Level Configuration Options */
Shengzhou Liu8d67c362014-03-05 15:04:48 +080021#define CONFIG_BOOKE
22#define CONFIG_E500 /* BOOKE e500 family */
23#define CONFIG_E500MC /* BOOKE e500mc family */
24#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
25#define CONFIG_MP /* support multiple processors */
26#define CONFIG_ENABLE_36BIT_PHYS
27
28#ifdef CONFIG_PHYS_64BIT
29#define CONFIG_ADDR_MAP 1
30#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
31#endif
32
33#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
34#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
35#define CONFIG_FSL_IFC /* Enable IFC Support */
Ruchika Gupta737537e2014-10-15 11:35:31 +053036#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
Shengzhou Liu8d67c362014-03-05 15:04:48 +080037#define CONFIG_ENV_OVERWRITE
38
39#ifdef CONFIG_RAMBOOT_PBL
Masahiro Yamadae4536f82014-03-11 11:05:16 +090040#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t208xrdb/t2080_pbi.cfg
Shengzhou Liu4d666682014-04-18 16:43:40 +080041
Shengzhou Liu4d666682014-04-18 16:43:40 +080042#define CONFIG_SPL_FLUSH_IMAGE
43#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
Shengzhou Liu4d666682014-04-18 16:43:40 +080044#define CONFIG_SYS_TEXT_BASE 0x00201000
45#define CONFIG_SPL_TEXT_BASE 0xFFFD8000
46#define CONFIG_SPL_PAD_TO 0x40000
47#define CONFIG_SPL_MAX_SIZE 0x28000
48#define RESET_VECTOR_OFFSET 0x27FFC
49#define BOOT_PAGE_OFFSET 0x27000
50#ifdef CONFIG_SPL_BUILD
51#define CONFIG_SPL_SKIP_RELOCATE
52#define CONFIG_SPL_COMMON_INIT_DDR
53#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
54#define CONFIG_SYS_NO_FLASH
Shengzhou Liu8d67c362014-03-05 15:04:48 +080055#endif
56
Shengzhou Liu4d666682014-04-18 16:43:40 +080057#ifdef CONFIG_NAND
Shengzhou Liu4d666682014-04-18 16:43:40 +080058#define CONFIG_SYS_NAND_U_BOOT_SIZE (768 << 10)
59#define CONFIG_SYS_NAND_U_BOOT_DST 0x00200000
60#define CONFIG_SYS_NAND_U_BOOT_START 0x00200000
61#define CONFIG_SYS_NAND_U_BOOT_OFFS (256 << 10)
62#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
Zhao Qiangec90ac72016-09-08 12:55:32 +080063#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_nand_rcw.cfg
Shengzhou Liu4d666682014-04-18 16:43:40 +080064#define CONFIG_SPL_NAND_BOOT
65#endif
66
67#ifdef CONFIG_SPIFLASH
68#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
Shengzhou Liu4d666682014-04-18 16:43:40 +080069#define CONFIG_SPL_SPI_FLASH_MINIMAL
70#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
71#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x00200000)
72#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x00200000)
73#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (256 << 10)
74#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
75#ifndef CONFIG_SPL_BUILD
76#define CONFIG_SYS_MPC85XX_NO_RESETVEC
77#endif
Zhao Qiangec90ac72016-09-08 12:55:32 +080078#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_spi_rcw.cfg
Shengzhou Liu4d666682014-04-18 16:43:40 +080079#define CONFIG_SPL_SPI_BOOT
80#endif
81
82#ifdef CONFIG_SDCARD
83#define CONFIG_RESET_VECTOR_ADDRESS 0x200FFC
Shengzhou Liu4d666682014-04-18 16:43:40 +080084#define CONFIG_SPL_MMC_MINIMAL
85#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
86#define CONFIG_SYS_MMC_U_BOOT_DST (0x00200000)
87#define CONFIG_SYS_MMC_U_BOOT_START (0x00200000)
88#define CONFIG_SYS_MMC_U_BOOT_OFFS (260 << 10)
89#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
90#ifndef CONFIG_SPL_BUILD
91#define CONFIG_SYS_MPC85XX_NO_RESETVEC
92#endif
Zhao Qiangec90ac72016-09-08 12:55:32 +080093#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t208xrdb/t2080_sd_rcw.cfg
Shengzhou Liu4d666682014-04-18 16:43:40 +080094#define CONFIG_SPL_MMC_BOOT
95#endif
96
97#endif /* CONFIG_RAMBOOT_PBL */
98
Shengzhou Liu8d67c362014-03-05 15:04:48 +080099#define CONFIG_SRIO_PCIE_BOOT_MASTER
100#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
101/* Set 1M boot space */
102#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
103#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
104 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
105#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
106#define CONFIG_SYS_NO_FLASH
107#endif
108
109#ifndef CONFIG_SYS_TEXT_BASE
110#define CONFIG_SYS_TEXT_BASE 0xeff40000
111#endif
112
113#ifndef CONFIG_RESET_VECTOR_ADDRESS
114#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
115#endif
116
117/*
118 * These can be toggled for performance analysis, otherwise use default.
119 */
120#define CONFIG_SYS_CACHE_STASHING
121#define CONFIG_BTB /* toggle branch predition */
122#define CONFIG_DDR_ECC
123#ifdef CONFIG_DDR_ECC
124#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
125#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
126#endif
127
Shengzhou Liu49132292015-03-27 15:53:14 +0800128#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
129#define CONFIG_SYS_MEMTEST_END 0x00400000
130#define CONFIG_SYS_ALT_MEMTEST
131
Shengzhou Liu4d666682014-04-18 16:43:40 +0800132#ifndef CONFIG_SYS_NO_FLASH
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800133#define CONFIG_FLASH_CFI_DRIVER
134#define CONFIG_SYS_FLASH_CFI
135#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
136#endif
137
138#if defined(CONFIG_SPIFLASH)
139#define CONFIG_SYS_EXTRA_ENV_RELOC
140#define CONFIG_ENV_IS_IN_SPI_FLASH
141#define CONFIG_ENV_SPI_BUS 0
142#define CONFIG_ENV_SPI_CS 0
143#define CONFIG_ENV_SPI_MAX_HZ 10000000
144#define CONFIG_ENV_SPI_MODE 0
145#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
146#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
147#define CONFIG_ENV_SECT_SIZE 0x10000
148#elif defined(CONFIG_SDCARD)
149#define CONFIG_SYS_EXTRA_ENV_RELOC
150#define CONFIG_ENV_IS_IN_MMC
151#define CONFIG_SYS_MMC_ENV_DEV 0
152#define CONFIG_ENV_SIZE 0x2000
Shengzhou Liu4d666682014-04-18 16:43:40 +0800153#define CONFIG_ENV_OFFSET (512 * 0x800)
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800154#elif defined(CONFIG_NAND)
155#define CONFIG_SYS_EXTRA_ENV_RELOC
156#define CONFIG_ENV_IS_IN_NAND
Shengzhou Liu4d666682014-04-18 16:43:40 +0800157#define CONFIG_ENV_SIZE 0x2000
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800158#define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE)
159#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
160#define CONFIG_ENV_IS_IN_REMOTE
161#define CONFIG_ENV_ADDR 0xffe20000
162#define CONFIG_ENV_SIZE 0x2000
163#elif defined(CONFIG_ENV_IS_NOWHERE)
164#define CONFIG_ENV_SIZE 0x2000
165#else
166#define CONFIG_ENV_IS_IN_FLASH
167#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
168#define CONFIG_ENV_SIZE 0x2000
169#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
170#endif
171
172#ifndef __ASSEMBLY__
173unsigned long get_board_sys_clk(void);
174unsigned long get_board_ddr_clk(void);
175#endif
176
177#define CONFIG_SYS_CLK_FREQ 66660000
178#define CONFIG_DDR_CLK_FREQ 133330000
179
180/*
181 * Config the L3 Cache as L3 SRAM
182 */
Shengzhou Liu4d666682014-04-18 16:43:40 +0800183#define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000
184#define CONFIG_SYS_L3_SIZE (512 << 10)
185#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
186#ifdef CONFIG_RAMBOOT_PBL
187#define CONFIG_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
188#endif
189#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SPL_GD_ADDR + 12 * 1024)
190#define CONFIG_SPL_RELOC_MALLOC_SIZE (50 << 10)
191#define CONFIG_SPL_RELOC_STACK (CONFIG_SPL_GD_ADDR + 64 * 1024)
192#define CONFIG_SPL_RELOC_STACK_SIZE (22 << 10)
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800193
194#define CONFIG_SYS_DCSRBAR 0xf0000000
195#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
196
197/* EEPROM */
198#define CONFIG_ID_EEPROM
199#define CONFIG_SYS_I2C_EEPROM_NXID
200#define CONFIG_SYS_EEPROM_BUS_NUM 0
201#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
Shengzhou Liuef531c72014-04-18 16:43:41 +0800202#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800203
204/*
205 * DDR Setup
206 */
207#define CONFIG_VERY_BIG_RAM
208#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
209#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
210#define CONFIG_DIMM_SLOTS_PER_CTLR 1
211#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
212#define CONFIG_DDR_SPD
213#define CONFIG_SYS_FSL_DDR3
214#undef CONFIG_FSL_DDR_INTERACTIVE
215#define CONFIG_SYS_SPD_BUS_NUM 0
216#define CONFIG_SYS_SDRAM_SIZE 2048 /* for fixed parameter use */
217#define SPD_EEPROM_ADDRESS1 0x51
218#define SPD_EEPROM_ADDRESS2 0x52
219#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1
220#define CTRL_INTLV_PREFERED cacheline
221
222/*
223 * IFC Definitions
224 */
225#define CONFIG_SYS_FLASH_BASE 0xe8000000
226#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
227#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
228#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
229 CSPR_PORT_SIZE_16 | \
230 CSPR_MSEL_NOR | \
231 CSPR_V)
232#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
233
234/* NOR Flash Timing Params */
235#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
236
237#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
238 FTIM0_NOR_TEADC(0x5) | \
239 FTIM0_NOR_TEAHC(0x5))
240#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
241 FTIM1_NOR_TRAD_NOR(0x1A) |\
242 FTIM1_NOR_TSEQRAD_NOR(0x13))
243#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
244 FTIM2_NOR_TCH(0x4) | \
245 FTIM2_NOR_TWPH(0x0E) | \
246 FTIM2_NOR_TWP(0x1c))
247#define CONFIG_SYS_NOR_FTIM3 0x0
248
249#define CONFIG_SYS_FLASH_QUIET_TEST
250#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
251
252#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
253#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
254#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
255#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
256#define CONFIG_SYS_FLASH_EMPTY_INFO
257#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS }
258
259/* CPLD on IFC */
260#define CONFIG_SYS_CPLD_BASE 0xffdf0000
261#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
262#define CONFIG_SYS_CSPR2_EXT (0xf)
263#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE) \
264 | CSPR_PORT_SIZE_8 \
265 | CSPR_MSEL_GPCM \
266 | CSPR_V)
267#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024)
268#define CONFIG_SYS_CSOR2 0x0
269
270/* CPLD Timing parameters for IFC CS2 */
271#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \
272 FTIM0_GPCM_TEADC(0x0e) | \
273 FTIM0_GPCM_TEAHC(0x0e))
274#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \
275 FTIM1_GPCM_TRAD(0x1f))
276#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \
Shaohui Xiede519162014-06-26 14:41:33 +0800277 FTIM2_GPCM_TCH(0x8) | \
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800278 FTIM2_GPCM_TWP(0x1f))
279#define CONFIG_SYS_CS2_FTIM3 0x0
280
281/* NAND Flash on IFC */
282#define CONFIG_NAND_FSL_IFC
283#define CONFIG_SYS_NAND_BASE 0xff800000
284#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
285
286#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
287#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
288 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
289 | CSPR_MSEL_NAND /* MSEL = NAND */ \
290 | CSPR_V)
291#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
292
293#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
294 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
295 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
296 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
297 | CSOR_NAND_PGS_2K /* Page Size = 2K */\
298 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */\
299 | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
300
301#define CONFIG_SYS_NAND_ONFI_DETECTION
302
303/* ONFI NAND Flash mode0 Timing Params */
304#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
305 FTIM0_NAND_TWP(0x18) | \
306 FTIM0_NAND_TWCHT(0x07) | \
307 FTIM0_NAND_TWH(0x0a))
308#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
309 FTIM1_NAND_TWBE(0x39) | \
310 FTIM1_NAND_TRR(0x0e) | \
311 FTIM1_NAND_TRP(0x18))
312#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
313 FTIM2_NAND_TREH(0x0a) | \
314 FTIM2_NAND_TWHRE(0x1e))
315#define CONFIG_SYS_NAND_FTIM3 0x0
316
317#define CONFIG_SYS_NAND_DDR_LAW 11
318#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
319#define CONFIG_SYS_MAX_NAND_DEVICE 1
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800320#define CONFIG_CMD_NAND
321#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
322
323#if defined(CONFIG_NAND)
324#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
325#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
326#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
327#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
328#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
329#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
330#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
331#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
332#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
333#define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
334#define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
335#define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
336#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
337#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
338#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
339#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
340#else
341#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
342#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
343#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
344#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
345#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
346#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
347#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
348#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
349#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
350#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
351#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
352#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
353#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
354#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
355#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
356#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
357#endif
358
359#if defined(CONFIG_RAMBOOT_PBL)
360#define CONFIG_SYS_RAMBOOT
361#endif
362
Shengzhou Liu4d666682014-04-18 16:43:40 +0800363#ifdef CONFIG_SPL_BUILD
364#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
365#else
366#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
367#endif
368
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800369#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
370#define CONFIG_MISC_INIT_R
371#define CONFIG_HWCONFIG
372
373/* define to use L1 as initial stack */
374#define CONFIG_L1_INIT_RAM
375#define CONFIG_SYS_INIT_RAM_LOCK
376#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
377#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
York Sunb3142e22015-08-17 13:31:51 -0700378#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800379/* The assembler doesn't like typecast */
380#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
381 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
382 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
383#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
384#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
385 GENERATED_GBL_DATA_SIZE)
386#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Prabhakar Kushwaha9307cba2014-03-31 15:31:48 +0530387#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800388#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
389
390/*
391 * Serial Port
392 */
393#define CONFIG_CONS_INDEX 1
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800394#define CONFIG_SYS_NS16550_SERIAL
395#define CONFIG_SYS_NS16550_REG_SIZE 1
396#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
397#define CONFIG_SYS_BAUDRATE_TABLE \
398 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
399#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
400#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
401#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
402#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
403
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800404/*
405 * I2C
406 */
407#define CONFIG_SYS_I2C
408#define CONFIG_SYS_I2C_FSL
409#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
410#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
411#define CONFIG_SYS_FSL_I2C3_SLAVE 0x7F
412#define CONFIG_SYS_FSL_I2C4_SLAVE 0x7F
413#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
414#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
415#define CONFIG_SYS_FSL_I2C3_OFFSET 0x119000
416#define CONFIG_SYS_FSL_I2C4_OFFSET 0x119100
417#define CONFIG_SYS_FSL_I2C_SPEED 100000
418#define CONFIG_SYS_FSL_I2C2_SPEED 100000
419#define CONFIG_SYS_FSL_I2C3_SPEED 100000
420#define CONFIG_SYS_FSL_I2C4_SPEED 100000
421#define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
422#define I2C_MUX_PCA_ADDR_SEC1 0x75 /* I2C bus multiplexer,secondary 1 */
423#define I2C_MUX_PCA_ADDR_SEC2 0x76 /* I2C bus multiplexer,secondary 2 */
424#define I2C_MUX_CH_DEFAULT 0x8
425
Ying Zhange5abb922015-03-10 14:21:36 +0800426#define I2C_MUX_CH_VOL_MONITOR 0xa
427
428#define CONFIG_VID_FLS_ENV "t208xrdb_vdd_mv"
429#ifndef CONFIG_SPL_BUILD
430#define CONFIG_VID
431#endif
432#define CONFIG_VOL_MONITOR_IR36021_SET
433#define CONFIG_VOL_MONITOR_IR36021_READ
434/* The lowest and highest voltage allowed for T208xRDB */
435#define VDD_MV_MIN 819
436#define VDD_MV_MAX 1212
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800437
438/*
439 * RapidIO
440 */
441#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000
442#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull
443#define CONFIG_SYS_SRIO1_MEM_SIZE 0x10000000 /* 256M */
444#define CONFIG_SYS_SRIO2_MEM_VIRT 0xb0000000
445#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc30000000ull
446#define CONFIG_SYS_SRIO2_MEM_SIZE 0x10000000 /* 256M */
447/*
448 * for slave u-boot IMAGE instored in master memory space,
449 * PHYS must be aligned based on the SIZE
450 */
Liu Gange4911812014-05-15 14:30:34 +0800451#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
452#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
453#define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000 /* 1M */
454#define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800455/*
456 * for slave UCODE and ENV instored in master memory space,
457 * PHYS must be aligned based on the SIZE
458 */
Liu Gange4911812014-05-15 14:30:34 +0800459#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800460#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
461#define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000 /* 256K */
462
463/* slave core release by master*/
464#define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
465#define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
466
467/*
468 * SRIO_PCIE_BOOT - SLAVE
469 */
470#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
471#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
472#define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
473 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
474#endif
475
476/*
477 * eSPI - Enhanced SPI
478 */
479#ifdef CONFIG_SPI_FLASH
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800480#define CONFIG_SPI_FLASH_BAR
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800481#define CONFIG_SF_DEFAULT_SPEED 10000000
482#define CONFIG_SF_DEFAULT_MODE 0
483#endif
484
485/*
486 * General PCI
487 * Memory space is mapped 1-1, but I/O space must start from 0.
488 */
Robert P. J. Dayb38eaec2016-05-03 19:52:49 -0400489#define CONFIG_PCIE1 /* PCIE controller 1 */
490#define CONFIG_PCIE2 /* PCIE controller 2 */
491#define CONFIG_PCIE3 /* PCIE controller 3 */
492#define CONFIG_PCIE4 /* PCIE controller 4 */
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800493#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
494#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
495/* controller 1, direct to uli, tgtid 3, Base address 20000 */
496#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
497#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
498#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
499#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
500#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
501#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
502#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
503#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
504
505/* controller 2, Slot 2, tgtid 2, Base address 201000 */
506#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
507#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
508#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
509#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */
510#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
511#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
512#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
513#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
514
515/* controller 3, Slot 1, tgtid 1, Base address 202000 */
516#define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000
517#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
518#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull
519#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */
520#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
521#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
522#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
523#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
524
525/* controller 4, Base address 203000 */
526#define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000
527#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
528#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull
529#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */
530#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
531#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
532#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
533
534#ifdef CONFIG_PCI
535#define CONFIG_PCI_INDIRECT_BRIDGE
536#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata LSZ ADD */
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800537#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
538#define CONFIG_DOS_PARTITION
539#endif
540
541/* Qman/Bman */
542#ifndef CONFIG_NOBQFMAN
543#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
544#define CONFIG_SYS_BMAN_NUM_PORTALS 18
545#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
546#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
547#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
Jeffrey Ladouceur3fa66db2014-12-08 14:54:01 -0500548#define CONFIG_SYS_BMAN_SP_CENA_SIZE 0x4000
549#define CONFIG_SYS_BMAN_SP_CINH_SIZE 0x1000
550#define CONFIG_SYS_BMAN_CENA_BASE CONFIG_SYS_BMAN_MEM_BASE
551#define CONFIG_SYS_BMAN_CENA_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
552#define CONFIG_SYS_BMAN_CINH_BASE (CONFIG_SYS_BMAN_MEM_BASE + \
553 CONFIG_SYS_BMAN_CENA_SIZE)
554#define CONFIG_SYS_BMAN_CINH_SIZE (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
555#define CONFIG_SYS_BMAN_SWP_ISDR_REG 0xE08
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800556#define CONFIG_SYS_QMAN_NUM_PORTALS 18
557#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
558#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
559#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
Jeffrey Ladouceur3fa66db2014-12-08 14:54:01 -0500560#define CONFIG_SYS_QMAN_SP_CENA_SIZE 0x4000
561#define CONFIG_SYS_QMAN_SP_CINH_SIZE 0x1000
562#define CONFIG_SYS_QMAN_CENA_BASE CONFIG_SYS_QMAN_MEM_BASE
563#define CONFIG_SYS_QMAN_CENA_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
564#define CONFIG_SYS_QMAN_CINH_BASE (CONFIG_SYS_QMAN_MEM_BASE + \
565 CONFIG_SYS_QMAN_CENA_SIZE)
566#define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
567#define CONFIG_SYS_QMAN_SWP_ISDR_REG 0xE08
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800568
569#define CONFIG_SYS_DPAA_FMAN
570#define CONFIG_SYS_DPAA_PME
571#define CONFIG_SYS_PMAN
572#define CONFIG_SYS_DPAA_DCE
573#define CONFIG_SYS_DPAA_RMAN /* RMan */
574#define CONFIG_SYS_INTERLAKEN
575
576/* Default address of microcode for the Linux Fman driver */
577#if defined(CONFIG_SPIFLASH)
578/*
579 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
580 * env, so we got 0x110000.
581 */
582#define CONFIG_SYS_QE_FW_IN_SPIFLASH
Shengzhou Liuef531c72014-04-18 16:43:41 +0800583#define CONFIG_SYS_CORTINA_FW_IN_SPIFLASH
584#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800585#define CONFIG_CORTINA_FW_ADDR 0x120000
586
587#elif defined(CONFIG_SDCARD)
588/*
589 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
Shengzhou Liu4d666682014-04-18 16:43:40 +0800590 * about 1MB (2048 blocks), Env is stored after the image, and the env size is
591 * 0x2000 (16 blocks), 8 + 2048 + 16 = 2072, enlarge it to 2080.
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800592 */
593#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
Shengzhou Liuef531c72014-04-18 16:43:41 +0800594#define CONFIG_SYS_CORTINA_FW_IN_MMC
Shengzhou Liu4d666682014-04-18 16:43:40 +0800595#define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
596#define CONFIG_CORTINA_FW_ADDR (512 * 0x8a0)
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800597
598#elif defined(CONFIG_NAND)
599#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
Shengzhou Liuef531c72014-04-18 16:43:41 +0800600#define CONFIG_SYS_CORTINA_FW_IN_NAND
Shengzhou Liu4d666682014-04-18 16:43:40 +0800601#define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
602#define CONFIG_CORTINA_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800603#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
604/*
605 * Slave has no ucode locally, it can fetch this from remote. When implementing
606 * in two corenet boards, slave's ucode could be stored in master's memory
607 * space, the address can be mapped from slave TLB->slave LAW->
608 * slave SRIO or PCIE outbound window->master inbound window->
609 * master LAW->the ucode address in master's memory space.
610 */
611#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
Shengzhou Liuef531c72014-04-18 16:43:41 +0800612#define CONFIG_SYS_CORTINA_FW_IN_REMOTE
613#define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800614#define CONFIG_CORTINA_FW_ADDR 0xFFE10000
615#else
616#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
Shengzhou Liuef531c72014-04-18 16:43:41 +0800617#define CONFIG_SYS_CORTINA_FW_IN_NOR
618#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800619#define CONFIG_CORTINA_FW_ADDR 0xEFE00000
620#endif
621#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
622#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
623#endif /* CONFIG_NOBQFMAN */
624
625#ifdef CONFIG_SYS_DPAA_FMAN
626#define CONFIG_FMAN_ENET
627#define CONFIG_PHYLIB_10G
Shengzhou Liu747aeda2015-04-08 11:12:15 +0800628#define CONFIG_PHY_AQUANTIA
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800629#define CONFIG_PHY_CORTINA
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800630#define CONFIG_PHY_REALTEK
631#define CONFIG_CORTINA_FW_LENGTH 0x40000
632#define RGMII_PHY1_ADDR 0x01 /* RealTek RTL8211E */
633#define RGMII_PHY2_ADDR 0x02
634#define CORTINA_PHY_ADDR1 0x0c /* Cortina CS4315 */
635#define CORTINA_PHY_ADDR2 0x0d
636#define FM1_10GEC3_PHY_ADDR 0x00 /* Aquantia AQ1202 10G Base-T */
637#define FM1_10GEC4_PHY_ADDR 0x01
638#endif
639
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800640#ifdef CONFIG_FMAN_ENET
641#define CONFIG_MII /* MII PHY management */
642#define CONFIG_ETHPRIME "FM1@DTSEC3"
643#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
644#endif
645
646/*
647 * SATA
648 */
649#ifdef CONFIG_FSL_SATA_V2
650#define CONFIG_LIBATA
651#define CONFIG_FSL_SATA
652#define CONFIG_SYS_SATA_MAX_DEVICE 2
653#define CONFIG_SATA1
654#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
655#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
656#define CONFIG_SATA2
657#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
658#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
659#define CONFIG_LBA48
660#define CONFIG_CMD_SATA
661#define CONFIG_DOS_PARTITION
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800662#endif
663
664/*
665 * USB
666 */
667#ifdef CONFIG_USB_EHCI
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800668#define CONFIG_USB_EHCI_FSL
669#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800670#define CONFIG_HAS_FSL_DR_USB
671#endif
672
673/*
674 * SDHC
675 */
676#ifdef CONFIG_MMC
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800677#define CONFIG_FSL_ESDHC
678#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
679#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
680#define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
681#define CONFIG_GENERIC_MMC
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800682#define CONFIG_DOS_PARTITION
683#endif
684
685/*
Shengzhou Liu4feac1c2014-04-02 14:28:35 +0800686 * Dynamic MTD Partition support with mtdparts
687 */
688#ifndef CONFIG_SYS_NO_FLASH
689#define CONFIG_MTD_DEVICE
690#define CONFIG_MTD_PARTITIONS
691#define CONFIG_CMD_MTDPARTS
692#define CONFIG_FLASH_CFI_MTD
693#define MTDIDS_DEFAULT "nor0=fe8000000.nor,nand0=fff800000.flash," \
694 "spi0=spife110000.1"
695#define MTDPARTS_DEFAULT "mtdparts=fe8000000.nor:1m(uboot),5m(kernel)," \
696 "128k(dtb),96m(fs),-(user);fff800000.flash:1m(uboot)," \
697 "5m(kernel),128k(dtb),96m(fs),-(user);spife110000.1:" \
698 "1m(uboot),5m(kernel),128k(dtb),-(user)"
699#endif
700
701/*
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800702 * Environment
703 */
704
705/*
706 * Command line configuration.
707 */
Shengzhou Liuc665c472014-04-24 11:10:09 +0800708#define CONFIG_CMD_ERRATA
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800709#define CONFIG_CMD_REGINFO
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800710
711#ifdef CONFIG_PCI
712#define CONFIG_CMD_PCI
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800713#endif
714
Ruchika Gupta737537e2014-10-15 11:35:31 +0530715/* Hash command with SHA acceleration supported in hardware */
716#ifdef CONFIG_FSL_CAAM
717#define CONFIG_CMD_HASH
718#define CONFIG_SHA_HW_ACCEL
719#endif
720
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800721/*
722 * Miscellaneous configurable options
723 */
724#define CONFIG_SYS_LONGHELP /* undef to save memory */
725#define CONFIG_CMDLINE_EDITING /* Command-line editing */
726#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
727#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800728#ifdef CONFIG_CMD_KGDB
729#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
730#else
731#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
732#endif
733#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
734#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
735#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800736
737/*
738 * For booting Linux, the board info and command line data
739 * have to be in the first 64 MB of memory, since this is
740 * the maximum mapped by the Linux kernel during initialization.
741 */
742#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
743#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
744
745#ifdef CONFIG_CMD_KGDB
746#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
747#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
748#endif
749
750/*
751 * Environment Configuration
752 */
753#define CONFIG_ROOTPATH "/opt/nfsroot"
754#define CONFIG_BOOTFILE "uImage"
755#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
756
757/* default location for tftp and bootm */
758#define CONFIG_LOADADDR 1000000
759#define CONFIG_BAUDRATE 115200
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800760#define __USB_PHY_TYPE utmi
761
762#define CONFIG_EXTRA_ENV_SETTINGS \
763 "hwconfig=fsl_ddr:" \
764 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
765 "bank_intlv=auto;" \
766 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
767 "netdev=eth0\0" \
768 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
769 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
770 "tftpflash=tftpboot $loadaddr $uboot && " \
771 "protect off $ubootaddr +$filesize && " \
772 "erase $ubootaddr +$filesize && " \
773 "cp.b $loadaddr $ubootaddr $filesize && " \
774 "protect on $ubootaddr +$filesize && " \
775 "cmp.b $loadaddr $ubootaddr $filesize\0" \
776 "consoledev=ttyS0\0" \
777 "ramdiskaddr=2000000\0" \
778 "ramdiskfile=t2080rdb/ramdisk.uboot\0" \
Scott Woodb24a4f62016-07-19 17:52:06 -0500779 "fdtaddr=1e00000\0" \
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800780 "fdtfile=t2080rdb/t2080rdb.dtb\0" \
Kim Phillips32465842014-05-14 19:33:45 -0500781 "bdev=sda3\0"
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800782
783/*
784 * For emulation this causes u-boot to jump to the start of the
785 * proof point app code automatically
786 */
787#define CONFIG_PROOF_POINTS \
788 "setenv bootargs root=/dev/$bdev rw " \
789 "console=$consoledev,$baudrate $othbootargs;" \
790 "cpu 1 release 0x29000000 - - -;" \
791 "cpu 2 release 0x29000000 - - -;" \
792 "cpu 3 release 0x29000000 - - -;" \
793 "cpu 4 release 0x29000000 - - -;" \
794 "cpu 5 release 0x29000000 - - -;" \
795 "cpu 6 release 0x29000000 - - -;" \
796 "cpu 7 release 0x29000000 - - -;" \
797 "go 0x29000000"
798
799#define CONFIG_HVBOOT \
800 "setenv bootargs config-addr=0x60000000; " \
801 "bootm 0x01000000 - 0x00f00000"
802
803#define CONFIG_ALU \
804 "setenv bootargs root=/dev/$bdev rw " \
805 "console=$consoledev,$baudrate $othbootargs;" \
806 "cpu 1 release 0x01000000 - - -;" \
807 "cpu 2 release 0x01000000 - - -;" \
808 "cpu 3 release 0x01000000 - - -;" \
809 "cpu 4 release 0x01000000 - - -;" \
810 "cpu 5 release 0x01000000 - - -;" \
811 "cpu 6 release 0x01000000 - - -;" \
812 "cpu 7 release 0x01000000 - - -;" \
813 "go 0x01000000"
814
815#define CONFIG_LINUX \
816 "setenv bootargs root=/dev/ram rw " \
817 "console=$consoledev,$baudrate $othbootargs;" \
818 "setenv ramdiskaddr 0x02000000;" \
819 "setenv fdtaddr 0x00c00000;" \
820 "setenv loadaddr 0x1000000;" \
821 "bootm $loadaddr $ramdiskaddr $fdtaddr"
822
823#define CONFIG_HDBOOT \
824 "setenv bootargs root=/dev/$bdev rw " \
825 "console=$consoledev,$baudrate $othbootargs;" \
826 "tftp $loadaddr $bootfile;" \
827 "tftp $fdtaddr $fdtfile;" \
828 "bootm $loadaddr - $fdtaddr"
829
830#define CONFIG_NFSBOOTCOMMAND \
831 "setenv bootargs root=/dev/nfs rw " \
832 "nfsroot=$serverip:$rootpath " \
833 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
834 "console=$consoledev,$baudrate $othbootargs;" \
835 "tftp $loadaddr $bootfile;" \
836 "tftp $fdtaddr $fdtfile;" \
837 "bootm $loadaddr - $fdtaddr"
838
839#define CONFIG_RAMBOOTCOMMAND \
840 "setenv bootargs root=/dev/ram rw " \
841 "console=$consoledev,$baudrate $othbootargs;" \
842 "tftp $ramdiskaddr $ramdiskfile;" \
843 "tftp $loadaddr $bootfile;" \
844 "tftp $fdtaddr $fdtfile;" \
845 "bootm $loadaddr $ramdiskaddr $fdtaddr"
846
847#define CONFIG_BOOTCOMMAND CONFIG_LINUX
848
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800849#include <asm/fsl_secure_boot.h>
Aneesh Bansalef6c55a2016-01-22 16:37:22 +0530850
Shengzhou Liu8d67c362014-03-05 15:04:48 +0800851#endif /* __T2080RDB_H */