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Aubrey.Li3f0606a2007-03-09 13:38:44 +08001/*
Bin Menga1875592016-02-05 19:30:11 -08002 * U-Boot - Configuration file for BF533 STAMP board
Aubrey.Li3f0606a2007-03-09 13:38:44 +08003 */
4
Mike Frysingercf6f4692008-06-01 09:09:48 -04005#ifndef __CONFIG_BF533_STAMP_H__
6#define __CONFIG_BF533_STAMP_H__
Aubrey.Li3f0606a2007-03-09 13:38:44 +08007
Mike Frysingerf348ab82009-04-24 17:22:40 -04008#include <asm/config-pre.h>
Mike Frysingerf7ce12c2008-02-18 05:26:48 -05009
Aubrey.Li3f0606a2007-03-09 13:38:44 +080010/*
Mike Frysingercf6f4692008-06-01 09:09:48 -040011 * Processor Settings
Aubrey.Li3f0606a2007-03-09 13:38:44 +080012 */
Mike Frysingerfbcf8e82010-12-23 14:58:37 -050013#define CONFIG_BFIN_CPU bf533-0.3
Mike Frysingercf6f4692008-06-01 09:09:48 -040014#define CONFIG_BFIN_BOOT_MODE BFIN_BOOT_BYPASS
15
Mike Frysingercf6f4692008-06-01 09:09:48 -040016/*
17 * Clock Settings
18 * CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
19 * SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
20 */
21/* CONFIG_CLKIN_HZ is any value in Hz */
22#define CONFIG_CLKIN_HZ 11059200
23/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
24/* 1 = CLKIN / 2 */
25#define CONFIG_CLKIN_HALF 0
26/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
27/* 1 = bypass PLL */
28#define CONFIG_PLL_BYPASS 0
29/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
30/* Values can range from 0-63 (where 0 means 64) */
Mike Frysinger9f64ba22008-10-12 23:49:13 -040031#define CONFIG_VCO_MULT 45
Mike Frysingercf6f4692008-06-01 09:09:48 -040032/* CCLK_DIV controls the core clock divider */
33/* Values can be 1, 2, 4, or 8 ONLY */
34#define CONFIG_CCLK_DIV 1
35/* SCLK_DIV controls the system clock divider */
36/* Values can range from 1-15 */
Mike Frysingerbaf35702009-07-10 10:42:06 -040037#define CONFIG_SCLK_DIV 6 /* note: 1.2 boards can go faster */
Mike Frysingercf6f4692008-06-01 09:09:48 -040038
Mike Frysingercf6f4692008-06-01 09:09:48 -040039/*
40 * Memory Settings
41 */
42#define CONFIG_MEM_ADD_WDTH 11
43#define CONFIG_MEM_SIZE 128
44
45#define CONFIG_EBIU_SDRRC_VAL 0x268
46#define CONFIG_EBIU_SDGCTL_VAL 0x911109
47
48#define CONFIG_EBIU_AMGCTL_VAL 0xFF
49#define CONFIG_EBIU_AMBCTL0_VAL 0xBBC3BBC3
50#define CONFIG_EBIU_AMBCTL1_VAL 0x99B39983
51
52#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
53#define CONFIG_SYS_MALLOC_LEN (384 * 1024)
54
Mike Frysingercf6f4692008-06-01 09:09:48 -040055/*
56 * Network Settings
57 */
58#define ADI_CMDS_NETWORK 1
Ben Warren7194ab82009-10-04 22:37:03 -070059#define CONFIG_SMC91111 1
Aubrey Li8db13d62007-03-10 23:49:29 +080060#define CONFIG_SMC91111_BASE 0x20300300
Mike Frysingercf6f4692008-06-01 09:09:48 -040061#define SMC91111_EEPROM_INIT() \
62 do { \
Ben Warren7194ab82009-10-04 22:37:03 -070063 bfin_write_FIO_DIR(bfin_read_FIO_DIR() | PF1 | PF0); \
64 bfin_write_FIO_FLAG_C(PF1); \
65 bfin_write_FIO_FLAG_S(PF0); \
Mike Frysingercf6f4692008-06-01 09:09:48 -040066 SSYNC(); \
67 } while (0)
68#define CONFIG_HOSTNAME bf533-stamp
Aubrey.Li3f0606a2007-03-09 13:38:44 +080069
Heiko Schocherea818db2013-01-29 08:53:15 +010070/* I2C */
71#define CONFIG_SYS_I2C
72#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
73#define CONFIG_SYS_I2C_SOFT_SPEED 50000
74#define CONFIG_SYS_I2C_SOFT_SLAVE 0
75/*
76 * Software (bit-bang) I2C driver configuration
77 */
Sonic Zhange5cb60a2013-11-18 18:59:18 +080078#define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF3
79#define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF2
Heiko Schocherea818db2013-01-29 08:53:15 +010080
Aubrey.Li3f0606a2007-03-09 13:38:44 +080081/*
Mike Frysingercf6f4692008-06-01 09:09:48 -040082 * Flash Settings
Aubrey.Li3f0606a2007-03-09 13:38:44 +080083 */
Mike Frysingercf6f4692008-06-01 09:09:48 -040084#define CONFIG_FLASH_CFI_DRIVER
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020085#define CONFIG_SYS_FLASH_BASE 0x20000000
Mike Frysingercf6f4692008-06-01 09:09:48 -040086#define CONFIG_SYS_FLASH_CFI
87#define CONFIG_SYS_FLASH_CFI_AMD_RESET
88#define CONFIG_SYS_MAX_FLASH_BANKS 1
89#define CONFIG_SYS_MAX_FLASH_SECT 67
Aubrey.Li3f0606a2007-03-09 13:38:44 +080090
Mike Frysingercf6f4692008-06-01 09:09:48 -040091/*
92 * SPI Settings
93 */
94#define CONFIG_BFIN_SPI
95#define CONFIG_ENV_SPI_MAX_HZ 30000000
Sonic Zhangc49eabe2014-07-17 19:00:29 +080096/*
Mike Frysingerafac8b02009-06-14 22:29:35 -040097#define CONFIG_SF_DEFAULT_SPEED 30000000
Mike Frysingerf4532202010-09-19 16:26:55 -040098#define CONFIG_SPI_FLASH_ALL
Sonic Zhangc49eabe2014-07-17 19:00:29 +080099*/
Mike Frysingercf6f4692008-06-01 09:09:48 -0400100
101/*
102 * Env Storage Settings
103 */
Mike Frysinger9171fc82008-03-30 15:46:13 -0400104#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
Mike Frysingercf6f4692008-06-01 09:09:48 -0400105#define CONFIG_ENV_IS_IN_SPI_FLASH
Vivi Libc43a8d2009-06-12 10:53:22 +0000106#define CONFIG_ENV_OFFSET 0x10000
Mike Frysingercf6f4692008-06-01 09:09:48 -0400107#define CONFIG_ENV_SIZE 0x2000
Vivi Libc43a8d2009-06-12 10:53:22 +0000108#define CONFIG_ENV_SECT_SIZE 0x10000
Mike Frysinger9171fc82008-03-30 15:46:13 -0400109#else
Mike Frysingercf6f4692008-06-01 09:09:48 -0400110#define CONFIG_ENV_IS_IN_FLASH
111#define CONFIG_ENV_OFFSET 0x4000
112#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
113#define CONFIG_ENV_SIZE 0x2000
114#define CONFIG_ENV_SECT_SIZE 0x2000
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800115#endif
Mike Frysingercf6f4692008-06-01 09:09:48 -0400116#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
117#define ENV_IS_EMBEDDED
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800118#else
Mike Frysinger76d82182009-07-21 22:17:36 -0400119#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800120#endif
Mike Frysinger9ff67e52009-06-14 06:29:07 -0400121#ifdef ENV_IS_EMBEDDED
122/* WARNING - the following is hand-optimized to fit within
123 * the sector before the environment sector. If it throws
124 * an error during compilation remove an object here to get
125 * it linked after the configuration sector.
126 */
127# define LDS_BOARD_TEXT \
Masahiro Yamadae2906a52013-11-11 14:36:00 +0900128 arch/blackfin/lib/built-in.o (.text*); \
129 arch/blackfin/cpu/built-in.o (.text*); \
Mike Frysinger9ff67e52009-06-14 06:29:07 -0400130 . = DEFINED(env_offset) ? env_offset : .; \
Mike Frysingerc70e7dd2010-11-19 19:28:56 -0500131 common/env_embedded.o (.text*);
Mike Frysinger9ff67e52009-06-14 06:29:07 -0400132#endif
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800133
Jon Loeligerba2351f2007-07-04 22:31:49 -0500134/*
Mike Frysingercf6f4692008-06-01 09:09:48 -0400135 * I2C Settings
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800136 */
Heiko Schocherea818db2013-01-29 08:53:15 +0100137#define CONFIG_SYS_I2C_SOFT
138#ifdef CONFIG_SYS_I2C_SOFT
139#define CONFIG_SYS_I2C
Mike Frysingerbeb60e72010-06-08 16:22:44 -0400140#define CONFIG_SOFT_I2C_GPIO_SCL GPIO_PF3
141#define CONFIG_SOFT_I2C_GPIO_SDA GPIO_PF2
Heiko Schocherea818db2013-01-29 08:53:15 +0100142#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
143#define CONFIG_SYS_I2C_SOFT_SPEED 50000
144#define CONFIG_SYS_I2C_SOFT_SLAVE 0
145#endif
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800146
147/*
Mike Frysingercf6f4692008-06-01 09:09:48 -0400148 * Compact Flash / IDE / ATA Settings
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800149 */
150
151/* Enabled below option for CF support */
Mike Frysingercf6f4692008-06-01 09:09:48 -0400152/* #define CONFIG_STAMP_CF */
153#if defined(CONFIG_STAMP_CF)
154#define CONFIG_MISC_INIT_R
Aubrey Li8db13d62007-03-10 23:49:29 +0800155#define CONFIG_DOS_PARTITION 1
Aubrey Li8db13d62007-03-10 23:49:29 +0800156#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
157#undef CONFIG_IDE_LED /* no led for ide supported */
158#undef CONFIG_IDE_RESET /* no reset for ide supported */
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800159
Mike Frysingercf6f4692008-06-01 09:09:48 -0400160#define CONFIG_SYS_IDE_MAXBUS 1
161#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS * 1)
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800162
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200163#define CONFIG_SYS_ATA_BASE_ADDR 0x20200000
164#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800165
Mike Frysingercf6f4692008-06-01 09:09:48 -0400166#define CONFIG_SYS_ATA_DATA_OFFSET 0x0020 /* data I/O */
167#define CONFIG_SYS_ATA_REG_OFFSET 0x0020 /* normal register accesses */
168#define CONFIG_SYS_ATA_ALT_OFFSET 0x0007 /* alternate registers */
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800169
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200170#define CONFIG_SYS_ATA_STRIDE 2
Mike Frysingercf6f4692008-06-01 09:09:48 -0400171
172#undef CONFIG_EBIU_AMBCTL1_VAL
173#define CONFIG_EBIU_AMBCTL1_VAL 0x99B3ffc2
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800174#endif
175
176/*
Mike Frysingercf6f4692008-06-01 09:09:48 -0400177 * Misc Settings
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800178 */
Mike Frysingercf6f4692008-06-01 09:09:48 -0400179#define CONFIG_RTC_BFIN
180#define CONFIG_UART_CONSOLE 0
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800181
Mike Frysingercf6f4692008-06-01 09:09:48 -0400182/* FLASH/ETHERNET uses the same async bank */
183#define SHARED_RESOURCES 1
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800184
Mike Frysinger23fd9592008-10-11 22:40:22 -0400185/* define to enable boot progress via leds */
186/* #define CONFIG_SHOW_BOOT_PROGRESS */
187
188/* define to enable run status via led */
189/* #define CONFIG_STATUS_LED */
190#ifdef CONFIG_STATUS_LED
Mike Frysingera84774f2010-06-02 05:12:11 -0400191#define CONFIG_GPIO_LED
Mike Frysinger23fd9592008-10-11 22:40:22 -0400192#define CONFIG_BOARD_SPECIFIC_LED
Mike Frysingera84774f2010-06-02 05:12:11 -0400193/* use LED0 to indicate booting/alive */
Mike Frysinger23fd9592008-10-11 22:40:22 -0400194#define STATUS_LED_BOOT 0
Mike Frysingera84774f2010-06-02 05:12:11 -0400195#define STATUS_LED_BIT GPIO_PF2
Mike Frysinger23fd9592008-10-11 22:40:22 -0400196#define STATUS_LED_STATE STATUS_LED_ON
197#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 4)
Mike Frysingera84774f2010-06-02 05:12:11 -0400198/* use LED1 to indicate crash */
Mike Frysinger23fd9592008-10-11 22:40:22 -0400199#define STATUS_LED_CRASH 1
Mike Frysingera84774f2010-06-02 05:12:11 -0400200#define STATUS_LED_BIT1 GPIO_PF3
Mike Frysinger23fd9592008-10-11 22:40:22 -0400201#define STATUS_LED_STATE1 STATUS_LED_ON
202#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2)
Mike Frysingera84774f2010-06-02 05:12:11 -0400203/* #define STATUS_LED_BIT2 GPIO_PF4 */
Mike Frysinger23fd9592008-10-11 22:40:22 -0400204#endif
205
Mike Frysingercf6f4692008-06-01 09:09:48 -0400206/* define to enable splash screen support */
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800207
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800208/*
Mike Frysingercf6f4692008-06-01 09:09:48 -0400209 * Pull in common ADI header for remaining command/environment setup
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800210 */
Mike Frysingercf6f4692008-06-01 09:09:48 -0400211#include <configs/bfin_adi_common.h>
Mike Frysinger9171fc82008-03-30 15:46:13 -0400212
Aubrey.Li3f0606a2007-03-09 13:38:44 +0800213#endif